2 cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #ifndef _POLARIS_REG_H_
23 #define _POLARIS_REG_H_
25 #define BOARD_CFG_STAT 0x0
26 #define TS_MODE_REG 0x4
27 #define TS1_CFG_REG 0x8
28 #define TS1_LENGTH_REG 0xc
29 #define TS2_CFG_REG 0x10
30 #define TS2_LENGTH_REG 0x14
31 #define EP_MODE_SET 0x18
32 #define CIR_PWR_PTN1 0x1c
33 #define CIR_PWR_PTN2 0x20
34 #define CIR_PWR_PTN3 0x24
35 #define CIR_PWR_MASK0 0x28
36 #define CIR_PWR_MASK1 0x2c
37 #define CIR_PWR_MASK2 0x30
39 #define CIR_CAR_REG 0x38
40 #define CIR_OT_CFG1 0x40
41 #define CIR_OT_CFG2 0x44
42 #define PWR_CTL_EN 0x74
44 /* Polaris Endpoints capture mask for register EP_MODE_SET */
45 #define ENABLE_EP1 0x01 /* Bit[0]=1 */
46 #define ENABLE_EP2 0x02 /* Bit[1]=1 */
47 #define ENABLE_EP3 0x04 /* Bit[2]=1 */
48 #define ENABLE_EP4 0x08 /* Bit[3]=1 */
49 #define ENABLE_EP5 0x10 /* Bit[4]=1 */
50 #define ENABLE_EP6 0x20 /* Bit[5]=1 */
52 /* Bit definition for register PWR_CTL_EN */
53 #define PWR_MODE_MASK 0x17f
54 #define PWR_AV_EN 0x08 /* bit3 */
55 #define PWR_ISO_EN 0x40 /* bit6 */
56 #define PWR_AV_MODE 0x30 /* bit4,5 */
57 #define PWR_TUNER_EN 0x04 /* bit2 */
58 #define PWR_DEMOD_EN 0x02 /* bit1 */
59 #define I2C_DEMOD_EN 0x01 /* bit0 */
60 #define PWR_RESETOUT_EN 0x100 /* bit8 */
63 POLARIS_AVMODE_DEFAULT = 0,
64 POLARIS_AVMODE_DIGITAL = 0x10,
65 POLARIS_AVMODE_ANALOGT_TV = 0x20,
66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
70 /* Colibri Registers */
72 #define SINGLE_ENDED 0x0
77 #define SUP_BLK_TUNE1 0x00
78 #define SUP_BLK_TUNE2 0x01
79 #define SUP_BLK_TUNE3 0x02
80 #define SUP_BLK_XTAL 0x03
81 #define SUP_BLK_PLL1 0x04
82 #define SUP_BLK_PLL2 0x05
83 #define SUP_BLK_PLL3 0x06
84 #define SUP_BLK_REF 0x07
85 #define SUP_BLK_PWRDN 0x08
86 #define SUP_BLK_TESTPAD 0x09
87 #define ADC_COM_INT5_STAB_REF 0x0a
88 #define ADC_COM_QUANT 0x0b
89 #define ADC_COM_BIAS1 0x0c
90 #define ADC_COM_BIAS2 0x0d
91 #define ADC_COM_BIAS3 0x0e
92 #define TESTBUS_CTRL 0x12
94 #define ADC_STATUS_CH1 0x20
95 #define ADC_STATUS_CH2 0x40
96 #define ADC_STATUS_CH3 0x60
98 #define ADC_STATUS2_CH1 0x21
99 #define ADC_STATUS2_CH2 0x41
100 #define ADC_STATUS2_CH3 0x61
102 #define ADC_CAL_ATEST_CH1 0x22
103 #define ADC_CAL_ATEST_CH2 0x42
104 #define ADC_CAL_ATEST_CH3 0x62
106 #define ADC_PWRDN_CLAMP_CH1 0x23
107 #define ADC_PWRDN_CLAMP_CH2 0x43
108 #define ADC_PWRDN_CLAMP_CH3 0x63
110 #define ADC_CTRL_DAC23_CH1 0x24
111 #define ADC_CTRL_DAC23_CH2 0x44
112 #define ADC_CTRL_DAC23_CH3 0x64
114 #define ADC_CTRL_DAC1_CH1 0x25
115 #define ADC_CTRL_DAC1_CH2 0x45
116 #define ADC_CTRL_DAC1_CH3 0x65
118 #define ADC_DCSERVO_DEM_CH1 0x26
119 #define ADC_DCSERVO_DEM_CH2 0x46
120 #define ADC_DCSERVO_DEM_CH3 0x66
122 #define ADC_FB_FRCRST_CH1 0x27
123 #define ADC_FB_FRCRST_CH2 0x47
124 #define ADC_FB_FRCRST_CH3 0x67
126 #define ADC_INPUT_CH1 0x28
127 #define ADC_INPUT_CH2 0x48
128 #define ADC_INPUT_CH3 0x68
129 #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
131 #define ADC_NTF_PRECLMP_EN_CH1 0x29
132 #define ADC_NTF_PRECLMP_EN_CH2 0x49
133 #define ADC_NTF_PRECLMP_EN_CH3 0x69
135 #define ADC_QGAIN_RES_TRM_CH1 0x2a
136 #define ADC_QGAIN_RES_TRM_CH2 0x4a
137 #define ADC_QGAIN_RES_TRM_CH3 0x6a
139 #define ADC_SOC_PRECLMP_TERM_CH1 0x2b
140 #define ADC_SOC_PRECLMP_TERM_CH2 0x4b
141 #define ADC_SOC_PRECLMP_TERM_CH3 0x6b
143 #define TESTBUS_CTRL_CH1 0x32
144 #define TESTBUS_CTRL_CH2 0x52
145 #define TESTBUS_CTRL_CH3 0x72
147 /******************************************************************************
149 ******************************************************************************/
150 #define DIRECT_IF_REVB_BASE 0x00300
152 /*****************************************************************************/
153 #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */
154 /*****************************************************************************/
155 #define FLD_DIF_PLL_LOCK 0x80000000
156 /* Reserved [30:29] */
157 #define FLD_DIF_PLL_FREE_RUN 0x10000000
158 #define FLD_DIF_PLL_FREQ 0x0FFFFFFF
160 /*****************************************************************************/
161 #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */
162 /*****************************************************************************/
163 #define FLD_DIF_KD_PD 0xFF000000
164 /* Reserved [23:20] */
165 #define FLD_DIF_KDS_PD 0x000F0000
166 #define FLD_DIF_KI_PD 0x0000FF00
168 #define FLD_DIF_KIS_PD 0x0000000F
170 /*****************************************************************************/
171 #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */
172 /*****************************************************************************/
173 #define FLD_DIF_KD_FD 0xFF000000
174 /* Reserved [23:20] */
175 #define FLD_DIF_KDS_FD 0x000F0000
176 #define FLD_DIF_KI_FD 0x0000FF00
177 #define FLD_DIF_SIG_PROP_SZ 0x000000F0
178 #define FLD_DIF_KIS_FD 0x0000000F
180 /*****************************************************************************/
181 #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */
182 /*****************************************************************************/
183 #define FLD_DIF_PLL_AGC_REF 0xFFF00000
184 #define FLD_DIF_PLL_AGC_KI 0x000F0000
186 #define FLD_DIF_FREQ_LIMIT 0x00007000
187 #define FLD_DIF_K_FD 0x00000F00
188 #define FLD_DIF_DOWNSMPL_FD 0x000000FF
190 /*****************************************************************************/
191 #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */
192 /*****************************************************************************/
193 /* Reserved [31:16] */
194 #define FLD_DIF_PLL_AGC_EN 0x00008000
195 /* Reserved [14:12] */
196 #define FLD_DIF_PLL_MAN_GAIN 0x00000FFF
198 /*****************************************************************************/
199 #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */
200 /*****************************************************************************/
201 #define FLD_DIF_K_AGC_RF 0xF0000000
202 #define FLD_DIF_K_AGC_IF 0x0F000000
203 #define FLD_DIF_K_AGC_INT 0x00F00000
204 /* Reserved [19:12] */
205 #define FLD_DIF_IF_REF 0x00000FFF
207 /*****************************************************************************/
208 #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */
209 /*****************************************************************************/
210 #define FLD_DIF_IF_MAX 0xFF000000
211 #define FLD_DIF_IF_MIN 0x00FF0000
212 #define FLD_DIF_IF_AGC 0x0000FFFF
214 /*****************************************************************************/
215 #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */
216 /*****************************************************************************/
217 #define FLD_DIF_INT_MAX 0xFF000000
218 #define FLD_DIF_INT_MIN 0x00FF0000
219 #define FLD_DIF_INT_AGC 0x0000FFFF
221 /*****************************************************************************/
222 #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */
223 /*****************************************************************************/
224 #define FLD_DIF_RF_MAX 0xFF000000
225 #define FLD_DIF_RF_MIN 0x00FF0000
226 #define FLD_DIF_RF_AGC 0x0000FFFF
228 /*****************************************************************************/
229 #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */
230 /*****************************************************************************/
231 #define FLD_DIF_IF_AGC_IN 0xFFFF0000
232 #define FLD_DIF_INT_AGC_IN 0x0000FFFF
234 /*****************************************************************************/
235 #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */
236 /*****************************************************************************/
237 /* Reserved [31:16] */
238 #define FLD_DIF_RF_AGC_IN 0x0000FFFF
240 /*****************************************************************************/
241 #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */
242 /*****************************************************************************/
243 #define FLD_DIF_AFD 0xC0000000
244 #define FLD_DIF_K_VID_AGC 0x30000000
245 #define FLD_DIF_LINE_LENGTH 0x0FFF0000
246 #define FLD_DIF_AGC_GAIN 0x0000FFFF
248 /*****************************************************************************/
249 #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */
250 /*****************************************************************************/
251 #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
252 /* Reserved [30:30] */
253 #define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000
254 /* Reserved [23:17] */
255 #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000
256 #define FLD_DIF_VID_MAN_GAIN 0x0000FFFF
258 /*****************************************************************************/
259 #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */
260 /*****************************************************************************/
261 #define FLD_DIF_LPF_FREQ 0xC0000000
262 #define FLD_DIF_AV_PHASE_INC 0x3F000000
263 #define FLD_DIF_AUDIO_FREQ 0x00FFFFFF
265 /*****************************************************************************/
266 #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */
267 /*****************************************************************************/
268 /* Reserved [31:24] */
269 #define FLD_DIF_IIR23_R2 0x00FF0000
270 #define FLD_DIF_IIR23_R1 0x0000FF00
271 #define FLD_DIF_IIR1_R1 0x000000FF
273 /*****************************************************************************/
274 #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */
275 /*****************************************************************************/
276 #define FLD_DIF_DIF_BYPASS 0x80000000
277 #define FLD_DIF_FM_NYQ_GAIN 0x40000000
278 #define FLD_DIF_RF_AGC_ENA 0x20000000
279 #define FLD_DIF_INT_AGC_ENA 0x10000000
280 #define FLD_DIF_IF_AGC_ENA 0x08000000
281 #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000
282 #define FLD_DIF_VIDEO_AGC_ENA 0x02000000
283 #define FLD_DIF_RF_AGC_INV 0x01000000
284 #define FLD_DIF_INT_AGC_INV 0x00800000
285 #define FLD_DIF_IF_AGC_INV 0x00400000
286 #define FLD_DIF_SPEC_INV 0x00200000
287 #define FLD_DIF_AUD_FULL_BW 0x00100000
288 #define FLD_DIF_AUD_SRC_SEL 0x00080000
290 #define FLD_DIF_IF_FREQ 0x00030000
291 /* Reserved [15:14] */
292 #define FLD_DIF_TIP_OFFSET 0x00003F00
294 #define FLD_DIF_DITHER_ENA 0x00000010
296 #define FLD_DIF_RF_IF_LOCK 0x00000001
298 /*****************************************************************************/
299 #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */
300 /*****************************************************************************/
301 /* Reserved [31:29] */
302 #define FLD_DIF_PHASE_INC 0x1FFFFFFF
304 /*****************************************************************************/
305 #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */
306 /*****************************************************************************/
307 /* Reserved [31:16] */
308 #define FLD_DIF_SRC_KI 0x0000FF00
309 #define FLD_DIF_SRC_KD 0x000000FF
311 /*****************************************************************************/
312 #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */
313 /*****************************************************************************/
314 /* Reserved [31:19] */
315 #define FLD_DIF_BPF_COEFF_0 0x00070000
316 /* Reserved [15:4] */
317 #define FLD_DIF_BPF_COEFF_1 0x0000000F
319 /*****************************************************************************/
320 #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */
321 /*****************************************************************************/
322 /* Reserved [31:22] */
323 #define FLD_DIF_BPF_COEFF_2 0x003F0000
324 /* Reserved [15:7] */
325 #define FLD_DIF_BPF_COEFF_3 0x0000007F
327 /*****************************************************************************/
328 #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */
329 /*****************************************************************************/
330 /* Reserved [31:24] */
331 #define FLD_DIF_BPF_COEFF_4 0x00FF0000
332 /* Reserved [15:8] */
333 #define FLD_DIF_BPF_COEFF_5 0x000000FF
335 /*****************************************************************************/
336 #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */
337 /*****************************************************************************/
338 /* Reserved [31:25] */
339 #define FLD_DIF_BPF_COEFF_6 0x01FF0000
340 /* Reserved [15:9] */
341 #define FLD_DIF_BPF_COEFF_7 0x000001FF
343 /*****************************************************************************/
344 #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */
345 /*****************************************************************************/
346 /* Reserved [31:26] */
347 #define FLD_DIF_BPF_COEFF_8 0x03FF0000
348 /* Reserved [15:10] */
349 #define FLD_DIF_BPF_COEFF_9 0x000003FF
351 /*****************************************************************************/
352 #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */
353 /*****************************************************************************/
354 /* Reserved [31:27] */
355 #define FLD_DIF_BPF_COEFF_10 0x07FF0000
356 /* Reserved [15:11] */
357 #define FLD_DIF_BPF_COEFF_11 0x000007FF
359 /*****************************************************************************/
360 #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */
361 /*****************************************************************************/
362 /* Reserved [31:27] */
363 #define FLD_DIF_BPF_COEFF_12 0x07FF0000
364 /* Reserved [15:12] */
365 #define FLD_DIF_BPF_COEFF_13 0x00000FFF
367 /*****************************************************************************/
368 #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */
369 /*****************************************************************************/
370 /* Reserved [31:28] */
371 #define FLD_DIF_BPF_COEFF_14 0x0FFF0000
372 /* Reserved [15:12] */
373 #define FLD_DIF_BPF_COEFF_15 0x00000FFF
375 /*****************************************************************************/
376 #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */
377 /*****************************************************************************/
378 /* Reserved [31:29] */
379 #define FLD_DIF_BPF_COEFF_16 0x1FFF0000
380 /* Reserved [15:13] */
381 #define FLD_DIF_BPF_COEFF_17 0x00001FFF
383 /*****************************************************************************/
384 #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */
385 /*****************************************************************************/
386 /* Reserved [31:29] */
387 #define FLD_DIF_BPF_COEFF_18 0x1FFF0000
388 /* Reserved [15:13] */
389 #define FLD_DIF_BPF_COEFF_19 0x00001FFF
391 /*****************************************************************************/
392 #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */
393 /*****************************************************************************/
394 /* Reserved [31:29] */
395 #define FLD_DIF_BPF_COEFF_20 0x1FFF0000
396 /* Reserved [15:14] */
397 #define FLD_DIF_BPF_COEFF_21 0x00003FFF
399 /*****************************************************************************/
400 #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */
401 /*****************************************************************************/
402 /* Reserved [31:30] */
403 #define FLD_DIF_BPF_COEFF_22 0x3FFF0000
404 /* Reserved [15:14] */
405 #define FLD_DIF_BPF_COEFF_23 0x00003FFF
407 /*****************************************************************************/
408 #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */
409 /*****************************************************************************/
410 /* Reserved [31:30] */
411 #define FLD_DIF_BPF_COEFF_24 0x3FFF0000
412 /* Reserved [15:14] */
413 #define FLD_DIF_BPF_COEFF_25 0x00003FFF
415 /*****************************************************************************/
416 #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */
417 /*****************************************************************************/
418 /* Reserved [31:30] */
419 #define FLD_DIF_BPF_COEFF_26 0x3FFF0000
420 /* Reserved [15:14] */
421 #define FLD_DIF_BPF_COEFF_27 0x00003FFF
423 /*****************************************************************************/
424 #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */
425 /*****************************************************************************/
426 /* Reserved [31:30] */
427 #define FLD_DIF_BPF_COEFF_28 0x3FFF0000
428 /* Reserved [15:14] */
429 #define FLD_DIF_BPF_COEFF_29 0x00003FFF
431 /*****************************************************************************/
432 #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */
433 /*****************************************************************************/
434 /* Reserved [31:30] */
435 #define FLD_DIF_BPF_COEFF_30 0x3FFF0000
436 /* Reserved [15:14] */
437 #define FLD_DIF_BPF_COEFF_31 0x00003FFF
439 /*****************************************************************************/
440 #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */
441 /*****************************************************************************/
442 /* Reserved [31:30] */
443 #define FLD_DIF_BPF_COEFF_32 0x3FFF0000
444 /* Reserved [15:14] */
445 #define FLD_DIF_BPF_COEFF_33 0x00003FFF
447 /*****************************************************************************/
448 #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */
449 /*****************************************************************************/
450 /* Reserved [31:30] */
451 #define FLD_DIF_BPF_COEFF_34 0x3FFF0000
452 /* Reserved [15:14] */
453 #define FLD_DIF_BPF_COEFF_35 0x00003FFF
455 /*****************************************************************************/
456 #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */
457 /*****************************************************************************/
458 /* Reserved [31:30] */
459 #define FLD_DIF_BPF_COEFF_36 0x3FFF0000
460 /* Reserved [15:0] */
462 /*****************************************************************************/
463 #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */
464 /*****************************************************************************/
465 /* Reserved [31:20] */
466 #define FLD_DIF_RPT_VARIANCE 0x000FFFFF
468 /*****************************************************************************/
469 #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */
470 /*****************************************************************************/
471 /* Reserved [31:8] */
472 #define FLD_DIF_DIF_SOFT_RST 0x00000080
473 #define FLD_DIF_DIF_REG_RST_MSK 0x00000040
474 #define FLD_DIF_AGC_RST_MSK 0x00000020
475 #define FLD_DIF_CMP_RST_MSK 0x00000010
476 #define FLD_DIF_AVS_RST_MSK 0x00000008
477 #define FLD_DIF_NYQ_RST_MSK 0x00000004
478 #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002
479 #define FLD_DIF_PLL_RST_MSK 0x00000001
481 /*****************************************************************************/
482 #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */
483 /*****************************************************************************/
484 /* Reserved [31:25] */
485 #define FLD_DIF_CTL_IP 0x01FFFFFF
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