Merge commit 'origin/master'
[linux-2.6] / arch / powerpc / boot / dts / mpc8572ds.dts
1 /*
2  * MPC8572 DS Device Tree Source
3  *
4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13 / {
14         model = "fsl,MPC8572DS";
15         compatible = "fsl,MPC8572DS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 ethernet2 = &enet2;
23                 ethernet3 = &enet3;
24                 serial0 = &serial0;
25                 serial1 = &serial1;
26                 pci0 = &pci0;
27                 pci1 = &pci1;
28                 pci2 = &pci2;
29         };
30
31         cpus {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34
35                 PowerPC,8572@0 {
36                         device_type = "cpu";
37                         reg = <0x0>;
38                         d-cache-line-size = <32>;       // 32 bytes
39                         i-cache-line-size = <32>;       // 32 bytes
40                         d-cache-size = <0x8000>;                // L1, 32K
41                         i-cache-size = <0x8000>;                // L1, 32K
42                         timebase-frequency = <0>;
43                         bus-frequency = <0>;
44                         clock-frequency = <0>;
45                         next-level-cache = <&L2>;
46                 };
47
48                 PowerPC,8572@1 {
49                         device_type = "cpu";
50                         reg = <0x1>;
51                         d-cache-line-size = <32>;       // 32 bytes
52                         i-cache-line-size = <32>;       // 32 bytes
53                         d-cache-size = <0x8000>;                // L1, 32K
54                         i-cache-size = <0x8000>;                // L1, 32K
55                         timebase-frequency = <0>;
56                         bus-frequency = <0>;
57                         clock-frequency = <0>;
58                         next-level-cache = <&L2>;
59                 };
60         };
61
62         memory {
63                 device_type = "memory";
64                 reg = <0x0 0x0>;        // Filled by U-Boot
65         };
66
67         soc8572@ffe00000 {
68                 #address-cells = <1>;
69                 #size-cells = <1>;
70                 device_type = "soc";
71                 ranges = <0x0 0xffe00000 0x100000>;
72                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
73                 bus-frequency = <0>;            // Filled out by uboot.
74
75                 memory-controller@2000 {
76                         compatible = "fsl,mpc8572-memory-controller";
77                         reg = <0x2000 0x1000>;
78                         interrupt-parent = <&mpic>;
79                         interrupts = <18 2>;
80                 };
81
82                 memory-controller@6000 {
83                         compatible = "fsl,mpc8572-memory-controller";
84                         reg = <0x6000 0x1000>;
85                         interrupt-parent = <&mpic>;
86                         interrupts = <18 2>;
87                 };
88
89                 L2: l2-cache-controller@20000 {
90                         compatible = "fsl,mpc8572-l2-cache-controller";
91                         reg = <0x20000 0x1000>;
92                         cache-line-size = <32>; // 32 bytes
93                         cache-size = <0x80000>; // L2, 512K
94                         interrupt-parent = <&mpic>;
95                         interrupts = <16 2>;
96                 };
97
98                 i2c@3000 {
99                         #address-cells = <1>;
100                         #size-cells = <0>;
101                         cell-index = <0>;
102                         compatible = "fsl-i2c";
103                         reg = <0x3000 0x100>;
104                         interrupts = <43 2>;
105                         interrupt-parent = <&mpic>;
106                         dfsrr;
107                 };
108
109                 i2c@3100 {
110                         #address-cells = <1>;
111                         #size-cells = <0>;
112                         cell-index = <1>;
113                         compatible = "fsl-i2c";
114                         reg = <0x3100 0x100>;
115                         interrupts = <43 2>;
116                         interrupt-parent = <&mpic>;
117                         dfsrr;
118                 };
119
120                 dma@c300 {
121                         #address-cells = <1>;
122                         #size-cells = <1>;
123                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
124                         reg = <0xc300 0x4>;
125                         ranges = <0x0 0xc100 0x200>;
126                         cell-index = <1>;
127                         dma-channel@0 {
128                                 compatible = "fsl,mpc8572-dma-channel",
129                                                 "fsl,eloplus-dma-channel";
130                                 reg = <0x0 0x80>;
131                                 cell-index = <0>;
132                                 interrupt-parent = <&mpic>;
133                                 interrupts = <76 2>;
134                         };
135                         dma-channel@80 {
136                                 compatible = "fsl,mpc8572-dma-channel",
137                                                 "fsl,eloplus-dma-channel";
138                                 reg = <0x80 0x80>;
139                                 cell-index = <1>;
140                                 interrupt-parent = <&mpic>;
141                                 interrupts = <77 2>;
142                         };
143                         dma-channel@100 {
144                                 compatible = "fsl,mpc8572-dma-channel",
145                                                 "fsl,eloplus-dma-channel";
146                                 reg = <0x100 0x80>;
147                                 cell-index = <2>;
148                                 interrupt-parent = <&mpic>;
149                                 interrupts = <78 2>;
150                         };
151                         dma-channel@180 {
152                                 compatible = "fsl,mpc8572-dma-channel",
153                                                 "fsl,eloplus-dma-channel";
154                                 reg = <0x180 0x80>;
155                                 cell-index = <3>;
156                                 interrupt-parent = <&mpic>;
157                                 interrupts = <79 2>;
158                         };
159                 };
160
161                 dma@21300 {
162                         #address-cells = <1>;
163                         #size-cells = <1>;
164                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
165                         reg = <0x21300 0x4>;
166                         ranges = <0x0 0x21100 0x200>;
167                         cell-index = <0>;
168                         dma-channel@0 {
169                                 compatible = "fsl,mpc8572-dma-channel",
170                                                 "fsl,eloplus-dma-channel";
171                                 reg = <0x0 0x80>;
172                                 cell-index = <0>;
173                                 interrupt-parent = <&mpic>;
174                                 interrupts = <20 2>;
175                         };
176                         dma-channel@80 {
177                                 compatible = "fsl,mpc8572-dma-channel",
178                                                 "fsl,eloplus-dma-channel";
179                                 reg = <0x80 0x80>;
180                                 cell-index = <1>;
181                                 interrupt-parent = <&mpic>;
182                                 interrupts = <21 2>;
183                         };
184                         dma-channel@100 {
185                                 compatible = "fsl,mpc8572-dma-channel",
186                                                 "fsl,eloplus-dma-channel";
187                                 reg = <0x100 0x80>;
188                                 cell-index = <2>;
189                                 interrupt-parent = <&mpic>;
190                                 interrupts = <22 2>;
191                         };
192                         dma-channel@180 {
193                                 compatible = "fsl,mpc8572-dma-channel",
194                                                 "fsl,eloplus-dma-channel";
195                                 reg = <0x180 0x80>;
196                                 cell-index = <3>;
197                                 interrupt-parent = <&mpic>;
198                                 interrupts = <23 2>;
199                         };
200                 };
201
202                 mdio@24520 {
203                         #address-cells = <1>;
204                         #size-cells = <0>;
205                         compatible = "fsl,gianfar-mdio";
206                         reg = <0x24520 0x20>;
207
208                         phy0: ethernet-phy@0 {
209                                 interrupt-parent = <&mpic>;
210                                 interrupts = <10 1>;
211                                 reg = <0x0>;
212                         };
213                         phy1: ethernet-phy@1 {
214                                 interrupt-parent = <&mpic>;
215                                 interrupts = <10 1>;
216                                 reg = <0x1>;
217                         };
218                         phy2: ethernet-phy@2 {
219                                 interrupt-parent = <&mpic>;
220                                 interrupts = <10 1>;
221                                 reg = <0x2>;
222                         };
223                         phy3: ethernet-phy@3 {
224                                 interrupt-parent = <&mpic>;
225                                 interrupts = <10 1>;
226                                 reg = <0x3>;
227                         };
228                 };
229
230                 enet0: ethernet@24000 {
231                         cell-index = <0>;
232                         device_type = "network";
233                         model = "eTSEC";
234                         compatible = "gianfar";
235                         reg = <0x24000 0x1000>;
236                         local-mac-address = [ 00 00 00 00 00 00 ];
237                         interrupts = <29 2 30 2 34 2>;
238                         interrupt-parent = <&mpic>;
239                         phy-handle = <&phy0>;
240                         phy-connection-type = "rgmii-id";
241                 };
242
243                 enet1: ethernet@25000 {
244                         cell-index = <1>;
245                         device_type = "network";
246                         model = "eTSEC";
247                         compatible = "gianfar";
248                         reg = <0x25000 0x1000>;
249                         local-mac-address = [ 00 00 00 00 00 00 ];
250                         interrupts = <35 2 36 2 40 2>;
251                         interrupt-parent = <&mpic>;
252                         phy-handle = <&phy1>;
253                         phy-connection-type = "rgmii-id";
254                 };
255
256                 enet2: ethernet@26000 {
257                         cell-index = <2>;
258                         device_type = "network";
259                         model = "eTSEC";
260                         compatible = "gianfar";
261                         reg = <0x26000 0x1000>;
262                         local-mac-address = [ 00 00 00 00 00 00 ];
263                         interrupts = <31 2 32 2 33 2>;
264                         interrupt-parent = <&mpic>;
265                         phy-handle = <&phy2>;
266                         phy-connection-type = "rgmii-id";
267                 };
268
269                 enet3: ethernet@27000 {
270                         cell-index = <3>;
271                         device_type = "network";
272                         model = "eTSEC";
273                         compatible = "gianfar";
274                         reg = <0x27000 0x1000>;
275                         local-mac-address = [ 00 00 00 00 00 00 ];
276                         interrupts = <37 2 38 2 39 2>;
277                         interrupt-parent = <&mpic>;
278                         phy-handle = <&phy3>;
279                         phy-connection-type = "rgmii-id";
280                 };
281
282                 serial0: serial@4500 {
283                         cell-index = <0>;
284                         device_type = "serial";
285                         compatible = "ns16550";
286                         reg = <0x4500 0x100>;
287                         clock-frequency = <0>;
288                         interrupts = <42 2>;
289                         interrupt-parent = <&mpic>;
290                 };
291
292                 serial1: serial@4600 {
293                         cell-index = <1>;
294                         device_type = "serial";
295                         compatible = "ns16550";
296                         reg = <0x4600 0x100>;
297                         clock-frequency = <0>;
298                         interrupts = <42 2>;
299                         interrupt-parent = <&mpic>;
300                 };
301
302                 global-utilities@e0000 {        //global utilities block
303                         compatible = "fsl,mpc8572-guts";
304                         reg = <0xe0000 0x1000>;
305                         fsl,has-rstcr;
306                 };
307
308                 msi@41600 {
309                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
310                         reg = <0x41600 0x80>;
311                         msi-available-ranges = <0 0x100>;
312                         interrupts = <
313                                 0xe0 0
314                                 0xe1 0
315                                 0xe2 0
316                                 0xe3 0
317                                 0xe4 0
318                                 0xe5 0
319                                 0xe6 0
320                                 0xe7 0>;
321                         interrupt-parent = <&mpic>;
322                 };
323
324                 crypto@30000 {
325                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
326                                      "fsl,sec2.1", "fsl,sec2.0";
327                         reg = <0x30000 0x10000>;
328                         interrupts = <45 2 58 2>;
329                         interrupt-parent = <&mpic>;
330                         fsl,num-channels = <4>;
331                         fsl,channel-fifo-len = <24>;
332                         fsl,exec-units-mask = <0x9fe>;
333                         fsl,descriptor-types-mask = <0x3ab0ebf>;
334                 };
335
336                 mpic: pic@40000 {
337                         interrupt-controller;
338                         #address-cells = <0>;
339                         #interrupt-cells = <2>;
340                         reg = <0x40000 0x40000>;
341                         compatible = "chrp,open-pic";
342                         device_type = "open-pic";
343                 };
344         };
345
346         pci0: pcie@ffe08000 {
347                 cell-index = <0>;
348                 compatible = "fsl,mpc8548-pcie";
349                 device_type = "pci";
350                 #interrupt-cells = <1>;
351                 #size-cells = <2>;
352                 #address-cells = <3>;
353                 reg = <0xffe08000 0x1000>;
354                 bus-range = <0 255>;
355                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
356                           0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
357                 clock-frequency = <33333333>;
358                 interrupt-parent = <&mpic>;
359                 interrupts = <24 2>;
360                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
361                 interrupt-map = <
362                         /* IDSEL 0x11 func 0 - PCI slot 1 */
363                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
364                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
365                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
366                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
367
368                         /* IDSEL 0x11 func 1 - PCI slot 1 */
369                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
370                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
371                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
372                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
373
374                         /* IDSEL 0x11 func 2 - PCI slot 1 */
375                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
376                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
377                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
378                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
379
380                         /* IDSEL 0x11 func 3 - PCI slot 1 */
381                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
382                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
383                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
384                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
385
386                         /* IDSEL 0x11 func 4 - PCI slot 1 */
387                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
388                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
389                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
390                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
391
392                         /* IDSEL 0x11 func 5 - PCI slot 1 */
393                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
394                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
395                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
396                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
397
398                         /* IDSEL 0x11 func 6 - PCI slot 1 */
399                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
400                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
401                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
402                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
403
404                         /* IDSEL 0x11 func 7 - PCI slot 1 */
405                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
406                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
407                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
408                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
409
410                         /* IDSEL 0x12 func 0 - PCI slot 2 */
411                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
412                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
413                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
414                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
415
416                         /* IDSEL 0x12 func 1 - PCI slot 2 */
417                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
418                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
419                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
420                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
421
422                         /* IDSEL 0x12 func 2 - PCI slot 2 */
423                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
424                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
425                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
426                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
427
428                         /* IDSEL 0x12 func 3 - PCI slot 2 */
429                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
430                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
431                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
432                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
433
434                         /* IDSEL 0x12 func 4 - PCI slot 2 */
435                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
436                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
437                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
438                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
439
440                         /* IDSEL 0x12 func 5 - PCI slot 2 */
441                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
442                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
443                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
444                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
445
446                         /* IDSEL 0x12 func 6 - PCI slot 2 */
447                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
448                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
449                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
450                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
451
452                         /* IDSEL 0x12 func 7 - PCI slot 2 */
453                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
454                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
455                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
456                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
457
458                         // IDSEL 0x1c  USB
459                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
460                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
461                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
462                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
463
464                         // IDSEL 0x1d  Audio
465                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
466
467                         // IDSEL 0x1e Legacy
468                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
469                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
470
471                         // IDSEL 0x1f IDE/SATA
472                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
473                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
474
475                         >;
476
477                 pcie@0 {
478                         reg = <0x0 0x0 0x0 0x0 0x0>;
479                         #size-cells = <2>;
480                         #address-cells = <3>;
481                         device_type = "pci";
482                         ranges = <0x2000000 0x0 0x80000000
483                                   0x2000000 0x0 0x80000000
484                                   0x0 0x20000000
485
486                                   0x1000000 0x0 0x0
487                                   0x1000000 0x0 0x0
488                                   0x0 0x100000>;
489                         uli1575@0 {
490                                 reg = <0x0 0x0 0x0 0x0 0x0>;
491                                 #size-cells = <2>;
492                                 #address-cells = <3>;
493                                 ranges = <0x2000000 0x0 0x80000000
494                                           0x2000000 0x0 0x80000000
495                                           0x0 0x20000000
496
497                                           0x1000000 0x0 0x0
498                                           0x1000000 0x0 0x0
499                                           0x0 0x100000>;
500                                 isa@1e {
501                                         device_type = "isa";
502                                         #interrupt-cells = <2>;
503                                         #size-cells = <1>;
504                                         #address-cells = <2>;
505                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
506                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
507                                                   0x1000>;
508                                         interrupt-parent = <&i8259>;
509
510                                         i8259: interrupt-controller@20 {
511                                                 reg = <0x1 0x20 0x2
512                                                        0x1 0xa0 0x2
513                                                        0x1 0x4d0 0x2>;
514                                                 interrupt-controller;
515                                                 device_type = "interrupt-controller";
516                                                 #address-cells = <0>;
517                                                 #interrupt-cells = <2>;
518                                                 compatible = "chrp,iic";
519                                                 interrupts = <9 2>;
520                                                 interrupt-parent = <&mpic>;
521                                         };
522
523                                         i8042@60 {
524                                                 #size-cells = <0>;
525                                                 #address-cells = <1>;
526                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
527                                                 interrupts = <1 3 12 3>;
528                                                 interrupt-parent =
529                                                         <&i8259>;
530
531                                                 keyboard@0 {
532                                                         reg = <0x0>;
533                                                         compatible = "pnpPNP,303";
534                                                 };
535
536                                                 mouse@1 {
537                                                         reg = <0x1>;
538                                                         compatible = "pnpPNP,f03";
539                                                 };
540                                         };
541
542                                         rtc@70 {
543                                                 compatible = "pnpPNP,b00";
544                                                 reg = <0x1 0x70 0x2>;
545                                         };
546
547                                         gpio@400 {
548                                                 reg = <0x1 0x400 0x80>;
549                                         };
550                                 };
551                         };
552                 };
553
554         };
555
556         pci1: pcie@ffe09000 {
557                 cell-index = <1>;
558                 compatible = "fsl,mpc8548-pcie";
559                 device_type = "pci";
560                 #interrupt-cells = <1>;
561                 #size-cells = <2>;
562                 #address-cells = <3>;
563                 reg = <0xffe09000 0x1000>;
564                 bus-range = <0 255>;
565                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
566                           0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
567                 clock-frequency = <33333333>;
568                 interrupt-parent = <&mpic>;
569                 interrupts = <26 2>;
570                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
571                 interrupt-map = <
572                         /* IDSEL 0x0 */
573                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
574                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
575                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
576                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
577                         >;
578                 pcie@0 {
579                         reg = <0x0 0x0 0x0 0x0 0x0>;
580                         #size-cells = <2>;
581                         #address-cells = <3>;
582                         device_type = "pci";
583                         ranges = <0x2000000 0x0 0xa0000000
584                                   0x2000000 0x0 0xa0000000
585                                   0x0 0x20000000
586
587                                   0x1000000 0x0 0x0
588                                   0x1000000 0x0 0x0
589                                   0x0 0x100000>;
590                 };
591         };
592
593         pci2: pcie@ffe0a000 {
594                 cell-index = <2>;
595                 compatible = "fsl,mpc8548-pcie";
596                 device_type = "pci";
597                 #interrupt-cells = <1>;
598                 #size-cells = <2>;
599                 #address-cells = <3>;
600                 reg = <0xffe0a000 0x1000>;
601                 bus-range = <0 255>;
602                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
603                           0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
604                 clock-frequency = <33333333>;
605                 interrupt-parent = <&mpic>;
606                 interrupts = <27 2>;
607                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
608                 interrupt-map = <
609                         /* IDSEL 0x0 */
610                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
611                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
612                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
613                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
614                         >;
615                 pcie@0 {
616                         reg = <0x0 0x0 0x0 0x0 0x0>;
617                         #size-cells = <2>;
618                         #address-cells = <3>;
619                         device_type = "pci";
620                         ranges = <0x2000000 0x0 0xc0000000
621                                   0x2000000 0x0 0xc0000000
622                                   0x0 0x20000000
623
624                                   0x1000000 0x0 0x0
625                                   0x1000000 0x0 0x0
626                                   0x0 0x100000>;
627                 };
628         };
629 };