git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 #define WAIT_FOR_BBP(__dev, __reg) \
  53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  54 #define WAIT_FOR_RF(__dev, __reg) \
  55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  56
  57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58                                 const unsigned int word, const u8 value)
  59 {
  60         u32 reg;
  61
  62         mutex_lock(&rt2x00dev->csr_mutex);
  63
  64         /*
  65          * Wait until the BBP becomes available, afterwards we
  66          * can safely write the new data into the register.
  67          */
  68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  69                 reg = 0;
  70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  74
  75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  76         }
  77
  78         mutex_unlock(&rt2x00dev->csr_mutex);
  79 }
  80
  81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  82                                const unsigned int word, u8 *value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the read request into the register.
  91          * After the data has been written, we wait until hardware
  92          * returns the correct value, if at any time the register
  93          * doesn't become available in time, reg will be 0xffffffff
  94          * which means we return 0xff to the caller.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 101
 102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 103
 104                 WAIT_FOR_BBP(rt2x00dev, &reg);
 105         }
 106
 107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 113                                const unsigned int word, const u32 value)
 114 {
 115         u32 reg;
 116
 117         if (!word)
 118                 return;
 119
 120         mutex_lock(&rt2x00dev->csr_mutex);
 121
 122         /*
 123          * Wait until the RF becomes available, afterwards we
 124          * can safely write the new data into the register.
 125          */
 126         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 127                 reg = 0;
 128                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 129                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 130                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 131                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 132
 133                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 134                 rt2x00_rf_write(rt2x00dev, word, value);
 135         }
 136
 137         mutex_unlock(&rt2x00dev->csr_mutex);
 138 }
 139
 140 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 141 {
 142         struct rt2x00_dev *rt2x00dev = eeprom->data;
 143         u32 reg;
 144
 145         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 146
 147         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 148         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 149         eeprom->reg_data_clock =
 150             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 151         eeprom->reg_chip_select =
 152             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 153 }
 154
 155 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 156 {
 157         struct rt2x00_dev *rt2x00dev = eeprom->data;
 158         u32 reg = 0;
 159
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 162         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 163                            !!eeprom->reg_data_clock);
 164         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 165                            !!eeprom->reg_chip_select);
 166
 167         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 168 }
 169
 170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 171 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 172         .owner  = THIS_MODULE,
 173         .csr    = {
 174                 .read           = rt2x00pci_register_read,
 175                 .write          = rt2x00pci_register_write,
 176                 .flags          = RT2X00DEBUGFS_OFFSET,
 177                 .word_base      = CSR_REG_BASE,
 178                 .word_size      = sizeof(u32),
 179                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 180         },
 181         .eeprom = {
 182                 .read           = rt2x00_eeprom_read,
 183                 .write          = rt2x00_eeprom_write,
 184                 .word_base      = EEPROM_BASE,
 185                 .word_size      = sizeof(u16),
 186                 .word_count     = EEPROM_SIZE / sizeof(u16),
 187         },
 188         .bbp    = {
 189                 .read           = rt2400pci_bbp_read,
 190                 .write          = rt2400pci_bbp_write,
 191                 .word_base      = BBP_BASE,
 192                 .word_size      = sizeof(u8),
 193                 .word_count     = BBP_SIZE / sizeof(u8),
 194         },
 195         .rf     = {
 196                 .read           = rt2x00_rf_read,
 197                 .write          = rt2400pci_rf_write,
 198                 .word_base      = RF_BASE,
 199                 .word_size      = sizeof(u32),
 200                 .word_count     = RF_SIZE / sizeof(u32),
 201         },
 202 };
 203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 204
 205 #ifdef CONFIG_RT2X00_LIB_RFKILL
 206 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 207 {
 208         u32 reg;
 209
 210         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 211         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 212 }
 213 #else
 214 #define rt2400pci_rfkill_poll   NULL
 215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 216
 217 #ifdef CONFIG_RT2X00_LIB_LEDS
 218 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 219                                      enum led_brightness brightness)
 220 {
 221         struct rt2x00_led *led =
 222             container_of(led_cdev, struct rt2x00_led, led_dev);
 223         unsigned int enabled = brightness != LED_OFF;
 224         u32 reg;
 225
 226         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 227
 228         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 229                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 230         else if (led->type == LED_TYPE_ACTIVITY)
 231                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 232
 233         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 234 }
 235
 236 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 237                                unsigned long *delay_on,
 238                                unsigned long *delay_off)
 239 {
 240         struct rt2x00_led *led =
 241             container_of(led_cdev, struct rt2x00_led, led_dev);
 242         u32 reg;
 243
 244         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 245         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 246         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 247         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 248
 249         return 0;
 250 }
 251
 252 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 253                                struct rt2x00_led *led,
 254                                enum led_type type)
 255 {
 256         led->rt2x00dev = rt2x00dev;
 257         led->type = type;
 258         led->led_dev.brightness_set = rt2400pci_brightness_set;
 259         led->led_dev.blink_set = rt2400pci_blink_set;
 260         led->flags = LED_INITIALIZED;
 261 }
 262 #endif /* CONFIG_RT2X00_LIB_LEDS */
 263
 264 /*
 265  * Configuration handlers.
 266  */
 267 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 268                                     const unsigned int filter_flags)
 269 {
 270         u32 reg;
 271
 272         /*
 273          * Start configuration steps.
 274          * Note that the version error will always be dropped
 275          * since there is no filter for it at this time.
 276          */
 277         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 279                            !(filter_flags & FIF_FCSFAIL));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 281                            !(filter_flags & FIF_PLCPFAIL));
 282         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 283                            !(filter_flags & FIF_CONTROL));
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 285                            !(filter_flags & FIF_PROMISC_IN_BSS));
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 287                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 288                            !rt2x00dev->intf_ap_count);
 289         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 290         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 291 }
 292
 293 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 294                                   struct rt2x00_intf *intf,
 295                                   struct rt2x00intf_conf *conf,
 296                                   const unsigned int flags)
 297 {
 298         unsigned int bcn_preload;
 299         u32 reg;
 300
 301         if (flags & CONFIG_UPDATE_TYPE) {
 302                 /*
 303                  * Enable beacon config
 304                  */
 305                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 306                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 307                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 309
 310                 /*
 311                  * Enable synchronisation.
 312                  */
 313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 318         }
 319
 320         if (flags & CONFIG_UPDATE_MAC)
 321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 322                                               conf->mac, sizeof(conf->mac));
 323
 324         if (flags & CONFIG_UPDATE_BSSID)
 325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 326                                               conf->bssid, sizeof(conf->bssid));
 327 }
 328
 329 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 330                                  struct rt2x00lib_erp *erp)
 331 {
 332         int preamble_mask;
 333         u32 reg;
 334
 335         /*
 336          * When short preamble is enabled, we should set bit 0x08
 337          */
 338         preamble_mask = erp->short_preamble << 3;
 339
 340         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 341         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 342                            erp->ack_timeout);
 343         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 344                            erp->ack_consume_time);
 345         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 346
 347         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 348         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 349         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 351         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 352
 353         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 354         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 355         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 357         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 358
 359         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 360         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 361         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 363         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 364
 365         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 366         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 367         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 369         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 370
 371         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 372
 373         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 374         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 375         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 378         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 379         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 380         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 381
 382         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 383         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 384         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 385         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 386 }
 387
 388 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 389                                  struct antenna_setup *ant)
 390 {
 391         u8 r1;
 392         u8 r4;
 393
 394         /*
 395          * We should never come here because rt2x00lib is supposed
 396          * to catch this and send us the correct antenna explicitely.
 397          */
 398         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 399                ant->tx == ANTENNA_SW_DIVERSITY);
 400
 401         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 402         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 403
 404         /*
 405          * Configure the TX antenna.
 406          */
 407         switch (ant->tx) {
 408         case ANTENNA_HW_DIVERSITY:
 409                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 410                 break;
 411         case ANTENNA_A:
 412                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 413                 break;
 414         case ANTENNA_B:
 415         default:
 416                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 417                 break;
 418         }
 419
 420         /*
 421          * Configure the RX antenna.
 422          */
 423         switch (ant->rx) {
 424         case ANTENNA_HW_DIVERSITY:
 425                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 426                 break;
 427         case ANTENNA_A:
 428                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 429                 break;
 430         case ANTENNA_B:
 431         default:
 432                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 433                 break;
 434         }
 435
 436         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 437         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 438 }
 439
 440 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 441                                      struct rf_channel *rf)
 442 {
 443         /*
 444          * Switch on tuning bits.
 445          */
 446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 448
 449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 450         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 451         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 452
 453         /*
 454          * RF2420 chipset don't need any additional actions.
 455          */
 456         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 457                 return;
 458
 459         /*
 460          * For the RT2421 chipsets we need to write an invalid
 461          * reference clock rate to activate auto_tune.
 462          * After that we set the value back to the correct channel.
 463          */
 464         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 465         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 466         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 467
 468         msleep(1);
 469
 470         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 471         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 472         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 473
 474         msleep(1);
 475
 476         /*
 477          * Switch off tuning bits.
 478          */
 479         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 480         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 481
 482         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 483         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 484
 485         /*
 486          * Clear false CRC during channel switch.
 487          */
 488         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 489 }
 490
 491 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 492 {
 493         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 494 }
 495
 496 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 497                                          struct rt2x00lib_conf *libconf)
 498 {
 499         u32 reg;
 500
 501         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 502         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 503                            libconf->conf->long_frame_max_tx_count);
 504         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 505                            libconf->conf->short_frame_max_tx_count);
 506         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 507 }
 508
 509 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 510                                       struct rt2x00lib_conf *libconf)
 511 {
 512         u32 reg;
 513
 514         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 515         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 516         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 517         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 518
 519         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 520         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 521                            libconf->conf->beacon_int * 16);
 522         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 523                            libconf->conf->beacon_int * 16);
 524         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 525 }
 526
 527 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
 528                                 struct rt2x00lib_conf *libconf)
 529 {
 530         enum dev_state state =
 531             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 532                 STATE_SLEEP : STATE_AWAKE;
 533         u32 reg;
 534
 535         if (state == STATE_SLEEP) {
 536                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 537                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 538                                    (libconf->conf->beacon_int - 20) * 16);
 539                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 540                                    libconf->conf->listen_interval - 1);
 541
 542                 /* We must first disable autowake before it can be enabled */
 543                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 544                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 545
 546                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 547                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 548         }
 549
 550         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 551 }
 552
 553 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 554                              struct rt2x00lib_conf *libconf,
 555                              const unsigned int flags)
 556 {
 557         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 558                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 559         if (flags & IEEE80211_CONF_CHANGE_POWER)
 560                 rt2400pci_config_txpower(rt2x00dev,
 561                                          libconf->conf->power_level);
 562         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 563                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
 564         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 565                 rt2400pci_config_duration(rt2x00dev, libconf);
 566         if (flags & IEEE80211_CONF_CHANGE_PS)
 567                 rt2400pci_config_ps(rt2x00dev, libconf);
 568 }
 569
 570 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 571                                 const int cw_min, const int cw_max)
 572 {
 573         u32 reg;
 574
 575         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 576         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 577         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 578         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 579 }
 580
 581 /*
 582  * Link tuning
 583  */
 584 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 585                                  struct link_qual *qual)
 586 {
 587         u32 reg;
 588         u8 bbp;
 589
 590         /*
 591          * Update FCS error count from register.
 592          */
 593         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 594         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 595
 596         /*
 597          * Update False CCA count from register.
 598          */
 599         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 600         qual->false_cca = bbp;
 601 }
 602
 603 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 604 {
 605         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 606         rt2x00dev->link.vgc_level = 0x08;
 607 }
 608
 609 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 610 {
 611         u8 reg;
 612
 613         /*
 614          * The link tuner should not run longer then 60 seconds,
 615          * and should run once every 2 seconds.
 616          */
 617         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 618                 return;
 619
 620         /*
 621          * Base r13 link tuning on the false cca count.
 622          */
 623         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 624
 625         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 626                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 627                 rt2x00dev->link.vgc_level = reg;
 628         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 629                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 630                 rt2x00dev->link.vgc_level = reg;
 631         }
 632 }
 633
 634 /*
 635  * Initialization functions.
 636  */
 637 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
 638 {
 639         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 640         u32 word;
 641
 642         if (entry->queue->qid == QID_RX) {
 643                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 644
 645                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 646         } else {
 647                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 648
 649                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 650                         rt2x00_get_field32(word, TXD_W0_VALID));
 651         }
 652 }
 653
 654 static void rt2400pci_clear_entry(struct queue_entry *entry)
 655 {
 656         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 657         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 658         u32 word;
 659
 660         if (entry->queue->qid == QID_RX) {
 661                 rt2x00_desc_read(entry_priv->desc, 2, &word);
 662                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 663                 rt2x00_desc_write(entry_priv->desc, 2, word);
 664
 665                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 666                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 667                 rt2x00_desc_write(entry_priv->desc, 1, word);
 668
 669                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 670                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 671                 rt2x00_desc_write(entry_priv->desc, 0, word);
 672         } else {
 673                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 674                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 675                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 676                 rt2x00_desc_write(entry_priv->desc, 0, word);
 677         }
 678 }
 679
 680 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 681 {
 682         struct queue_entry_priv_pci *entry_priv;
 683         u32 reg;
 684
 685         /*
 686          * Initialize registers.
 687          */
 688         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 689         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 690         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 691         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 692         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 693         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 694
 695         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 696         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 697         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 698                            entry_priv->desc_dma);
 699         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 700
 701         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 702         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 703         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 704                            entry_priv->desc_dma);
 705         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 706
 707         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 708         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 709         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 710                            entry_priv->desc_dma);
 711         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 712
 713         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 714         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 715         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 716                            entry_priv->desc_dma);
 717         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 718
 719         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 720         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 721         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 722         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 723
 724         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 725         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 726         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 727                            entry_priv->desc_dma);
 728         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 729
 730         return 0;
 731 }
 732
 733 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 734 {
 735         u32 reg;
 736
 737         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 738         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 739         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 740         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 741
 742         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 743         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 744         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 745         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 746         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 747
 748         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 749         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 750                            (rt2x00dev->rx->data_size / 128));
 751         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 752
 753         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 754         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 755         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 756         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 757         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 758         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 759         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 760         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 761         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 762         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 763
 764         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 765
 766         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 767         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 768         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 769         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 770         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 771         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 772
 773         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 774         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 775         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 776         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 777         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 779         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 780         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 781
 782         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 783
 784         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 785                 return -EBUSY;
 786
 787         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 788         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 789
 790         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 791         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 792         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 793
 794         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 795         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 796         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 797         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 798         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 799         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 800
 801         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 802         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 803         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 804         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 805         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 806
 807         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 808         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 809         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 810         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 811
 812         /*
 813          * We must clear the FCS and FIFO error count.
 814          * These registers are cleared on read,
 815          * so we may pass a useless variable to store the value.
 816          */
 817         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 818         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 819
 820         return 0;
 821 }
 822
 823 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 824 {
 825         unsigned int i;
 826         u8 value;
 827
 828         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 829                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 830                 if ((value != 0xff) && (value != 0x00))
 831                         return 0;
 832                 udelay(REGISTER_BUSY_DELAY);
 833         }
 834
 835         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 836         return -EACCES;
 837 }
 838
 839 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 840 {
 841         unsigned int i;
 842         u16 eeprom;
 843         u8 reg_id;
 844         u8 value;
 845
 846         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 847                 return -EACCES;
 848
 849         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 850         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 851         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 852         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 853         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 854         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 855         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 856         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 857         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 858         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 859         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 860         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 861         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 862         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 863
 864         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 866
 867                 if (eeprom != 0xffff && eeprom != 0x0000) {
 868                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 869                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 870                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 871                 }
 872         }
 873
 874         return 0;
 875 }
 876
 877 /*
 878  * Device state switch handlers.
 879  */
 880 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 881                                 enum dev_state state)
 882 {
 883         u32 reg;
 884
 885         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 886         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 887                            (state == STATE_RADIO_RX_OFF) ||
 888                            (state == STATE_RADIO_RX_OFF_LINK));
 889         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 890 }
 891
 892 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 893                                  enum dev_state state)
 894 {
 895         int mask = (state == STATE_RADIO_IRQ_OFF);
 896         u32 reg;
 897
 898         /*
 899          * When interrupts are being enabled, the interrupt registers
 900          * should clear the register to assure a clean state.
 901          */
 902         if (state == STATE_RADIO_IRQ_ON) {
 903                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 904                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 905         }
 906
 907         /*
 908          * Only toggle the interrupts bits we are going to use.
 909          * Non-checked interrupt bits are disabled by default.
 910          */
 911         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 912         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 913         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 914         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 915         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 916         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 917         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 918 }
 919
 920 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 921 {
 922         /*
 923          * Initialize all registers.
 924          */
 925         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 926                      rt2400pci_init_registers(rt2x00dev) ||
 927                      rt2400pci_init_bbp(rt2x00dev)))
 928                 return -EIO;
 929
 930         return 0;
 931 }
 932
 933 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 934 {
 935         u32 reg;
 936
 937         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 938
 939         /*
 940          * Disable synchronisation.
 941          */
 942         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 943
 944         /*
 945          * Cancel RX and TX.
 946          */
 947         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 948         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 949         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 950 }
 951
 952 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 953                                enum dev_state state)
 954 {
 955         u32 reg;
 956         unsigned int i;
 957         char put_to_sleep;
 958         char bbp_state;
 959         char rf_state;
 960
 961         put_to_sleep = (state != STATE_AWAKE);
 962
 963         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 964         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 965         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 966         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 967         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 968         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 969
 970         /*
 971          * Device is not guaranteed to be in the requested state yet.
 972          * We must wait until the register indicates that the
 973          * device has entered the correct state.
 974          */
 975         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 976                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 977                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 978                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 979                 if (bbp_state == state && rf_state == state)
 980                         return 0;
 981                 msleep(10);
 982         }
 983
 984         return -EBUSY;
 985 }
 986
 987 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 988                                       enum dev_state state)
 989 {
 990         int retval = 0;
 991
 992         switch (state) {
 993         case STATE_RADIO_ON:
 994                 retval = rt2400pci_enable_radio(rt2x00dev);
 995                 break;
 996         case STATE_RADIO_OFF:
 997                 rt2400pci_disable_radio(rt2x00dev);
 998                 break;
 999         case STATE_RADIO_RX_ON:
1000         case STATE_RADIO_RX_ON_LINK:
1001         case STATE_RADIO_RX_OFF:
1002         case STATE_RADIO_RX_OFF_LINK:
1003                 rt2400pci_toggle_rx(rt2x00dev, state);
1004                 break;
1005         case STATE_RADIO_IRQ_ON:
1006         case STATE_RADIO_IRQ_OFF:
1007                 rt2400pci_toggle_irq(rt2x00dev, state);
1008                 break;
1009         case STATE_DEEP_SLEEP:
1010         case STATE_SLEEP:
1011         case STATE_STANDBY:
1012         case STATE_AWAKE:
1013                 retval = rt2400pci_set_state(rt2x00dev, state);
1014                 break;
1015         default:
1016                 retval = -ENOTSUPP;
1017                 break;
1018         }
1019
1020         if (unlikely(retval))
1021                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1022                       state, retval);
1023
1024         return retval;
1025 }
1026
1027 /*
1028  * TX descriptor initialization
1029  */
1030 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1031                                     struct sk_buff *skb,
1032                                     struct txentry_desc *txdesc)
1033 {
1034         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1035         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1036         __le32 *txd = skbdesc->desc;
1037         u32 word;
1038
1039         /*
1040          * Start writing the descriptor words.
1041          */
1042         rt2x00_desc_read(entry_priv->desc, 1, &word);
1043         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1044         rt2x00_desc_write(entry_priv->desc, 1, word);
1045
1046         rt2x00_desc_read(txd, 2, &word);
1047         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1048         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1049         rt2x00_desc_write(txd, 2, word);
1050
1051         rt2x00_desc_read(txd, 3, &word);
1052         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1053         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1054         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1055         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1056         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1057         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1058         rt2x00_desc_write(txd, 3, word);
1059
1060         rt2x00_desc_read(txd, 4, &word);
1061         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1062         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1063         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1064         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1065         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1066         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1067         rt2x00_desc_write(txd, 4, word);
1068
1069         rt2x00_desc_read(txd, 0, &word);
1070         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1071         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1072         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1073                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1074         rt2x00_set_field32(&word, TXD_W0_ACK,
1075                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1076         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1077                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1078         rt2x00_set_field32(&word, TXD_W0_RTS,
1079                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1080         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1081         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1082                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1083         rt2x00_desc_write(txd, 0, word);
1084 }
1085
1086 /*
1087  * TX data initialization
1088  */
1089 static void rt2400pci_write_beacon(struct queue_entry *entry)
1090 {
1091         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1092         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1093         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1094         u32 word;
1095         u32 reg;
1096
1097         /*
1098          * Disable beaconing while we are reloading the beacon data,
1099          * otherwise we might be sending out invalid data.
1100          */
1101         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1102         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1103         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1104         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1105         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1106
1107         /*
1108          * Replace rt2x00lib allocated descriptor with the
1109          * pointer to the _real_ hardware descriptor.
1110          * After that, map the beacon to DMA and update the
1111          * descriptor.
1112          */
1113         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1114         skbdesc->desc = entry_priv->desc;
1115
1116         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1117
1118         rt2x00_desc_read(entry_priv->desc, 1, &word);
1119         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1120         rt2x00_desc_write(entry_priv->desc, 1, word);
1121 }
1122
1123 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1124                                     const enum data_queue_qid queue)
1125 {
1126         u32 reg;
1127
1128         if (queue == QID_BEACON) {
1129                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1130                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1131                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1132                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1133                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1134                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1135                 }
1136                 return;
1137         }
1138
1139         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1140         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1141         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1142         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1143         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1144 }
1145
1146 /*
1147  * RX control handlers
1148  */
1149 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1150                                   struct rxdone_entry_desc *rxdesc)
1151 {
1152         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1153         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1154         u32 word0;
1155         u32 word2;
1156         u32 word3;
1157         u32 word4;
1158         u64 tsf;
1159         u32 rx_low;
1160         u32 rx_high;
1161
1162         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1163         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1164         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1165         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1166
1167         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1168                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1169         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1170                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1171
1172         /*
1173          * We only get the lower 32bits from the timestamp,
1174          * to get the full 64bits we must complement it with
1175          * the timestamp from get_tsf().
1176          * Note that when a wraparound of the lower 32bits
1177          * has occurred between the frame arrival and the get_tsf()
1178          * call, we must decrease the higher 32bits with 1 to get
1179          * to correct value.
1180          */
1181         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1182         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1183         rx_high = upper_32_bits(tsf);
1184
1185         if ((u32)tsf <= rx_low)
1186                 rx_high--;
1187
1188         /*
1189          * Obtain the status about this packet.
1190          * The signal is the PLCP value, and needs to be stripped
1191          * of the preamble bit (0x08).
1192          */
1193         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1194         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1195         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1196             entry->queue->rt2x00dev->rssi_offset;
1197         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1198
1199         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1200         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1201                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1202 }
1203
1204 /*
1205  * Interrupt functions.
1206  */
1207 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1208                              const enum data_queue_qid queue_idx)
1209 {
1210         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1211         struct queue_entry_priv_pci *entry_priv;
1212         struct queue_entry *entry;
1213         struct txdone_entry_desc txdesc;
1214         u32 word;
1215
1216         while (!rt2x00queue_empty(queue)) {
1217                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1218                 entry_priv = entry->priv_data;
1219                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1220
1221                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1222                     !rt2x00_get_field32(word, TXD_W0_VALID))
1223                         break;
1224
1225                 /*
1226                  * Obtain the status about this packet.
1227                  */
1228                 txdesc.flags = 0;
1229                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1230                 case 0: /* Success */
1231                 case 1: /* Success with retry */
1232                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1233                         break;
1234                 case 2: /* Failure, excessive retries */
1235                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1236                         /* Don't break, this is a failed frame! */
1237                 default: /* Failure */
1238                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1239                 }
1240                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1241
1242                 rt2x00lib_txdone(entry, &txdesc);
1243         }
1244 }
1245
1246 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1247 {
1248         struct rt2x00_dev *rt2x00dev = dev_instance;
1249         u32 reg;
1250
1251         /*
1252          * Get the interrupt sources & saved to local variable.
1253          * Write register value back to clear pending interrupts.
1254          */
1255         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1256         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1257
1258         if (!reg)
1259                 return IRQ_NONE;
1260
1261         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1262                 return IRQ_HANDLED;
1263
1264         /*
1265          * Handle interrupts, walk through all bits
1266          * and run the tasks, the bits are checked in order of
1267          * priority.
1268          */
1269
1270         /*
1271          * 1 - Beacon timer expired interrupt.
1272          */
1273         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1274                 rt2x00lib_beacondone(rt2x00dev);
1275
1276         /*
1277          * 2 - Rx ring done interrupt.
1278          */
1279         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1280                 rt2x00pci_rxdone(rt2x00dev);
1281
1282         /*
1283          * 3 - Atim ring transmit done interrupt.
1284          */
1285         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1286                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1287
1288         /*
1289          * 4 - Priority ring transmit done interrupt.
1290          */
1291         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1292                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1293
1294         /*
1295          * 5 - Tx ring transmit done interrupt.
1296          */
1297         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1298                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1299
1300         return IRQ_HANDLED;
1301 }
1302
1303 /*
1304  * Device probe functions.
1305  */
1306 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1307 {
1308         struct eeprom_93cx6 eeprom;
1309         u32 reg;
1310         u16 word;
1311         u8 *mac;
1312
1313         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1314
1315         eeprom.data = rt2x00dev;
1316         eeprom.register_read = rt2400pci_eepromregister_read;
1317         eeprom.register_write = rt2400pci_eepromregister_write;
1318         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1319             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1320         eeprom.reg_data_in = 0;
1321         eeprom.reg_data_out = 0;
1322         eeprom.reg_data_clock = 0;
1323         eeprom.reg_chip_select = 0;
1324
1325         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1326                                EEPROM_SIZE / sizeof(u16));
1327
1328         /*
1329          * Start validation of the data that has been read.
1330          */
1331         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1332         if (!is_valid_ether_addr(mac)) {
1333                 random_ether_addr(mac);
1334                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1335         }
1336
1337         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1338         if (word == 0xffff) {
1339                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1340                 return -EINVAL;
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1347 {
1348         u32 reg;
1349         u16 value;
1350         u16 eeprom;
1351
1352         /*
1353          * Read EEPROM word for configuration.
1354          */
1355         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1356
1357         /*
1358          * Identify RF chipset.
1359          */
1360         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1361         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1362         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1363
1364         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1365             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1366                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1367                 return -ENODEV;
1368         }
1369
1370         /*
1371          * Identify default antenna configuration.
1372          */
1373         rt2x00dev->default_ant.tx =
1374             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1375         rt2x00dev->default_ant.rx =
1376             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1377
1378         /*
1379          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1380          * I am not 100% sure about this, but the legacy drivers do not
1381          * indicate antenna swapping in software is required when
1382          * diversity is enabled.
1383          */
1384         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1385                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1386         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1387                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1388
1389         /*
1390          * Store led mode, for correct led behaviour.
1391          */
1392 #ifdef CONFIG_RT2X00_LIB_LEDS
1393         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1394
1395         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1396         if (value == LED_MODE_TXRX_ACTIVITY)
1397                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1398                                    LED_TYPE_ACTIVITY);
1399 #endif /* CONFIG_RT2X00_LIB_LEDS */
1400
1401         /*
1402          * Detect if this device has an hardware controlled radio.
1403          */
1404 #ifdef CONFIG_RT2X00_LIB_RFKILL
1405         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1406                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1407 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1408
1409         /*
1410          * Check if the BBP tuning should be enabled.
1411          */
1412         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1413                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1414
1415         return 0;
1416 }
1417
1418 /*
1419  * RF value list for RF2420 & RF2421
1420  * Supports: 2.4 GHz
1421  */
1422 static const struct rf_channel rf_vals_b[] = {
1423         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1424         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1425         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1426         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1427         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1428         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1429         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1430         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1431         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1432         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1433         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1434         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1435         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1436         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1437 };
1438
1439 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1440 {
1441         struct hw_mode_spec *spec = &rt2x00dev->spec;
1442         struct channel_info *info;
1443         char *tx_power;
1444         unsigned int i;
1445
1446         /*
1447          * Initialize all hw fields.
1448          */
1449         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1450                                IEEE80211_HW_SIGNAL_DBM;
1451         rt2x00dev->hw->extra_tx_headroom = 0;
1452
1453         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1454         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1455                                 rt2x00_eeprom_addr(rt2x00dev,
1456                                                    EEPROM_MAC_ADDR_0));
1457
1458         /*
1459          * Initialize hw_mode information.
1460          */
1461         spec->supported_bands = SUPPORT_BAND_2GHZ;
1462         spec->supported_rates = SUPPORT_RATE_CCK;
1463
1464         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1465         spec->channels = rf_vals_b;
1466
1467         /*
1468          * Create channel information array
1469          */
1470         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1471         if (!info)
1472                 return -ENOMEM;
1473
1474         spec->channels_info = info;
1475
1476         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1477         for (i = 0; i < 14; i++)
1478                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1479
1480         return 0;
1481 }
1482
1483 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1484 {
1485         int retval;
1486
1487         /*
1488          * Allocate eeprom data.
1489          */
1490         retval = rt2400pci_validate_eeprom(rt2x00dev);
1491         if (retval)
1492                 return retval;
1493
1494         retval = rt2400pci_init_eeprom(rt2x00dev);
1495         if (retval)
1496                 return retval;
1497
1498         /*
1499          * Initialize hw specifications.
1500          */
1501         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1502         if (retval)
1503                 return retval;
1504
1505         /*
1506          * This device requires the atim queue and DMA-mapped skbs.
1507          */
1508         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1509         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1510
1511         /*
1512          * Set the rssi offset.
1513          */
1514         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1515
1516         return 0;
1517 }
1518
1519 /*
1520  * IEEE80211 stack callback functions.
1521  */
1522 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1523                              const struct ieee80211_tx_queue_params *params)
1524 {
1525         struct rt2x00_dev *rt2x00dev = hw->priv;
1526
1527         /*
1528          * We don't support variating cw_min and cw_max variables
1529          * per queue. So by default we only configure the TX queue,
1530          * and ignore all other configurations.
1531          */
1532         if (queue != 0)
1533                 return -EINVAL;
1534
1535         if (rt2x00mac_conf_tx(hw, queue, params))
1536                 return -EINVAL;
1537
1538         /*
1539          * Write configuration to register.
1540          */
1541         rt2400pci_config_cw(rt2x00dev,
1542                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1543
1544         return 0;
1545 }
1546
1547 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1548 {
1549         struct rt2x00_dev *rt2x00dev = hw->priv;
1550         u64 tsf;
1551         u32 reg;
1552
1553         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1554         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1555         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1556         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1557
1558         return tsf;
1559 }
1560
1561 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1562 {
1563         struct rt2x00_dev *rt2x00dev = hw->priv;
1564         u32 reg;
1565
1566         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1567         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1568 }
1569
1570 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1571         .tx                     = rt2x00mac_tx,
1572         .start                  = rt2x00mac_start,
1573         .stop                   = rt2x00mac_stop,
1574         .add_interface          = rt2x00mac_add_interface,
1575         .remove_interface       = rt2x00mac_remove_interface,
1576         .config                 = rt2x00mac_config,
1577         .config_interface       = rt2x00mac_config_interface,
1578         .configure_filter       = rt2x00mac_configure_filter,
1579         .get_stats              = rt2x00mac_get_stats,
1580         .bss_info_changed       = rt2x00mac_bss_info_changed,
1581         .conf_tx                = rt2400pci_conf_tx,
1582         .get_tx_stats           = rt2x00mac_get_tx_stats,
1583         .get_tsf                = rt2400pci_get_tsf,
1584         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1585 };
1586
1587 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1588         .irq_handler            = rt2400pci_interrupt,
1589         .probe_hw               = rt2400pci_probe_hw,
1590         .initialize             = rt2x00pci_initialize,
1591         .uninitialize           = rt2x00pci_uninitialize,
1592         .get_entry_state        = rt2400pci_get_entry_state,
1593         .clear_entry            = rt2400pci_clear_entry,
1594         .set_device_state       = rt2400pci_set_device_state,
1595         .rfkill_poll            = rt2400pci_rfkill_poll,
1596         .link_stats             = rt2400pci_link_stats,
1597         .reset_tuner            = rt2400pci_reset_tuner,
1598         .link_tuner             = rt2400pci_link_tuner,
1599         .write_tx_desc          = rt2400pci_write_tx_desc,
1600         .write_tx_data          = rt2x00pci_write_tx_data,
1601         .write_beacon           = rt2400pci_write_beacon,
1602         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1603         .fill_rxdone            = rt2400pci_fill_rxdone,
1604         .config_filter          = rt2400pci_config_filter,
1605         .config_intf            = rt2400pci_config_intf,
1606         .config_erp             = rt2400pci_config_erp,
1607         .config_ant             = rt2400pci_config_ant,
1608         .config                 = rt2400pci_config,
1609 };
1610
1611 static const struct data_queue_desc rt2400pci_queue_rx = {
1612         .entry_num              = RX_ENTRIES,
1613         .data_size              = DATA_FRAME_SIZE,
1614         .desc_size              = RXD_DESC_SIZE,
1615         .priv_size              = sizeof(struct queue_entry_priv_pci),
1616 };
1617
1618 static const struct data_queue_desc rt2400pci_queue_tx = {
1619         .entry_num              = TX_ENTRIES,
1620         .data_size              = DATA_FRAME_SIZE,
1621         .desc_size              = TXD_DESC_SIZE,
1622         .priv_size              = sizeof(struct queue_entry_priv_pci),
1623 };
1624
1625 static const struct data_queue_desc rt2400pci_queue_bcn = {
1626         .entry_num              = BEACON_ENTRIES,
1627         .data_size              = MGMT_FRAME_SIZE,
1628         .desc_size              = TXD_DESC_SIZE,
1629         .priv_size              = sizeof(struct queue_entry_priv_pci),
1630 };
1631
1632 static const struct data_queue_desc rt2400pci_queue_atim = {
1633         .entry_num              = ATIM_ENTRIES,
1634         .data_size              = DATA_FRAME_SIZE,
1635         .desc_size              = TXD_DESC_SIZE,
1636         .priv_size              = sizeof(struct queue_entry_priv_pci),
1637 };
1638
1639 static const struct rt2x00_ops rt2400pci_ops = {
1640         .name           = KBUILD_MODNAME,
1641         .max_sta_intf   = 1,
1642         .max_ap_intf    = 1,
1643         .eeprom_size    = EEPROM_SIZE,
1644         .rf_size        = RF_SIZE,
1645         .tx_queues      = NUM_TX_QUEUES,
1646         .rx             = &rt2400pci_queue_rx,
1647         .tx             = &rt2400pci_queue_tx,
1648         .bcn            = &rt2400pci_queue_bcn,
1649         .atim           = &rt2400pci_queue_atim,
1650         .lib            = &rt2400pci_rt2x00_ops,
1651         .hw             = &rt2400pci_mac80211_ops,
1652 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1653         .debugfs        = &rt2400pci_rt2x00debug,
1654 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1655 };
1656
1657 /*
1658  * RT2400pci module information.
1659  */
1660 static struct pci_device_id rt2400pci_device_table[] = {
1661         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1662         { 0, }
1663 };
1664
1665 MODULE_AUTHOR(DRV_PROJECT);
1666 MODULE_VERSION(DRV_VERSION);
1667 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1668 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1669 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1670 MODULE_LICENSE("GPL");
1671
1672 static struct pci_driver rt2400pci_driver = {
1673         .name           = KBUILD_MODNAME,
1674         .id_table       = rt2400pci_device_table,
1675         .probe          = rt2x00pci_probe,
1676         .remove         = __devexit_p(rt2x00pci_remove),
1677         .suspend        = rt2x00pci_suspend,
1678         .resume         = rt2x00pci_resume,
1679 };
1680
1681 static int __init rt2400pci_init(void)
1682 {
1683         return pci_register_driver(&rt2400pci_driver);
1684 }
1685
1686 static void __exit rt2400pci_exit(void)
1687 {
1688         pci_unregister_driver(&rt2400pci_driver);
1689 }
1690
1691 module_init(rt2400pci_init);
1692 module_exit(rt2400pci_exit);