git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 0;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attampt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  60 #define WAIT_FOR_RF(__dev, __reg) \
  61         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  62 #define WAIT_FOR_MCU(__dev, __reg) \
  63         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  64                                H2M_MAILBOX_CSR_OWNER, (__reg))
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         if (!word)
 127                 return;
 128
 129         mutex_lock(&rt2x00dev->csr_mutex);
 130
 131         /*
 132          * Wait until the RF becomes available, afterwards we
 133          * can safely write the new data into the register.
 134          */
 135         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 136                 reg = 0;
 137                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 139                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 140                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 141
 142                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 143                 rt2x00_rf_write(rt2x00dev, word, value);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 150                                 const u8 command, const u8 token,
 151                                 const u8 arg0, const u8 arg1)
 152 {
 153         u32 reg;
 154
 155         mutex_lock(&rt2x00dev->csr_mutex);
 156
 157         /*
 158          * Wait until the MCU becomes available, afterwards we
 159          * can safely write the new data into the register.
 160          */
 161         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 164                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 165                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 166                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 167
 168                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 169                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 170                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 171                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 172         }
 173
 174         mutex_unlock(&rt2x00dev->csr_mutex);
 175
 176 }
 177
 178 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 179 {
 180         struct rt2x00_dev *rt2x00dev = eeprom->data;
 181         u32 reg;
 182
 183         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 184
 185         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 186         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 187         eeprom->reg_data_clock =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 189         eeprom->reg_chip_select =
 190             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 191 }
 192
 193 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg = 0;
 197
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 199         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 201                            !!eeprom->reg_data_clock);
 202         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 203                            !!eeprom->reg_chip_select);
 204
 205         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 206 }
 207
 208 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 209 static const struct rt2x00debug rt61pci_rt2x00debug = {
 210         .owner  = THIS_MODULE,
 211         .csr    = {
 212                 .read           = rt2x00pci_register_read,
 213                 .write          = rt2x00pci_register_write,
 214                 .flags          = RT2X00DEBUGFS_OFFSET,
 215                 .word_base      = CSR_REG_BASE,
 216                 .word_size      = sizeof(u32),
 217                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 218         },
 219         .eeprom = {
 220                 .read           = rt2x00_eeprom_read,
 221                 .write          = rt2x00_eeprom_write,
 222                 .word_base      = EEPROM_BASE,
 223                 .word_size      = sizeof(u16),
 224                 .word_count     = EEPROM_SIZE / sizeof(u16),
 225         },
 226         .bbp    = {
 227                 .read           = rt61pci_bbp_read,
 228                 .write          = rt61pci_bbp_write,
 229                 .word_base      = BBP_BASE,
 230                 .word_size      = sizeof(u8),
 231                 .word_count     = BBP_SIZE / sizeof(u8),
 232         },
 233         .rf     = {
 234                 .read           = rt2x00_rf_read,
 235                 .write          = rt61pci_rf_write,
 236                 .word_base      = RF_BASE,
 237                 .word_size      = sizeof(u32),
 238                 .word_count     = RF_SIZE / sizeof(u32),
 239         },
 240 };
 241 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 242
 243 #ifdef CONFIG_RT2X00_LIB_RFKILL
 244 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 245 {
 246         u32 reg;
 247
 248         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 249         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 250 }
 251 #else
 252 #define rt61pci_rfkill_poll     NULL
 253 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 254
 255 #ifdef CONFIG_RT2X00_LIB_LEDS
 256 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 257                                    enum led_brightness brightness)
 258 {
 259         struct rt2x00_led *led =
 260             container_of(led_cdev, struct rt2x00_led, led_dev);
 261         unsigned int enabled = brightness != LED_OFF;
 262         unsigned int a_mode =
 263             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 264         unsigned int bg_mode =
 265             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 266
 267         if (led->type == LED_TYPE_RADIO) {
 268                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 269                                    MCU_LEDCS_RADIO_STATUS, enabled);
 270
 271                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 272                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 273                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 274         } else if (led->type == LED_TYPE_ASSOC) {
 275                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 276                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 277                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 278                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 279
 280                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 281                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 282                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 283         } else if (led->type == LED_TYPE_QUALITY) {
 284                 /*
 285                  * The brightness is divided into 6 levels (0 - 5),
 286                  * this means we need to convert the brightness
 287                  * argument into the matching level within that range.
 288                  */
 289                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 290                                     brightness / (LED_FULL / 6), 0);
 291         }
 292 }
 293
 294 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 295                              unsigned long *delay_on,
 296                              unsigned long *delay_off)
 297 {
 298         struct rt2x00_led *led =
 299             container_of(led_cdev, struct rt2x00_led, led_dev);
 300         u32 reg;
 301
 302         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 303         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 304         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 305         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 306
 307         return 0;
 308 }
 309
 310 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 311                              struct rt2x00_led *led,
 312                              enum led_type type)
 313 {
 314         led->rt2x00dev = rt2x00dev;
 315         led->type = type;
 316         led->led_dev.brightness_set = rt61pci_brightness_set;
 317         led->led_dev.blink_set = rt61pci_blink_set;
 318         led->flags = LED_INITIALIZED;
 319 }
 320 #endif /* CONFIG_RT2X00_LIB_LEDS */
 321
 322 /*
 323  * Configuration handlers.
 324  */
 325 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 326                                      struct rt2x00lib_crypto *crypto,
 327                                      struct ieee80211_key_conf *key)
 328 {
 329         struct hw_key_entry key_entry;
 330         struct rt2x00_field32 field;
 331         u32 mask;
 332         u32 reg;
 333
 334         if (crypto->cmd == SET_KEY) {
 335                 /*
 336                  * rt2x00lib can't determine the correct free
 337                  * key_idx for shared keys. We have 1 register
 338                  * with key valid bits. The goal is simple, read
 339                  * the register, if that is full we have no slots
 340                  * left.
 341                  * Note that each BSS is allowed to have up to 4
 342                  * shared keys, so put a mask over the allowed
 343                  * entries.
 344                  */
 345                 mask = (0xf << crypto->bssidx);
 346
 347                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 348                 reg &= mask;
 349
 350                 if (reg && reg == mask)
 351                         return -ENOSPC;
 352
 353                 key->hw_key_idx += reg ? ffz(reg) : 0;
 354
 355                 /*
 356                  * Upload key to hardware
 357                  */
 358                 memcpy(key_entry.key, crypto->key,
 359                        sizeof(key_entry.key));
 360                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 361                        sizeof(key_entry.tx_mic));
 362                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 363                        sizeof(key_entry.rx_mic));
 364
 365                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 366                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 367                                               &key_entry, sizeof(key_entry));
 368
 369                 /*
 370                  * The cipher types are stored over 2 registers.
 371                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 372                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 373                  * Using the correct defines correctly will cause overhead,
 374                  * so just calculate the correct offset.
 375                  */
 376                 if (key->hw_key_idx < 8) {
 377                         field.bit_offset = (3 * key->hw_key_idx);
 378                         field.bit_mask = 0x7 << field.bit_offset;
 379
 380                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 381                         rt2x00_set_field32(&reg, field, crypto->cipher);
 382                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 383                 } else {
 384                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 385                         field.bit_mask = 0x7 << field.bit_offset;
 386
 387                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 388                         rt2x00_set_field32(&reg, field, crypto->cipher);
 389                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 390                 }
 391
 392                 /*
 393                  * The driver does not support the IV/EIV generation
 394                  * in hardware. However it doesn't support the IV/EIV
 395                  * inside the ieee80211 frame either, but requires it
 396                  * to be provided seperately for the descriptor.
 397                  * rt2x00lib will cut the IV/EIV data out of all frames
 398                  * given to us by mac80211, but we must tell mac80211
 399                  * to generate the IV/EIV data.
 400                  */
 401                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 402         }
 403
 404         /*
 405          * SEC_CSR0 contains only single-bit fields to indicate
 406          * a particular key is valid. Because using the FIELD32()
 407          * defines directly will cause a lot of overhead we use
 408          * a calculation to determine the correct bit directly.
 409          */
 410         mask = 1 << key->hw_key_idx;
 411
 412         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 413         if (crypto->cmd == SET_KEY)
 414                 reg |= mask;
 415         else if (crypto->cmd == DISABLE_KEY)
 416                 reg &= ~mask;
 417         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 418
 419         return 0;
 420 }
 421
 422 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 423                                        struct rt2x00lib_crypto *crypto,
 424                                        struct ieee80211_key_conf *key)
 425 {
 426         struct hw_pairwise_ta_entry addr_entry;
 427         struct hw_key_entry key_entry;
 428         u32 mask;
 429         u32 reg;
 430
 431         if (crypto->cmd == SET_KEY) {
 432                 /*
 433                  * rt2x00lib can't determine the correct free
 434                  * key_idx for pairwise keys. We have 2 registers
 435                  * with key valid bits. The goal is simple, read
 436                  * the first register, if that is full move to
 437                  * the next register.
 438                  * When both registers are full, we drop the key,
 439                  * otherwise we use the first invalid entry.
 440                  */
 441                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 442                 if (reg && reg == ~0) {
 443                         key->hw_key_idx = 32;
 444                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 445                         if (reg && reg == ~0)
 446                                 return -ENOSPC;
 447                 }
 448
 449                 key->hw_key_idx += reg ? ffz(reg) : 0;
 450
 451                 /*
 452                  * Upload key to hardware
 453                  */
 454                 memcpy(key_entry.key, crypto->key,
 455                        sizeof(key_entry.key));
 456                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 457                        sizeof(key_entry.tx_mic));
 458                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 459                        sizeof(key_entry.rx_mic));
 460
 461                 memset(&addr_entry, 0, sizeof(addr_entry));
 462                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 463                 addr_entry.cipher = crypto->cipher;
 464
 465                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 466                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 467                                               &key_entry, sizeof(key_entry));
 468
 469                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 470                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 471                                               &addr_entry, sizeof(addr_entry));
 472
 473                 /*
 474                  * Enable pairwise lookup table for given BSS idx,
 475                  * without this received frames will not be decrypted
 476                  * by the hardware.
 477                  */
 478                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 479                 reg |= (1 << crypto->bssidx);
 480                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 481
 482                 /*
 483                  * The driver does not support the IV/EIV generation
 484                  * in hardware. However it doesn't support the IV/EIV
 485                  * inside the ieee80211 frame either, but requires it
 486                  * to be provided seperately for the descriptor.
 487                  * rt2x00lib will cut the IV/EIV data out of all frames
 488                  * given to us by mac80211, but we must tell mac80211
 489                  * to generate the IV/EIV data.
 490                  */
 491                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 492         }
 493
 494         /*
 495          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 496          * a particular key is valid. Because using the FIELD32()
 497          * defines directly will cause a lot of overhead we use
 498          * a calculation to determine the correct bit directly.
 499          */
 500         if (key->hw_key_idx < 32) {
 501                 mask = 1 << key->hw_key_idx;
 502
 503                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 504                 if (crypto->cmd == SET_KEY)
 505                         reg |= mask;
 506                 else if (crypto->cmd == DISABLE_KEY)
 507                         reg &= ~mask;
 508                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 509         } else {
 510                 mask = 1 << (key->hw_key_idx - 32);
 511
 512                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 513                 if (crypto->cmd == SET_KEY)
 514                         reg |= mask;
 515                 else if (crypto->cmd == DISABLE_KEY)
 516                         reg &= ~mask;
 517                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 524                                   const unsigned int filter_flags)
 525 {
 526         u32 reg;
 527
 528         /*
 529          * Start configuration steps.
 530          * Note that the version error will always be dropped
 531          * and broadcast frames will always be accepted since
 532          * there is no filter for it at this time.
 533          */
 534         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 536                            !(filter_flags & FIF_FCSFAIL));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 538                            !(filter_flags & FIF_PLCPFAIL));
 539         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 542                            !(filter_flags & FIF_PROMISC_IN_BSS));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 544                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 545                            !rt2x00dev->intf_ap_count);
 546         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 547         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 548                            !(filter_flags & FIF_ALLMULTI));
 549         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 550         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 551                            !(filter_flags & FIF_CONTROL));
 552         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 553 }
 554
 555 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 556                                 struct rt2x00_intf *intf,
 557                                 struct rt2x00intf_conf *conf,
 558                                 const unsigned int flags)
 559 {
 560         unsigned int beacon_base;
 561         u32 reg;
 562
 563         if (flags & CONFIG_UPDATE_TYPE) {
 564                 /*
 565                  * Clear current synchronisation setup.
 566                  * For the Beacon base registers we only need to clear
 567                  * the first byte since that byte contains the VALID and OWNER
 568                  * bits which (when set to 0) will invalidate the entire beacon.
 569                  */
 570                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 571                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 572
 573                 /*
 574                  * Enable synchronisation.
 575                  */
 576                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 577                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 578                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 579                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 580                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 581         }
 582
 583         if (flags & CONFIG_UPDATE_MAC) {
 584                 reg = le32_to_cpu(conf->mac[1]);
 585                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 586                 conf->mac[1] = cpu_to_le32(reg);
 587
 588                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 589                                               conf->mac, sizeof(conf->mac));
 590         }
 591
 592         if (flags & CONFIG_UPDATE_BSSID) {
 593                 reg = le32_to_cpu(conf->bssid[1]);
 594                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 595                 conf->bssid[1] = cpu_to_le32(reg);
 596
 597                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 598                                               conf->bssid, sizeof(conf->bssid));
 599         }
 600 }
 601
 602 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 603                                struct rt2x00lib_erp *erp)
 604 {
 605         u32 reg;
 606
 607         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 608         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 609         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 610
 611         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 612         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 613                            !!erp->short_preamble);
 614         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 615
 616         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 617
 618         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 619         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 620         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 621
 622         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 623         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 624         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 625         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 626         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 627 }
 628
 629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 630                                       struct antenna_setup *ant)
 631 {
 632         u8 r3;
 633         u8 r4;
 634         u8 r77;
 635
 636         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 637         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 638         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 639
 640         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 641                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 642
 643         /*
 644          * Configure the RX antenna.
 645          */
 646         switch (ant->rx) {
 647         case ANTENNA_HW_DIVERSITY:
 648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 649                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 650                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 651                 break;
 652         case ANTENNA_A:
 653                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 654                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 655                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 656                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 657                 else
 658                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 659                 break;
 660         case ANTENNA_B:
 661         default:
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 666                 else
 667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 668                 break;
 669         }
 670
 671         rt61pci_bbp_write(rt2x00dev, 77, r77);
 672         rt61pci_bbp_write(rt2x00dev, 3, r3);
 673         rt61pci_bbp_write(rt2x00dev, 4, r4);
 674 }
 675
 676 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 677                                       struct antenna_setup *ant)
 678 {
 679         u8 r3;
 680         u8 r4;
 681         u8 r77;
 682
 683         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 684         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 685         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 686
 687         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 688                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 689         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 690                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 691
 692         /*
 693          * Configure the RX antenna.
 694          */
 695         switch (ant->rx) {
 696         case ANTENNA_HW_DIVERSITY:
 697                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 698                 break;
 699         case ANTENNA_A:
 700                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 701                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 702                 break;
 703         case ANTENNA_B:
 704         default:
 705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 706                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 707                 break;
 708         }
 709
 710         rt61pci_bbp_write(rt2x00dev, 77, r77);
 711         rt61pci_bbp_write(rt2x00dev, 3, r3);
 712         rt61pci_bbp_write(rt2x00dev, 4, r4);
 713 }
 714
 715 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 716                                            const int p1, const int p2)
 717 {
 718         u32 reg;
 719
 720         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 721
 722         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 723         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 724
 725         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 726         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 727
 728         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 729 }
 730
 731 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 732                                         struct antenna_setup *ant)
 733 {
 734         u8 r3;
 735         u8 r4;
 736         u8 r77;
 737
 738         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 739         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 740         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 741
 742         /*
 743          * Configure the RX antenna.
 744          */
 745         switch (ant->rx) {
 746         case ANTENNA_A:
 747                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 748                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 749                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 750                 break;
 751         case ANTENNA_HW_DIVERSITY:
 752                 /*
 753                  * FIXME: Antenna selection for the rf 2529 is very confusing
 754                  * in the legacy driver. Just default to antenna B until the
 755                  * legacy code can be properly translated into rt2x00 code.
 756                  */
 757         case ANTENNA_B:
 758         default:
 759                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 760                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 761                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 762                 break;
 763         }
 764
 765         rt61pci_bbp_write(rt2x00dev, 77, r77);
 766         rt61pci_bbp_write(rt2x00dev, 3, r3);
 767         rt61pci_bbp_write(rt2x00dev, 4, r4);
 768 }
 769
 770 struct antenna_sel {
 771         u8 word;
 772         /*
 773          * value[0] -> non-LNA
 774          * value[1] -> LNA
 775          */
 776         u8 value[2];
 777 };
 778
 779 static const struct antenna_sel antenna_sel_a[] = {
 780         { 96,  { 0x58, 0x78 } },
 781         { 104, { 0x38, 0x48 } },
 782         { 75,  { 0xfe, 0x80 } },
 783         { 86,  { 0xfe, 0x80 } },
 784         { 88,  { 0xfe, 0x80 } },
 785         { 35,  { 0x60, 0x60 } },
 786         { 97,  { 0x58, 0x58 } },
 787         { 98,  { 0x58, 0x58 } },
 788 };
 789
 790 static const struct antenna_sel antenna_sel_bg[] = {
 791         { 96,  { 0x48, 0x68 } },
 792         { 104, { 0x2c, 0x3c } },
 793         { 75,  { 0xfe, 0x80 } },
 794         { 86,  { 0xfe, 0x80 } },
 795         { 88,  { 0xfe, 0x80 } },
 796         { 35,  { 0x50, 0x50 } },
 797         { 97,  { 0x48, 0x48 } },
 798         { 98,  { 0x48, 0x48 } },
 799 };
 800
 801 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 802                                struct antenna_setup *ant)
 803 {
 804         const struct antenna_sel *sel;
 805         unsigned int lna;
 806         unsigned int i;
 807         u32 reg;
 808
 809         /*
 810          * We should never come here because rt2x00lib is supposed
 811          * to catch this and send us the correct antenna explicitely.
 812          */
 813         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 814                ant->tx == ANTENNA_SW_DIVERSITY);
 815
 816         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 817                 sel = antenna_sel_a;
 818                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 819         } else {
 820                 sel = antenna_sel_bg;
 821                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 822         }
 823
 824         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 825                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 826
 827         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 828
 829         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 830                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 831         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 832                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 833
 834         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 835
 836         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 837             rt2x00_rf(&rt2x00dev->chip, RF5325))
 838                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 839         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 840                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 841         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 842                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 843                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 844                 else
 845                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 846         }
 847 }
 848
 849 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 850                                     struct rt2x00lib_conf *libconf)
 851 {
 852         u16 eeprom;
 853         short lna_gain = 0;
 854
 855         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 856                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 857                         lna_gain += 14;
 858
 859                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 860                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 861         } else {
 862                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 863                         lna_gain += 14;
 864
 865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 866                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 867         }
 868
 869         rt2x00dev->lna_gain = lna_gain;
 870 }
 871
 872 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 873                                    struct rf_channel *rf, const int txpower)
 874 {
 875         u8 r3;
 876         u8 r94;
 877         u8 smart;
 878
 879         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 880         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 881
 882         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 883                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 884
 885         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 886         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 887         rt61pci_bbp_write(rt2x00dev, 3, r3);
 888
 889         r94 = 6;
 890         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 891                 r94 += txpower - MAX_TXPOWER;
 892         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 893                 r94 += txpower;
 894         rt61pci_bbp_write(rt2x00dev, 94, r94);
 895
 896         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 897         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 898         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 899         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 900
 901         udelay(200);
 902
 903         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 904         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 905         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 906         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 907
 908         udelay(200);
 909
 910         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 911         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 912         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 913         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 914
 915         msleep(1);
 916 }
 917
 918 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 919                                    const int txpower)
 920 {
 921         struct rf_channel rf;
 922
 923         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 924         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 925         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 926         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 927
 928         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 929 }
 930
 931 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 932                                     struct rt2x00lib_conf *libconf)
 933 {
 934         u32 reg;
 935
 936         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 937         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 938                            libconf->conf->long_frame_max_tx_count);
 939         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 940                            libconf->conf->short_frame_max_tx_count);
 941         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 942 }
 943
 944 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 945                                     struct rt2x00lib_conf *libconf)
 946 {
 947         u32 reg;
 948
 949         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 950         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 951         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 952
 953         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 954         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 955         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 956
 957         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 958         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 959                            libconf->conf->beacon_int * 16);
 960         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 961 }
 962
 963 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 964                                 struct rt2x00lib_conf *libconf)
 965 {
 966         enum dev_state state =
 967             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 968                 STATE_SLEEP : STATE_AWAKE;
 969         u32 reg;
 970
 971         if (state == STATE_SLEEP) {
 972                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 974                                    libconf->conf->beacon_int - 10);
 975                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 976                                    libconf->conf->listen_interval - 1);
 977                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 978
 979                 /* We must first disable autowake before it can be enabled */
 980                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 981                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 982
 983                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 984                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 985
 986                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 987                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 988                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 989
 990                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 991         } else {
 992                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 993                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 994                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 995                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 996                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 997                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 998
 999                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
1000                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
1001                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
1002
1003                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1004         }
1005 }
1006
1007 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
1008                            struct rt2x00lib_conf *libconf,
1009                            const unsigned int flags)
1010 {
1011         /* Always recalculate LNA gain before changing configuration */
1012         rt61pci_config_lna_gain(rt2x00dev, libconf);
1013
1014         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1015                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1016                                        libconf->conf->power_level);
1017         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1018             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1019                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1020         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1021                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1022         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1023                 rt61pci_config_duration(rt2x00dev, libconf);
1024         if (flags & IEEE80211_CONF_CHANGE_PS)
1025                 rt61pci_config_ps(rt2x00dev, libconf);
1026 }
1027
1028 /*
1029  * Link tuning
1030  */
1031 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1032                                struct link_qual *qual)
1033 {
1034         u32 reg;
1035
1036         /*
1037          * Update FCS error count from register.
1038          */
1039         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1040         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1041
1042         /*
1043          * Update False CCA count from register.
1044          */
1045         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1046         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1047 }
1048
1049 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1050 {
1051         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1052         rt2x00dev->link.vgc_level = 0x20;
1053 }
1054
1055 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1056 {
1057         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1058         u8 r17;
1059         u8 up_bound;
1060         u8 low_bound;
1061
1062         rt61pci_bbp_read(rt2x00dev, 17, &r17);
1063
1064         /*
1065          * Determine r17 bounds.
1066          */
1067         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1068                 low_bound = 0x28;
1069                 up_bound = 0x48;
1070                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1071                         low_bound += 0x10;
1072                         up_bound += 0x10;
1073                 }
1074         } else {
1075                 low_bound = 0x20;
1076                 up_bound = 0x40;
1077                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1078                         low_bound += 0x10;
1079                         up_bound += 0x10;
1080                 }
1081         }
1082
1083         /*
1084          * If we are not associated, we should go straight to the
1085          * dynamic CCA tuning.
1086          */
1087         if (!rt2x00dev->intf_associated)
1088                 goto dynamic_cca_tune;
1089
1090         /*
1091          * Special big-R17 for very short distance
1092          */
1093         if (rssi >= -35) {
1094                 if (r17 != 0x60)
1095                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1096                 return;
1097         }
1098
1099         /*
1100          * Special big-R17 for short distance
1101          */
1102         if (rssi >= -58) {
1103                 if (r17 != up_bound)
1104                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1105                 return;
1106         }
1107
1108         /*
1109          * Special big-R17 for middle-short distance
1110          */
1111         if (rssi >= -66) {
1112                 low_bound += 0x10;
1113                 if (r17 != low_bound)
1114                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1115                 return;
1116         }
1117
1118         /*
1119          * Special mid-R17 for middle distance
1120          */
1121         if (rssi >= -74) {
1122                 low_bound += 0x08;
1123                 if (r17 != low_bound)
1124                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1125                 return;
1126         }
1127
1128         /*
1129          * Special case: Change up_bound based on the rssi.
1130          * Lower up_bound when rssi is weaker then -74 dBm.
1131          */
1132         up_bound -= 2 * (-74 - rssi);
1133         if (low_bound > up_bound)
1134                 up_bound = low_bound;
1135
1136         if (r17 > up_bound) {
1137                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1138                 return;
1139         }
1140
1141 dynamic_cca_tune:
1142
1143         /*
1144          * r17 does not yet exceed upper limit, continue and base
1145          * the r17 tuning on the false CCA count.
1146          */
1147         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1148                 if (++r17 > up_bound)
1149                         r17 = up_bound;
1150                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1151         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1152                 if (--r17 < low_bound)
1153                         r17 = low_bound;
1154                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1155         }
1156 }
1157
1158 /*
1159  * Firmware functions
1160  */
1161 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1162 {
1163         char *fw_name;
1164
1165         switch (rt2x00dev->chip.rt) {
1166         case RT2561:
1167                 fw_name = FIRMWARE_RT2561;
1168                 break;
1169         case RT2561s:
1170                 fw_name = FIRMWARE_RT2561s;
1171                 break;
1172         case RT2661:
1173                 fw_name = FIRMWARE_RT2661;
1174                 break;
1175         default:
1176                 fw_name = NULL;
1177                 break;
1178         }
1179
1180         return fw_name;
1181 }
1182
1183 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1184 {
1185         u16 crc;
1186
1187         /*
1188          * Use the crc itu-t algorithm.
1189          * The last 2 bytes in the firmware array are the crc checksum itself,
1190          * this means that we should never pass those 2 bytes to the crc
1191          * algorithm.
1192          */
1193         crc = crc_itu_t(0, data, len - 2);
1194         crc = crc_itu_t_byte(crc, 0);
1195         crc = crc_itu_t_byte(crc, 0);
1196
1197         return crc;
1198 }
1199
1200 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1201                                  const size_t len)
1202 {
1203         int i;
1204         u32 reg;
1205
1206         /*
1207          * Wait for stable hardware.
1208          */
1209         for (i = 0; i < 100; i++) {
1210                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1211                 if (reg)
1212                         break;
1213                 msleep(1);
1214         }
1215
1216         if (!reg) {
1217                 ERROR(rt2x00dev, "Unstable hardware.\n");
1218                 return -EBUSY;
1219         }
1220
1221         /*
1222          * Prepare MCU and mailbox for firmware loading.
1223          */
1224         reg = 0;
1225         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1226         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1227         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1228         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1229         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1230
1231         /*
1232          * Write firmware to device.
1233          */
1234         reg = 0;
1235         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1236         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1237         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1238
1239         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1240                                       data, len);
1241
1242         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1243         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1244
1245         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1246         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1247
1248         for (i = 0; i < 100; i++) {
1249                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1250                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1251                         break;
1252                 msleep(1);
1253         }
1254
1255         if (i == 100) {
1256                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1257                 return -EBUSY;
1258         }
1259
1260         /*
1261          * Hardware needs another millisecond before it is ready.
1262          */
1263         msleep(1);
1264
1265         /*
1266          * Reset MAC and BBP registers.
1267          */
1268         reg = 0;
1269         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1270         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1271         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1272
1273         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1274         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1275         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1276         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1277
1278         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1279         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1280         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1281
1282         return 0;
1283 }
1284
1285 /*
1286  * Initialization functions.
1287  */
1288 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1289 {
1290         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1291         u32 word;
1292
1293         if (entry->queue->qid == QID_RX) {
1294                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1295
1296                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1297         } else {
1298                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1299
1300                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1301                         rt2x00_get_field32(word, TXD_W0_VALID));
1302         }
1303 }
1304
1305 static void rt61pci_clear_entry(struct queue_entry *entry)
1306 {
1307         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1308         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1309         u32 word;
1310
1311         if (entry->queue->qid == QID_RX) {
1312                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1313                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1314                                    skbdesc->skb_dma);
1315                 rt2x00_desc_write(entry_priv->desc, 5, word);
1316
1317                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1318                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1319                 rt2x00_desc_write(entry_priv->desc, 0, word);
1320         } else {
1321                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1322                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1323                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1324                 rt2x00_desc_write(entry_priv->desc, 0, word);
1325         }
1326 }
1327
1328 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1329 {
1330         struct queue_entry_priv_pci *entry_priv;
1331         u32 reg;
1332
1333         /*
1334          * Initialize registers.
1335          */
1336         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1337         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1338                            rt2x00dev->tx[0].limit);
1339         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1340                            rt2x00dev->tx[1].limit);
1341         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1342                            rt2x00dev->tx[2].limit);
1343         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1344                            rt2x00dev->tx[3].limit);
1345         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1346
1347         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1348         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1349                            rt2x00dev->tx[0].desc_size / 4);
1350         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1351
1352         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1353         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1354         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1355                            entry_priv->desc_dma);
1356         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1357
1358         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1359         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1360         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1361                            entry_priv->desc_dma);
1362         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1363
1364         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1365         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1366         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1367                            entry_priv->desc_dma);
1368         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1369
1370         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1371         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1372         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1373                            entry_priv->desc_dma);
1374         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1375
1376         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1377         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1378         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1379                            rt2x00dev->rx->desc_size / 4);
1380         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1381         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1382
1383         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1384         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1385         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1386                            entry_priv->desc_dma);
1387         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1388
1389         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1390         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1391         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1392         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1393         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1394         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1395
1396         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1397         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1398         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1399         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1400         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1401         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1402
1403         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1404         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1405         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1406
1407         return 0;
1408 }
1409
1410 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1411 {
1412         u32 reg;
1413
1414         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1415         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1416         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1417         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1418         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1419
1420         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1421         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1422         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1423         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1424         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1425         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1426         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1427         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1428         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1430
1431         /*
1432          * CCK TXD BBP registers
1433          */
1434         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1435         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1436         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1437         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1438         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1439         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1440         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1441         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1442         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1443         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1444
1445         /*
1446          * OFDM TXD BBP registers
1447          */
1448         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1449         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1450         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1451         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1452         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1453         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1454         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1455         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1456
1457         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1458         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1459         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1460         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1461         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1462         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1463
1464         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1465         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1466         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1467         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1468         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1469         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1470
1471         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1472         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1473         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1474         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1475         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1476         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1477         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1478         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1479
1480         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1481
1482         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1483
1484         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1485         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1486         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1487
1488         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1489
1490         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1491                 return -EBUSY;
1492
1493         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1494
1495         /*
1496          * Invalidate all Shared Keys (SEC_CSR0),
1497          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1498          */
1499         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1500         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1501         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1502
1503         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1504         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1505         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1506         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1507
1508         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1509
1510         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1511
1512         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1513
1514         /*
1515          * Clear all beacons
1516          * For the Beacon base registers we only need to clear
1517          * the first byte since that byte contains the VALID and OWNER
1518          * bits which (when set to 0) will invalidate the entire beacon.
1519          */
1520         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1521         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1522         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1523         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1524
1525         /*
1526          * We must clear the error counters.
1527          * These registers are cleared on read,
1528          * so we may pass a useless variable to store the value.
1529          */
1530         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1531         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1532         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1533
1534         /*
1535          * Reset MAC and BBP registers.
1536          */
1537         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1538         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1539         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1540         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1541
1542         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1543         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1544         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1545         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1546
1547         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1548         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1549         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1550
1551         return 0;
1552 }
1553
1554 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1555 {
1556         unsigned int i;
1557         u8 value;
1558
1559         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1560                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1561                 if ((value != 0xff) && (value != 0x00))
1562                         return 0;
1563                 udelay(REGISTER_BUSY_DELAY);
1564         }
1565
1566         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1567         return -EACCES;
1568 }
1569
1570 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1571 {
1572         unsigned int i;
1573         u16 eeprom;
1574         u8 reg_id;
1575         u8 value;
1576
1577         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1578                 return -EACCES;
1579
1580         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1581         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1582         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1583         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1584         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1585         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1586         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1587         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1588         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1589         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1590         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1591         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1592         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1593         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1594         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1595         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1596         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1597         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1598         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1599         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1600         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1601         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1602         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1603         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1604
1605         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1606                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1607
1608                 if (eeprom != 0xffff && eeprom != 0x0000) {
1609                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1610                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1611                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1612                 }
1613         }
1614
1615         return 0;
1616 }
1617
1618 /*
1619  * Device state switch handlers.
1620  */
1621 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1622                               enum dev_state state)
1623 {
1624         u32 reg;
1625
1626         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1627         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1628                            (state == STATE_RADIO_RX_OFF) ||
1629                            (state == STATE_RADIO_RX_OFF_LINK));
1630         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1631 }
1632
1633 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1634                                enum dev_state state)
1635 {
1636         int mask = (state == STATE_RADIO_IRQ_OFF);
1637         u32 reg;
1638
1639         /*
1640          * When interrupts are being enabled, the interrupt registers
1641          * should clear the register to assure a clean state.
1642          */
1643         if (state == STATE_RADIO_IRQ_ON) {
1644                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1645                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1646
1647                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1648                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1649         }
1650
1651         /*
1652          * Only toggle the interrupts bits we are going to use.
1653          * Non-checked interrupt bits are disabled by default.
1654          */
1655         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1656         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1657         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1658         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1659         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1660         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1661
1662         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1663         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1664         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1665         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1666         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1667         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1668         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1669         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1670         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1671         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1672 }
1673
1674 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1675 {
1676         u32 reg;
1677
1678         /*
1679          * Initialize all registers.
1680          */
1681         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1682                      rt61pci_init_registers(rt2x00dev) ||
1683                      rt61pci_init_bbp(rt2x00dev)))
1684                 return -EIO;
1685
1686         /*
1687          * Enable RX.
1688          */
1689         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1690         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1691         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1692
1693         return 0;
1694 }
1695
1696 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1697 {
1698         u32 reg;
1699
1700         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1701
1702         /*
1703          * Disable synchronisation.
1704          */
1705         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1706
1707         /*
1708          * Cancel RX and TX.
1709          */
1710         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1711         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1712         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1713         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1714         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1715         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1716 }
1717
1718 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1719 {
1720         u32 reg;
1721         unsigned int i;
1722         char put_to_sleep;
1723
1724         put_to_sleep = (state != STATE_AWAKE);
1725
1726         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1727         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1728         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1729         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1730
1731         /*
1732          * Device is not guaranteed to be in the requested state yet.
1733          * We must wait until the register indicates that the
1734          * device has entered the correct state.
1735          */
1736         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1737                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1738                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1739                 if (state == !put_to_sleep)
1740                         return 0;
1741                 msleep(10);
1742         }
1743
1744         return -EBUSY;
1745 }
1746
1747 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1748                                     enum dev_state state)
1749 {
1750         int retval = 0;
1751
1752         switch (state) {
1753         case STATE_RADIO_ON:
1754                 retval = rt61pci_enable_radio(rt2x00dev);
1755                 break;
1756         case STATE_RADIO_OFF:
1757                 rt61pci_disable_radio(rt2x00dev);
1758                 break;
1759         case STATE_RADIO_RX_ON:
1760         case STATE_RADIO_RX_ON_LINK:
1761         case STATE_RADIO_RX_OFF:
1762         case STATE_RADIO_RX_OFF_LINK:
1763                 rt61pci_toggle_rx(rt2x00dev, state);
1764                 break;
1765         case STATE_RADIO_IRQ_ON:
1766         case STATE_RADIO_IRQ_OFF:
1767                 rt61pci_toggle_irq(rt2x00dev, state);
1768                 break;
1769         case STATE_DEEP_SLEEP:
1770         case STATE_SLEEP:
1771         case STATE_STANDBY:
1772         case STATE_AWAKE:
1773                 retval = rt61pci_set_state(rt2x00dev, state);
1774                 break;
1775         default:
1776                 retval = -ENOTSUPP;
1777                 break;
1778         }
1779
1780         if (unlikely(retval))
1781                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1782                       state, retval);
1783
1784         return retval;
1785 }
1786
1787 /*
1788  * TX descriptor initialization
1789  */
1790 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1791                                   struct sk_buff *skb,
1792                                   struct txentry_desc *txdesc)
1793 {
1794         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1795         __le32 *txd = skbdesc->desc;
1796         u32 word;
1797
1798         /*
1799          * Start writing the descriptor words.
1800          */
1801         rt2x00_desc_read(txd, 1, &word);
1802         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1803         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1804         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1805         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1806         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1807         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1808                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1809         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1810         rt2x00_desc_write(txd, 1, word);
1811
1812         rt2x00_desc_read(txd, 2, &word);
1813         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1814         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1815         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1816         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1817         rt2x00_desc_write(txd, 2, word);
1818
1819         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1820                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1821                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1822         }
1823
1824         rt2x00_desc_read(txd, 5, &word);
1825         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1826         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1827                            skbdesc->entry->entry_idx);
1828         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1829                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1830         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1831         rt2x00_desc_write(txd, 5, word);
1832
1833         rt2x00_desc_read(txd, 6, &word);
1834         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1835                            skbdesc->skb_dma);
1836         rt2x00_desc_write(txd, 6, word);
1837
1838         if (skbdesc->desc_len > TXINFO_SIZE) {
1839                 rt2x00_desc_read(txd, 11, &word);
1840                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1841                 rt2x00_desc_write(txd, 11, word);
1842         }
1843
1844         rt2x00_desc_read(txd, 0, &word);
1845         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1846         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1847         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1848                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1849         rt2x00_set_field32(&word, TXD_W0_ACK,
1850                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1851         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1852                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1853         rt2x00_set_field32(&word, TXD_W0_OFDM,
1854                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1855         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1856         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1857                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1858         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1859                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1860         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1861                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1862         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1863         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1864         rt2x00_set_field32(&word, TXD_W0_BURST,
1865                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1866         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1867         rt2x00_desc_write(txd, 0, word);
1868 }
1869
1870 /*
1871  * TX data initialization
1872  */
1873 static void rt61pci_write_beacon(struct queue_entry *entry)
1874 {
1875         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1876         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1877         unsigned int beacon_base;
1878         u32 reg;
1879
1880         /*
1881          * Disable beaconing while we are reloading the beacon data,
1882          * otherwise we might be sending out invalid data.
1883          */
1884         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1885         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1886         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1887         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1888         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1889
1890         /*
1891          * Write entire beacon with descriptor to register.
1892          */
1893         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1894         rt2x00pci_register_multiwrite(rt2x00dev,
1895                                       beacon_base,
1896                                       skbdesc->desc, skbdesc->desc_len);
1897         rt2x00pci_register_multiwrite(rt2x00dev,
1898                                       beacon_base + skbdesc->desc_len,
1899                                       entry->skb->data, entry->skb->len);
1900
1901         /*
1902          * Clean up beacon skb.
1903          */
1904         dev_kfree_skb_any(entry->skb);
1905         entry->skb = NULL;
1906 }
1907
1908 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1909                                   const enum data_queue_qid queue)
1910 {
1911         u32 reg;
1912
1913         if (queue == QID_BEACON) {
1914                 /*
1915                  * For Wi-Fi faily generated beacons between participating
1916                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1917                  */
1918                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1919
1920                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1921                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1922                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1923                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1924                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1925                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1926                 }
1927                 return;
1928         }
1929
1930         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1931         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1932         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1933         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1934         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1935         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1936 }
1937
1938 /*
1939  * RX control handlers
1940  */
1941 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1942 {
1943         u8 offset = rt2x00dev->lna_gain;
1944         u8 lna;
1945
1946         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1947         switch (lna) {
1948         case 3:
1949                 offset += 90;
1950                 break;
1951         case 2:
1952                 offset += 74;
1953                 break;
1954         case 1:
1955                 offset += 64;
1956                 break;
1957         default:
1958                 return 0;
1959         }
1960
1961         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1962                 if (lna == 3 || lna == 2)
1963                         offset += 10;
1964         }
1965
1966         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1967 }
1968
1969 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1970                                 struct rxdone_entry_desc *rxdesc)
1971 {
1972         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1973         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1974         u32 word0;
1975         u32 word1;
1976
1977         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1978         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1979
1980         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1981                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1982
1983         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1984                 rxdesc->cipher =
1985                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1986                 rxdesc->cipher_status =
1987                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1988         }
1989
1990         if (rxdesc->cipher != CIPHER_NONE) {
1991                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1992                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1993                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1994
1995                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1996                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1997
1998                 /*
1999                  * Hardware has stripped IV/EIV data from 802.11 frame during
2000                  * decryption. It has provided the data seperately but rt2x00lib
2001                  * should decide if it should be reinserted.
2002                  */
2003                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2004
2005                 /*
2006                  * FIXME: Legacy driver indicates that the frame does
2007                  * contain the Michael Mic. Unfortunately, in rt2x00
2008                  * the MIC seems to be missing completely...
2009                  */
2010                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2011
2012                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2013                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2014                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2015                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2016         }
2017
2018         /*
2019          * Obtain the status about this packet.
2020          * When frame was received with an OFDM bitrate,
2021          * the signal is the PLCP value. If it was received with
2022          * a CCK bitrate the signal is the rate in 100kbit/s.
2023          */
2024         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2025         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2026         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2027
2028         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2029                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2030         else
2031                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2032         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2033                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2034 }
2035
2036 /*
2037  * Interrupt functions.
2038  */
2039 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2040 {
2041         struct data_queue *queue;
2042         struct queue_entry *entry;
2043         struct queue_entry *entry_done;
2044         struct queue_entry_priv_pci *entry_priv;
2045         struct txdone_entry_desc txdesc;
2046         u32 word;
2047         u32 reg;
2048         u32 old_reg;
2049         int type;
2050         int index;
2051
2052         /*
2053          * During each loop we will compare the freshly read
2054          * STA_CSR4 register value with the value read from
2055          * the previous loop. If the 2 values are equal then
2056          * we should stop processing because the chance it
2057          * quite big that the device has been unplugged and
2058          * we risk going into an endless loop.
2059          */
2060         old_reg = 0;
2061
2062         while (1) {
2063                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2064                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2065                         break;
2066
2067                 if (old_reg == reg)
2068                         break;
2069                 old_reg = reg;
2070
2071                 /*
2072                  * Skip this entry when it contains an invalid
2073                  * queue identication number.
2074                  */
2075                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2076                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2077                 if (unlikely(!queue))
2078                         continue;
2079
2080                 /*
2081                  * Skip this entry when it contains an invalid
2082                  * index number.
2083                  */
2084                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2085                 if (unlikely(index >= queue->limit))
2086                         continue;
2087
2088                 entry = &queue->entries[index];
2089                 entry_priv = entry->priv_data;
2090                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2091
2092                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2093                     !rt2x00_get_field32(word, TXD_W0_VALID))
2094                         return;
2095
2096                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2097                 while (entry != entry_done) {
2098                         /* Catch up.
2099                          * Just report any entries we missed as failed.
2100                          */
2101                         WARNING(rt2x00dev,
2102                                 "TX status report missed for entry %d\n",
2103                                 entry_done->entry_idx);
2104
2105                         txdesc.flags = 0;
2106                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2107                         txdesc.retry = 0;
2108
2109                         rt2x00lib_txdone(entry_done, &txdesc);
2110                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2111                 }
2112
2113                 /*
2114                  * Obtain the status about this packet.
2115                  */
2116                 txdesc.flags = 0;
2117                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2118                 case 0: /* Success, maybe with retry */
2119                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2120                         break;
2121                 case 6: /* Failure, excessive retries */
2122                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2123                         /* Don't break, this is a failed frame! */
2124                 default: /* Failure */
2125                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2126                 }
2127                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2128
2129                 rt2x00lib_txdone(entry, &txdesc);
2130         }
2131 }
2132
2133 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2134 {
2135         struct rt2x00_dev *rt2x00dev = dev_instance;
2136         u32 reg_mcu;
2137         u32 reg;
2138
2139         /*
2140          * Get the interrupt sources & saved to local variable.
2141          * Write register value back to clear pending interrupts.
2142          */
2143         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2144         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2145
2146         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2147         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2148
2149         if (!reg && !reg_mcu)
2150                 return IRQ_NONE;
2151
2152         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2153                 return IRQ_HANDLED;
2154
2155         /*
2156          * Handle interrupts, walk through all bits
2157          * and run the tasks, the bits are checked in order of
2158          * priority.
2159          */
2160
2161         /*
2162          * 1 - Rx ring done interrupt.
2163          */
2164         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2165                 rt2x00pci_rxdone(rt2x00dev);
2166
2167         /*
2168          * 2 - Tx ring done interrupt.
2169          */
2170         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2171                 rt61pci_txdone(rt2x00dev);
2172
2173         /*
2174          * 3 - Handle MCU command done.
2175          */
2176         if (reg_mcu)
2177                 rt2x00pci_register_write(rt2x00dev,
2178                                          M2H_CMD_DONE_CSR, 0xffffffff);
2179
2180         return IRQ_HANDLED;
2181 }
2182
2183 /*
2184  * Device probe functions.
2185  */
2186 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2187 {
2188         struct eeprom_93cx6 eeprom;
2189         u32 reg;
2190         u16 word;
2191         u8 *mac;
2192         s8 value;
2193
2194         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2195
2196         eeprom.data = rt2x00dev;
2197         eeprom.register_read = rt61pci_eepromregister_read;
2198         eeprom.register_write = rt61pci_eepromregister_write;
2199         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2200             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2201         eeprom.reg_data_in = 0;
2202         eeprom.reg_data_out = 0;
2203         eeprom.reg_data_clock = 0;
2204         eeprom.reg_chip_select = 0;
2205
2206         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2207                                EEPROM_SIZE / sizeof(u16));
2208
2209         /*
2210          * Start validation of the data that has been read.
2211          */
2212         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2213         if (!is_valid_ether_addr(mac)) {
2214                 random_ether_addr(mac);
2215                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2216         }
2217
2218         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2219         if (word == 0xffff) {
2220                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2221                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2222                                    ANTENNA_B);
2223                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2224                                    ANTENNA_B);
2225                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2226                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2227                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2228                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2229                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2230                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2231         }
2232
2233         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2234         if (word == 0xffff) {
2235                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2236                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2237                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2238                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2239                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2240                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2241                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2242                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2243         }
2244
2245         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2246         if (word == 0xffff) {
2247                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2248                                    LED_MODE_DEFAULT);
2249                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2250                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2251         }
2252
2253         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2254         if (word == 0xffff) {
2255                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2256                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2257                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2258                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2259         }
2260
2261         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2262         if (word == 0xffff) {
2263                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2264                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2265                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2266                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2267         } else {
2268                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2269                 if (value < -10 || value > 10)
2270                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2271                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2272                 if (value < -10 || value > 10)
2273                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2274                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2275         }
2276
2277         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2278         if (word == 0xffff) {
2279                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2280                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2281                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2282                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2283         } else {
2284                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2285                 if (value < -10 || value > 10)
2286                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2287                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2288                 if (value < -10 || value > 10)
2289                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2290                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2291         }
2292
2293         return 0;
2294 }
2295
2296 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2297 {
2298         u32 reg;
2299         u16 value;
2300         u16 eeprom;
2301         u16 device;
2302
2303         /*
2304          * Read EEPROM word for configuration.
2305          */
2306         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2307
2308         /*
2309          * Identify RF chipset.
2310          * To determine the RT chip we have to read the
2311          * PCI header of the device.
2312          */
2313         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2314                              PCI_CONFIG_HEADER_DEVICE, &device);
2315         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2316         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2317         rt2x00_set_chip(rt2x00dev, device, value, reg);
2318
2319         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2320             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2321             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2322             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2323                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2324                 return -ENODEV;
2325         }
2326
2327         /*
2328          * Determine number of antenna's.
2329          */
2330         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2331                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2332
2333         /*
2334          * Identify default antenna configuration.
2335          */
2336         rt2x00dev->default_ant.tx =
2337             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2338         rt2x00dev->default_ant.rx =
2339             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2340
2341         /*
2342          * Read the Frame type.
2343          */
2344         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2345                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2346
2347         /*
2348          * Detect if this device has an hardware controlled radio.
2349          */
2350 #ifdef CONFIG_RT2X00_LIB_RFKILL
2351         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2352                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2353 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2354
2355         /*
2356          * Read frequency offset and RF programming sequence.
2357          */
2358         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2359         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2360                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2361
2362         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2363
2364         /*
2365          * Read external LNA informations.
2366          */
2367         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2368
2369         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2370                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2371         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2372                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2373
2374         /*
2375          * When working with a RF2529 chip without double antenna
2376          * the antenna settings should be gathered from the NIC
2377          * eeprom word.
2378          */
2379         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2380             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2381                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2382                 case 0:
2383                         rt2x00dev->default_ant.tx = ANTENNA_B;
2384                         rt2x00dev->default_ant.rx = ANTENNA_A;
2385                         break;
2386                 case 1:
2387                         rt2x00dev->default_ant.tx = ANTENNA_B;
2388                         rt2x00dev->default_ant.rx = ANTENNA_B;
2389                         break;
2390                 case 2:
2391                         rt2x00dev->default_ant.tx = ANTENNA_A;
2392                         rt2x00dev->default_ant.rx = ANTENNA_A;
2393                         break;
2394                 case 3:
2395                         rt2x00dev->default_ant.tx = ANTENNA_A;
2396                         rt2x00dev->default_ant.rx = ANTENNA_B;
2397                         break;
2398                 }
2399
2400                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2401                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2402                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2403                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2404         }
2405
2406         /*
2407          * Store led settings, for correct led behaviour.
2408          * If the eeprom value is invalid,
2409          * switch to default led mode.
2410          */
2411 #ifdef CONFIG_RT2X00_LIB_LEDS
2412         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2413         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2414
2415         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2416         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2417         if (value == LED_MODE_SIGNAL_STRENGTH)
2418                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2419                                  LED_TYPE_QUALITY);
2420
2421         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2422         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2423                            rt2x00_get_field16(eeprom,
2424                                               EEPROM_LED_POLARITY_GPIO_0));
2425         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2426                            rt2x00_get_field16(eeprom,
2427                                               EEPROM_LED_POLARITY_GPIO_1));
2428         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2429                            rt2x00_get_field16(eeprom,
2430                                               EEPROM_LED_POLARITY_GPIO_2));
2431         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2432                            rt2x00_get_field16(eeprom,
2433                                               EEPROM_LED_POLARITY_GPIO_3));
2434         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2435                            rt2x00_get_field16(eeprom,
2436                                               EEPROM_LED_POLARITY_GPIO_4));
2437         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2438                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2439         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2440                            rt2x00_get_field16(eeprom,
2441                                               EEPROM_LED_POLARITY_RDY_G));
2442         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2443                            rt2x00_get_field16(eeprom,
2444                                               EEPROM_LED_POLARITY_RDY_A));
2445 #endif /* CONFIG_RT2X00_LIB_LEDS */
2446
2447         return 0;
2448 }
2449
2450 /*
2451  * RF value list for RF5225 & RF5325
2452  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2453  */
2454 static const struct rf_channel rf_vals_noseq[] = {
2455         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2456         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2457         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2458         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2459         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2460         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2461         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2462         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2463         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2464         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2465         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2466         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2467         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2468         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2469
2470         /* 802.11 UNI / HyperLan 2 */
2471         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2472         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2473         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2474         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2475         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2476         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2477         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2478         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2479
2480         /* 802.11 HyperLan 2 */
2481         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2482         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2483         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2484         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2485         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2486         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2487         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2488         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2489         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2490         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2491
2492         /* 802.11 UNII */
2493         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2494         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2495         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2496         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2497         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2498         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2499
2500         /* MMAC(Japan)J52 ch 34,38,42,46 */
2501         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2502         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2503         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2504         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2505 };
2506
2507 /*
2508  * RF value list for RF5225 & RF5325
2509  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2510  */
2511 static const struct rf_channel rf_vals_seq[] = {
2512         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2513         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2514         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2515         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2516         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2517         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2518         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2519         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2520         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2521         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2522         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2523         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2524         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2525         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2526
2527         /* 802.11 UNI / HyperLan 2 */
2528         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2529         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2530         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2531         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2532         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2533         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2534         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2535         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2536
2537         /* 802.11 HyperLan 2 */
2538         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2539         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2540         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2541         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2542         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2543         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2544         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2545         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2546         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2547         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2548
2549         /* 802.11 UNII */
2550         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2551         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2552         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2553         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2554         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2555         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2556
2557         /* MMAC(Japan)J52 ch 34,38,42,46 */
2558         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2559         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2560         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2561         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2562 };
2563
2564 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2565 {
2566         struct hw_mode_spec *spec = &rt2x00dev->spec;
2567         struct channel_info *info;
2568         char *tx_power;
2569         unsigned int i;
2570
2571         /*
2572          * Initialize all hw fields.
2573          */
2574         rt2x00dev->hw->flags =
2575             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2576             IEEE80211_HW_SIGNAL_DBM;
2577         rt2x00dev->hw->extra_tx_headroom = 0;
2578
2579         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2580         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2581                                 rt2x00_eeprom_addr(rt2x00dev,
2582                                                    EEPROM_MAC_ADDR_0));
2583
2584         /*
2585          * Initialize hw_mode information.
2586          */
2587         spec->supported_bands = SUPPORT_BAND_2GHZ;
2588         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2589
2590         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2591                 spec->num_channels = 14;
2592                 spec->channels = rf_vals_noseq;
2593         } else {
2594                 spec->num_channels = 14;
2595                 spec->channels = rf_vals_seq;
2596         }
2597
2598         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2599             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2600                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2601                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2602         }
2603
2604         /*
2605          * Create channel information array
2606          */
2607         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2608         if (!info)
2609                 return -ENOMEM;
2610
2611         spec->channels_info = info;
2612
2613         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2614         for (i = 0; i < 14; i++)
2615                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2616
2617         if (spec->num_channels > 14) {
2618                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2619                 for (i = 14; i < spec->num_channels; i++)
2620                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2621         }
2622
2623         return 0;
2624 }
2625
2626 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2627 {
2628         int retval;
2629
2630         /*
2631          * Allocate eeprom data.
2632          */
2633         retval = rt61pci_validate_eeprom(rt2x00dev);
2634         if (retval)
2635                 return retval;
2636
2637         retval = rt61pci_init_eeprom(rt2x00dev);
2638         if (retval)
2639                 return retval;
2640
2641         /*
2642          * Initialize hw specifications.
2643          */
2644         retval = rt61pci_probe_hw_mode(rt2x00dev);
2645         if (retval)
2646                 return retval;
2647
2648         /*
2649          * This device requires firmware and DMA mapped skbs.
2650          */
2651         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2652         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2653         if (!modparam_nohwcrypt)
2654                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2655
2656         /*
2657          * Set the rssi offset.
2658          */
2659         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2660
2661         return 0;
2662 }
2663
2664 /*
2665  * IEEE80211 stack callback functions.
2666  */
2667 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2668                            const struct ieee80211_tx_queue_params *params)
2669 {
2670         struct rt2x00_dev *rt2x00dev = hw->priv;
2671         struct data_queue *queue;
2672         struct rt2x00_field32 field;
2673         int retval;
2674         u32 reg;
2675
2676         /*
2677          * First pass the configuration through rt2x00lib, that will
2678          * update the queue settings and validate the input. After that
2679          * we are free to update the registers based on the value
2680          * in the queue parameter.
2681          */
2682         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2683         if (retval)
2684                 return retval;
2685
2686         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2687
2688         /* Update WMM TXOP register */
2689         if (queue_idx < 2) {
2690                 field.bit_offset = queue_idx * 16;
2691                 field.bit_mask = 0xffff << field.bit_offset;
2692
2693                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2694                 rt2x00_set_field32(&reg, field, queue->txop);
2695                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2696         } else if (queue_idx < 4) {
2697                 field.bit_offset = (queue_idx - 2) * 16;
2698                 field.bit_mask = 0xffff << field.bit_offset;
2699
2700                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2701                 rt2x00_set_field32(&reg, field, queue->txop);
2702                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2703         }
2704
2705         /* Update WMM registers */
2706         field.bit_offset = queue_idx * 4;
2707         field.bit_mask = 0xf << field.bit_offset;
2708
2709         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2710         rt2x00_set_field32(&reg, field, queue->aifs);
2711         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2712
2713         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2714         rt2x00_set_field32(&reg, field, queue->cw_min);
2715         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2716
2717         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2718         rt2x00_set_field32(&reg, field, queue->cw_max);
2719         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2720
2721         return 0;
2722 }
2723
2724 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2725 {
2726         struct rt2x00_dev *rt2x00dev = hw->priv;
2727         u64 tsf;
2728         u32 reg;
2729
2730         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2731         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2732         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2733         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2734
2735         return tsf;
2736 }
2737
2738 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2739         .tx                     = rt2x00mac_tx,
2740         .start                  = rt2x00mac_start,
2741         .stop                   = rt2x00mac_stop,
2742         .add_interface          = rt2x00mac_add_interface,
2743         .remove_interface       = rt2x00mac_remove_interface,
2744         .config                 = rt2x00mac_config,
2745         .config_interface       = rt2x00mac_config_interface,
2746         .configure_filter       = rt2x00mac_configure_filter,
2747         .set_key                = rt2x00mac_set_key,
2748         .get_stats              = rt2x00mac_get_stats,
2749         .bss_info_changed       = rt2x00mac_bss_info_changed,
2750         .conf_tx                = rt61pci_conf_tx,
2751         .get_tx_stats           = rt2x00mac_get_tx_stats,
2752         .get_tsf                = rt61pci_get_tsf,
2753 };
2754
2755 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2756         .irq_handler            = rt61pci_interrupt,
2757         .probe_hw               = rt61pci_probe_hw,
2758         .get_firmware_name      = rt61pci_get_firmware_name,
2759         .get_firmware_crc       = rt61pci_get_firmware_crc,
2760         .load_firmware          = rt61pci_load_firmware,
2761         .initialize             = rt2x00pci_initialize,
2762         .uninitialize           = rt2x00pci_uninitialize,
2763         .get_entry_state        = rt61pci_get_entry_state,
2764         .clear_entry            = rt61pci_clear_entry,
2765         .set_device_state       = rt61pci_set_device_state,
2766         .rfkill_poll            = rt61pci_rfkill_poll,
2767         .link_stats             = rt61pci_link_stats,
2768         .reset_tuner            = rt61pci_reset_tuner,
2769         .link_tuner             = rt61pci_link_tuner,
2770         .write_tx_desc          = rt61pci_write_tx_desc,
2771         .write_tx_data          = rt2x00pci_write_tx_data,
2772         .write_beacon           = rt61pci_write_beacon,
2773         .kick_tx_queue          = rt61pci_kick_tx_queue,
2774         .fill_rxdone            = rt61pci_fill_rxdone,
2775         .config_shared_key      = rt61pci_config_shared_key,
2776         .config_pairwise_key    = rt61pci_config_pairwise_key,
2777         .config_filter          = rt61pci_config_filter,
2778         .config_intf            = rt61pci_config_intf,
2779         .config_erp             = rt61pci_config_erp,
2780         .config_ant             = rt61pci_config_ant,
2781         .config                 = rt61pci_config,
2782 };
2783
2784 static const struct data_queue_desc rt61pci_queue_rx = {
2785         .entry_num              = RX_ENTRIES,
2786         .data_size              = DATA_FRAME_SIZE,
2787         .desc_size              = RXD_DESC_SIZE,
2788         .priv_size              = sizeof(struct queue_entry_priv_pci),
2789 };
2790
2791 static const struct data_queue_desc rt61pci_queue_tx = {
2792         .entry_num              = TX_ENTRIES,
2793         .data_size              = DATA_FRAME_SIZE,
2794         .desc_size              = TXD_DESC_SIZE,
2795         .priv_size              = sizeof(struct queue_entry_priv_pci),
2796 };
2797
2798 static const struct data_queue_desc rt61pci_queue_bcn = {
2799         .entry_num              = 4 * BEACON_ENTRIES,
2800         .data_size              = 0, /* No DMA required for beacons */
2801         .desc_size              = TXINFO_SIZE,
2802         .priv_size              = sizeof(struct queue_entry_priv_pci),
2803 };
2804
2805 static const struct rt2x00_ops rt61pci_ops = {
2806         .name           = KBUILD_MODNAME,
2807         .max_sta_intf   = 1,
2808         .max_ap_intf    = 4,
2809         .eeprom_size    = EEPROM_SIZE,
2810         .rf_size        = RF_SIZE,
2811         .tx_queues      = NUM_TX_QUEUES,
2812         .rx             = &rt61pci_queue_rx,
2813         .tx             = &rt61pci_queue_tx,
2814         .bcn            = &rt61pci_queue_bcn,
2815         .lib            = &rt61pci_rt2x00_ops,
2816         .hw             = &rt61pci_mac80211_ops,
2817 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2818         .debugfs        = &rt61pci_rt2x00debug,
2819 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2820 };
2821
2822 /*
2823  * RT61pci module information.
2824  */
2825 static struct pci_device_id rt61pci_device_table[] = {
2826         /* RT2561s */
2827         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2828         /* RT2561 v2 */
2829         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2830         /* RT2661 */
2831         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2832         { 0, }
2833 };
2834
2835 MODULE_AUTHOR(DRV_PROJECT);
2836 MODULE_VERSION(DRV_VERSION);
2837 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2838 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2839                         "PCI & PCMCIA chipset based cards");
2840 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2841 MODULE_FIRMWARE(FIRMWARE_RT2561);
2842 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2843 MODULE_FIRMWARE(FIRMWARE_RT2661);
2844 MODULE_LICENSE("GPL");
2845
2846 static struct pci_driver rt61pci_driver = {
2847         .name           = KBUILD_MODNAME,
2848         .id_table       = rt61pci_device_table,
2849         .probe          = rt2x00pci_probe,
2850         .remove         = __devexit_p(rt2x00pci_remove),
2851         .suspend        = rt2x00pci_suspend,
2852         .resume         = rt2x00pci_resume,
2853 };
2854
2855 static int __init rt61pci_init(void)
2856 {
2857         return pci_register_driver(&rt61pci_driver);
2858 }
2859
2860 static void __exit rt61pci_exit(void)
2861 {
2862         pci_unregister_driver(&rt61pci_driver);
2863 }
2864
2865 module_init(rt61pci_init);
2866 module_exit(rt61pci_exit);