git.oblomov.eu Git - linux-2.6/blob - drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * Definitions for PCI support.
  38  */
  39 #define FL_BASE_MASK            0x0007
  40 #define FL_BASE0                0x0000
  41 #define FL_BASE1                0x0001
  42 #define FL_BASE2                0x0002
  43 #define FL_BASE3                0x0003
  44 #define FL_BASE4                0x0004
  45 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  46
  47 /* Use successive BARs (PCI base address registers),
  48    else use offset into some specified BAR */
  49 #define FL_BASE_BARS            0x0008
  50
  51 /* do not assign an irq */
  52 #define FL_NOIRQ                0x0080
  53
  54 /* Use the Base address register size to cap number of ports */
  55 #define FL_REGION_SZ_CAP        0x0100
  56
  57 struct pci_board {
  58         unsigned int flags;
  59         unsigned int num_ports;
  60         unsigned int base_baud;
  61         unsigned int uart_offset;
  62         unsigned int reg_shift;
  63         unsigned int first_offset;
  64 };
  65
  66 /*
  67  * init function returns:
  68  *  > 0 - number of ports
  69  *  = 0 - use board->num_ports
  70  *  < 0 - error
  71  */
  72 struct pci_serial_quirk {
  73         u32     vendor;
  74         u32     device;
  75         u32     subvendor;
  76         u32     subdevice;
  77         int     (*init)(struct pci_dev *dev);
  78         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  79                          struct uart_port *port, int idx);
  80         void    (*exit)(struct pci_dev *dev);
  81 };
  82
  83 #define PCI_NUM_BAR_RESOURCES   6
  84
  85 struct serial_private {
  86         unsigned int            nr;
  87         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  88         struct pci_serial_quirk *quirk;
  89         int                     line[0];
  90 };
  91
  92 static void moan_device(const char *str, struct pci_dev *dev)
  93 {
  94         printk(KERN_WARNING "%s: %s\n"
  95                KERN_WARNING "Please send the output of lspci -vv, this\n"
  96                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  97                KERN_WARNING "manufacturer and name of serial board or\n"
  98                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  99                pci_name(dev), str, dev->vendor, dev->device,
 100                dev->subsystem_vendor, dev->subsystem_device);
 101 }
 102
 103 static int
 104 setup_port(struct pci_dev *dev, struct uart_port *port,
 105            int bar, int offset, int regshift)
 106 {
 107         struct serial_private *priv = pci_get_drvdata(dev);
 108         unsigned long base, len;
 109
 110         if (bar >= PCI_NUM_BAR_RESOURCES)
 111                 return -EINVAL;
 112
 113         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 114                 base = pci_resource_start(dev, bar);
 115                 len =  pci_resource_len(dev, bar);
 116
 117                 if (!priv->remapped_bar[bar])
 118                         priv->remapped_bar[bar] = ioremap(base, len);
 119                 if (!priv->remapped_bar[bar])
 120                         return -ENOMEM;
 121
 122                 port->iotype = UPIO_MEM;
 123                 port->mapbase = base + offset;
 124                 port->membase = priv->remapped_bar[bar] + offset;
 125                 port->regshift = regshift;
 126         } else {
 127                 base = pci_resource_start(dev, bar) + offset;
 128                 port->iotype = UPIO_PORT;
 129                 port->iobase = base;
 130         }
 131         return 0;
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(dev, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180                 rc = 1;
 181                 break;
 182         }
 183
 184         return rc;
 185 }
 186
 187 /*
 188  * HP's Diva chip puts the 4th/5th serial port further out, and
 189  * some serial ports are supposed to be hidden on certain models.
 190  */
 191 static int
 192 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 193               struct uart_port *port, int idx)
 194 {
 195         unsigned int offset = board->first_offset;
 196         unsigned int bar = FL_GET_BASE(board->flags);
 197
 198         switch (dev->subsystem_device) {
 199         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 200                 if (idx == 3)
 201                         idx++;
 202                 break;
 203         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 204                 if (idx > 0)
 205                         idx++;
 206                 if (idx > 2)
 207                         idx++;
 208                 break;
 209         }
 210         if (idx > 2)
 211                 offset = 0x18;
 212
 213         offset += idx * board->uart_offset;
 214
 215         return setup_port(dev, port, bar, offset, board->reg_shift);
 216 }
 217
 218 /*
 219  * Added for EKF Intel i960 serial boards
 220  */
 221 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 222 {
 223         unsigned long oldval;
 224
 225         if (!(dev->subsystem_device & 0x1000))
 226                 return -ENODEV;
 227
 228         /* is firmware started? */
 229         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 230         if (oldval == 0x00001000L) { /* RESET value */
 231                 printk(KERN_DEBUG "Local i960 firmware missing");
 232                 return -ENODEV;
 233         }
 234         return 0;
 235 }
 236
 237 /*
 238  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 239  * that the card interrupt be explicitly enabled or disabled.  This
 240  * seems to be mainly needed on card using the PLX which also use I/O
 241  * mapped memory.
 242  */
 243 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 244 {
 245         u8 irq_config;
 246         void __iomem *p;
 247
 248         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 249                 moan_device("no memory in bar 0", dev);
 250                 return 0;
 251         }
 252
 253         irq_config = 0x41;
 254         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 255                 irq_config = 0x43;
 256         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 257             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 258                 /*
 259                  * As the megawolf cards have the int pins active
 260                  * high, and have 2 UART chips, both ints must be
 261                  * enabled on the 9050. Also, the UARTS are set in
 262                  * 16450 mode by default, so we have to enable the
 263                  * 16C950 'enhanced' mode so that we can use the
 264                  * deep FIFOs
 265                  */
 266                 irq_config = 0x5b;
 267         }
 268
 269         /*
 270          * enable/disable interrupts
 271          */
 272         p = ioremap(pci_resource_start(dev, 0), 0x80);
 273         if (p == NULL)
 274                 return -ENOMEM;
 275         writel(irq_config, p + 0x4c);
 276
 277         /*
 278          * Read the register back to ensure that it took effect.
 279          */
 280         readl(p + 0x4c);
 281         iounmap(p);
 282
 283         return 0;
 284 }
 285
 286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 287 {
 288         u8 __iomem *p;
 289
 290         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 291                 return;
 292
 293         /*
 294          * disable interrupts
 295          */
 296         p = ioremap(pci_resource_start(dev, 0), 0x80);
 297         if (p != NULL) {
 298                 writel(0, p + 0x4c);
 299
 300                 /*
 301                  * Read the register back to ensure that it took effect.
 302                  */
 303                 readl(p + 0x4c);
 304                 iounmap(p);
 305         }
 306 }
 307
 308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 309 static int
 310 sbs_setup(struct pci_dev *dev, struct pci_board *board,
 311                 struct uart_port *port, int idx)
 312 {
 313         unsigned int bar, offset = board->first_offset;
 314
 315         bar = 0;
 316
 317         if (idx < 4) {
 318                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 319                 offset += idx * board->uart_offset;
 320         } else if (idx < 8) {
 321                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 322                 offset += idx * board->uart_offset + 0xC00;
 323         } else /* we have only 8 ports on PMC-OCTALPRO */
 324                 return 1;
 325
 326         return setup_port(dev, port, bar, offset, board->reg_shift);
 327 }
 328
 329 /*
 330 * This does initialization for PMC OCTALPRO cards:
 331 * maps the device memory, resets the UARTs (needed, bc
 332 * if the module is removed and inserted again, the card
 333 * is in the sleep mode) and enables global interrupt.
 334 */
 335
 336 /* global control register offset for SBS PMC-OctalPro */
 337 #define OCT_REG_CR_OFF          0x500
 338
 339 static int __devinit sbs_init(struct pci_dev *dev)
 340 {
 341         u8 __iomem *p;
 342
 343         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 344
 345         if (p == NULL)
 346                 return -ENOMEM;
 347         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348         writeb(0x10,p + OCT_REG_CR_OFF);
 349         udelay(50);
 350         writeb(0x0,p + OCT_REG_CR_OFF);
 351
 352         /* Set bit-2 (INTENABLE) of Control Register */
 353         writeb(0x4, p + OCT_REG_CR_OFF);
 354         iounmap(p);
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Disables the global interrupt of PMC-OctalPro
 361  */
 362
 363 static void __devexit sbs_exit(struct pci_dev *dev)
 364 {
 365         u8 __iomem *p;
 366
 367         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 368         if (p != NULL) {
 369                 writeb(0, p + OCT_REG_CR_OFF);
 370         }
 371         iounmap(p);
 372 }
 373
 374 /*
 375  * SIIG serial cards have an PCI interface chip which also controls
 376  * the UART clocking frequency. Each UART can be clocked independently
 377  * (except cards equiped with 4 UARTs) and initial clocking settings
 378  * are stored in the EEPROM chip. It can cause problems because this
 379  * version of serial driver doesn't support differently clocked UART's
 380  * on single PCI card. To prevent this, initialization functions set
 381  * high frequency clocking for all UART's on given card. It is safe (I
 382  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 383  * with other OSes (like M$ DOS).
 384  *
 385  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 386  *
 387  * There is two family of SIIG serial cards with different PCI
 388  * interface chip and different configuration methods:
 389  *     - 10x cards have control registers in IO and/or memory space;
 390  *     - 20x cards have control registers in standard PCI configuration space.
 391  *
 392  * There are also Quartet Serial cards which use Oxford Semiconductor
 393  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 394  *
 395  * Note: some SIIG cards are probed by the parport_serial object.
 396  */
 397
 398 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 399 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 400
 401 static int pci_siig10x_init(struct pci_dev *dev)
 402 {
 403         u16 data;
 404         void __iomem *p;
 405
 406         switch (dev->device & 0xfff8) {
 407         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 408                 data = 0xffdf;
 409                 break;
 410         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 411                 data = 0xf7ff;
 412                 break;
 413         default:                        /* 1S1P, 4S */
 414                 data = 0xfffb;
 415                 break;
 416         }
 417
 418         p = ioremap(pci_resource_start(dev, 0), 0x80);
 419         if (p == NULL)
 420                 return -ENOMEM;
 421
 422         writew(readw(p + 0x28) & data, p + 0x28);
 423         readw(p + 0x28);
 424         iounmap(p);
 425         return 0;
 426 }
 427
 428 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 429 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 430
 431 static int pci_siig20x_init(struct pci_dev *dev)
 432 {
 433         u8 data;
 434
 435         /* Change clock frequency for the first UART. */
 436         pci_read_config_byte(dev, 0x6f, &data);
 437         pci_write_config_byte(dev, 0x6f, data & 0xef);
 438
 439         /* If this card has 2 UART, we have to do the same with second UART. */
 440         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 441             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 442                 pci_read_config_byte(dev, 0x73, &data);
 443                 pci_write_config_byte(dev, 0x73, data & 0xef);
 444         }
 445         return 0;
 446 }
 447
 448 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 449 {
 450         int ret = 0;
 451         if (enable)
 452                 ret = pci_siig10x_init(dev);
 453         return ret;
 454 }
 455
 456 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 457 {
 458         int ret = 0;
 459         if (enable)
 460                 ret = pci_siig20x_init(dev);
 461         return ret;
 462 }
 463
 464 EXPORT_SYMBOL(pci_siig10x_fn);
 465 EXPORT_SYMBOL(pci_siig20x_fn);
 466
 467 /*
 468  * Timedia has an explosion of boards, and to avoid the PCI table from
 469  * growing *huge*, we use this function to collapse some 70 entries
 470  * in the PCI table into one, for sanity's and compactness's sake.
 471  */
 472 static unsigned short timedia_single_port[] = {
 473         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 474 };
 475
 476 static unsigned short timedia_dual_port[] = {
 477         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 478         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 479         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 480         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 481         0xD079, 0
 482 };
 483
 484 static unsigned short timedia_quad_port[] = {
 485         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 486         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 487         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 488         0xB157, 0
 489 };
 490
 491 static unsigned short timedia_eight_port[] = {
 492         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 493         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 494 };
 495
 496 static struct timedia_struct {
 497         int num;
 498         unsigned short *ids;
 499 } timedia_data[] = {
 500         { 1, timedia_single_port },
 501         { 2, timedia_dual_port },
 502         { 4, timedia_quad_port },
 503         { 8, timedia_eight_port },
 504         { 0, NULL }
 505 };
 506
 507 static int __devinit pci_timedia_init(struct pci_dev *dev)
 508 {
 509         unsigned short *ids;
 510         int i, j;
 511
 512         for (i = 0; timedia_data[i].num; i++) {
 513                 ids = timedia_data[i].ids;
 514                 for (j = 0; ids[j]; j++)
 515                         if (dev->subsystem_device == ids[j])
 516                                 return timedia_data[i].num;
 517         }
 518         return 0;
 519 }
 520
 521 /*
 522  * Timedia/SUNIX uses a mixture of BARs and offsets
 523  * Ugh, this is ugly as all hell --- TYT
 524  */
 525 static int
 526 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 527                   struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = 0, offset = board->first_offset;
 530
 531         switch (idx) {
 532         case 0:
 533                 bar = 0;
 534                 break;
 535         case 1:
 536                 offset = board->uart_offset;
 537                 bar = 0;
 538                 break;
 539         case 2:
 540                 bar = 1;
 541                 break;
 542         case 3:
 543                 offset = board->uart_offset;
 544                 bar = 1;
 545         case 4: /* BAR 2 */
 546         case 5: /* BAR 3 */
 547         case 6: /* BAR 4 */
 548         case 7: /* BAR 5 */
 549                 bar = idx - 2;
 550         }
 551
 552         return setup_port(dev, port, bar, offset, board->reg_shift);
 553 }
 554
 555 /*
 556  * Some Titan cards are also a little weird
 557  */
 558 static int
 559 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 560                       struct uart_port *port, int idx)
 561 {
 562         unsigned int bar, offset = board->first_offset;
 563
 564         switch (idx) {
 565         case 0:
 566                 bar = 1;
 567                 break;
 568         case 1:
 569                 bar = 2;
 570                 break;
 571         default:
 572                 bar = 4;
 573                 offset = (idx - 2) * board->uart_offset;
 574         }
 575
 576         return setup_port(dev, port, bar, offset, board->reg_shift);
 577 }
 578
 579 static int __devinit pci_xircom_init(struct pci_dev *dev)
 580 {
 581         msleep(100);
 582         return 0;
 583 }
 584
 585 static int __devinit pci_netmos_init(struct pci_dev *dev)
 586 {
 587         /* subdevice 0x00PS means <P> parallel, <S> serial */
 588         unsigned int num_serial = dev->subsystem_device & 0xf;
 589
 590         if (num_serial == 0)
 591                 return -ENODEV;
 592         return num_serial;
 593 }
 594
 595 static int
 596 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 597                   struct uart_port *port, int idx)
 598 {
 599         unsigned int bar, offset = board->first_offset, maxnr;
 600
 601         bar = FL_GET_BASE(board->flags);
 602         if (board->flags & FL_BASE_BARS)
 603                 bar += idx;
 604         else
 605                 offset += idx * board->uart_offset;
 606
 607         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 608                 (8 << board->reg_shift);
 609
 610         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 611                 return 1;
 612
 613         return setup_port(dev, port, bar, offset, board->reg_shift);
 614 }
 615
 616 /* This should be in linux/pci_ids.h */
 617 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 618 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 619 #define PCI_DEVICE_ID_OCTPRO            0x0001
 620 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 621 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 622 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 623 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 624
 625 /*
 626  * Master list of serial port init/setup/exit quirks.
 627  * This does not describe the general nature of the port.
 628  * (ie, baud base, number and location of ports, etc)
 629  *
 630  * This list is ordered alphabetically by vendor then device.
 631  * Specific entries must come before more generic entries.
 632  */
 633 static struct pci_serial_quirk pci_serial_quirks[] = {
 634         /*
 635          * AFAVLAB cards.
 636          *  It is not clear whether this applies to all products.
 637          */
 638         {
 639                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 640                 .device         = PCI_ANY_ID,
 641                 .subvendor      = PCI_ANY_ID,
 642                 .subdevice      = PCI_ANY_ID,
 643                 .setup          = afavlab_setup,
 644         },
 645         /*
 646          * HP Diva
 647          */
 648         {
 649                 .vendor         = PCI_VENDOR_ID_HP,
 650                 .device         = PCI_DEVICE_ID_HP_DIVA,
 651                 .subvendor      = PCI_ANY_ID,
 652                 .subdevice      = PCI_ANY_ID,
 653                 .init           = pci_hp_diva_init,
 654                 .setup          = pci_hp_diva_setup,
 655         },
 656         /*
 657          * Intel
 658          */
 659         {
 660                 .vendor         = PCI_VENDOR_ID_INTEL,
 661                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 662                 .subvendor      = 0xe4bf,
 663                 .subdevice      = PCI_ANY_ID,
 664                 .init           = pci_inteli960ni_init,
 665                 .setup          = pci_default_setup,
 666         },
 667         /*
 668          * Panacom
 669          */
 670         {
 671                 .vendor         = PCI_VENDOR_ID_PANACOM,
 672                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 673                 .subvendor      = PCI_ANY_ID,
 674                 .subdevice      = PCI_ANY_ID,
 675                 .init           = pci_plx9050_init,
 676                 .setup          = pci_default_setup,
 677                 .exit           = __devexit_p(pci_plx9050_exit),
 678         },
 679         {
 680                 .vendor         = PCI_VENDOR_ID_PANACOM,
 681                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 682                 .subvendor      = PCI_ANY_ID,
 683                 .subdevice      = PCI_ANY_ID,
 684                 .init           = pci_plx9050_init,
 685                 .setup          = pci_default_setup,
 686                 .exit           = __devexit_p(pci_plx9050_exit),
 687         },
 688         /*
 689          * PLX
 690          */
 691         {
 692                 .vendor         = PCI_VENDOR_ID_PLX,
 693                 .device         = PCI_DEVICE_ID_PLX_9050,
 694                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 695                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 696                 .init           = pci_plx9050_init,
 697                 .setup          = pci_default_setup,
 698                 .exit           = __devexit_p(pci_plx9050_exit),
 699         },
 700         {
 701                 .vendor         = PCI_VENDOR_ID_PLX,
 702                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 703                 .subvendor      = PCI_VENDOR_ID_PLX,
 704                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 705                 .init           = pci_plx9050_init,
 706                 .setup          = pci_default_setup,
 707                 .exit           = __devexit_p(pci_plx9050_exit),
 708         },
 709         /*
 710          * SBS Technologies, Inc., PMC-OCTALPRO 232
 711          */
 712         {
 713                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 714                 .device         = PCI_DEVICE_ID_OCTPRO,
 715                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 716                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 717                 .init           = sbs_init,
 718                 .setup          = sbs_setup,
 719                 .exit           = __devexit_p(sbs_exit),
 720         },
 721         /*
 722          * SBS Technologies, Inc., PMC-OCTALPRO 422
 723          */
 724         {
 725                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 726                 .device         = PCI_DEVICE_ID_OCTPRO,
 727                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 728                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 729                 .init           = sbs_init,
 730                 .setup          = sbs_setup,
 731                 .exit           = __devexit_p(sbs_exit),
 732         },
 733         /*
 734          * SBS Technologies, Inc., P-Octal 232
 735          */
 736         {
 737                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 738                 .device         = PCI_DEVICE_ID_OCTPRO,
 739                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 740                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 741                 .init           = sbs_init,
 742                 .setup          = sbs_setup,
 743                 .exit           = __devexit_p(sbs_exit),
 744         },
 745         /*
 746          * SBS Technologies, Inc., P-Octal 422
 747          */
 748         {
 749                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 750                 .device         = PCI_DEVICE_ID_OCTPRO,
 751                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 752                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 753                 .init           = sbs_init,
 754                 .setup          = sbs_setup,
 755                 .exit           = __devexit_p(sbs_exit),
 756         },
 757
 758         /*
 759          * SIIG cards.
 760          *  It is not clear whether these could be collapsed.
 761          */
 762         {
 763                 .vendor         = PCI_VENDOR_ID_SIIG,
 764                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 765                 .subvendor      = PCI_ANY_ID,
 766                 .subdevice      = PCI_ANY_ID,
 767                 .init           = pci_siig10x_init,
 768                 .setup          = pci_default_setup,
 769         },
 770         {
 771                 .vendor         = PCI_VENDOR_ID_SIIG,
 772                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 773                 .subvendor      = PCI_ANY_ID,
 774                 .subdevice      = PCI_ANY_ID,
 775                 .init           = pci_siig10x_init,
 776                 .setup          = pci_default_setup,
 777         },
 778         {
 779                 .vendor         = PCI_VENDOR_ID_SIIG,
 780                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 781                 .subvendor      = PCI_ANY_ID,
 782                 .subdevice      = PCI_ANY_ID,
 783                 .init           = pci_siig10x_init,
 784                 .setup          = pci_default_setup,
 785         },
 786         {
 787                 .vendor         = PCI_VENDOR_ID_SIIG,
 788                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 789                 .subvendor      = PCI_ANY_ID,
 790                 .subdevice      = PCI_ANY_ID,
 791                 .init           = pci_siig10x_init,
 792                 .setup          = pci_default_setup,
 793         },
 794         {
 795                 .vendor         = PCI_VENDOR_ID_SIIG,
 796                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 797                 .subvendor      = PCI_ANY_ID,
 798                 .subdevice      = PCI_ANY_ID,
 799                 .init           = pci_siig10x_init,
 800                 .setup          = pci_default_setup,
 801         },
 802         {
 803                 .vendor         = PCI_VENDOR_ID_SIIG,
 804                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 805                 .subvendor      = PCI_ANY_ID,
 806                 .subdevice      = PCI_ANY_ID,
 807                 .init           = pci_siig10x_init,
 808                 .setup          = pci_default_setup,
 809         },
 810         {
 811                 .vendor         = PCI_VENDOR_ID_SIIG,
 812                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 813                 .subvendor      = PCI_ANY_ID,
 814                 .subdevice      = PCI_ANY_ID,
 815                 .init           = pci_siig10x_init,
 816                 .setup          = pci_default_setup,
 817         },
 818         {
 819                 .vendor         = PCI_VENDOR_ID_SIIG,
 820                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 821                 .subvendor      = PCI_ANY_ID,
 822                 .subdevice      = PCI_ANY_ID,
 823                 .init           = pci_siig10x_init,
 824                 .setup          = pci_default_setup,
 825         },
 826         {
 827                 .vendor         = PCI_VENDOR_ID_SIIG,
 828                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 829                 .subvendor      = PCI_ANY_ID,
 830                 .subdevice      = PCI_ANY_ID,
 831                 .init           = pci_siig10x_init,
 832                 .setup          = pci_default_setup,
 833         },
 834         {
 835                 .vendor         = PCI_VENDOR_ID_SIIG,
 836                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 837                 .subvendor      = PCI_ANY_ID,
 838                 .subdevice      = PCI_ANY_ID,
 839                 .init           = pci_siig20x_init,
 840                 .setup          = pci_default_setup,
 841         },
 842         {
 843                 .vendor         = PCI_VENDOR_ID_SIIG,
 844                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 845                 .subvendor      = PCI_ANY_ID,
 846                 .subdevice      = PCI_ANY_ID,
 847                 .init           = pci_siig20x_init,
 848                 .setup          = pci_default_setup,
 849         },
 850         {
 851                 .vendor         = PCI_VENDOR_ID_SIIG,
 852                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 853                 .subvendor      = PCI_ANY_ID,
 854                 .subdevice      = PCI_ANY_ID,
 855                 .init           = pci_siig20x_init,
 856                 .setup          = pci_default_setup,
 857         },
 858         {
 859                 .vendor         = PCI_VENDOR_ID_SIIG,
 860                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 861                 .subvendor      = PCI_ANY_ID,
 862                 .subdevice      = PCI_ANY_ID,
 863                 .init           = pci_siig20x_init,
 864                 .setup          = pci_default_setup,
 865         },
 866         {       .vendor         = PCI_VENDOR_ID_SIIG,
 867                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 868                 .subvendor      = PCI_ANY_ID,
 869                 .subdevice      = PCI_ANY_ID,
 870                 .init           = pci_siig20x_init,
 871                 .setup          = pci_default_setup,
 872         },
 873         {
 874                 .vendor         = PCI_VENDOR_ID_SIIG,
 875                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 876                 .subvendor      = PCI_ANY_ID,
 877                 .subdevice      = PCI_ANY_ID,
 878                 .init           = pci_siig20x_init,
 879                 .setup          = pci_default_setup,
 880         },
 881         {
 882                 .vendor         = PCI_VENDOR_ID_SIIG,
 883                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 884                 .subvendor      = PCI_ANY_ID,
 885                 .subdevice      = PCI_ANY_ID,
 886                 .init           = pci_siig20x_init,
 887                 .setup          = pci_default_setup,
 888         },
 889         {
 890                 .vendor         = PCI_VENDOR_ID_SIIG,
 891                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 892                 .subvendor      = PCI_ANY_ID,
 893                 .subdevice      = PCI_ANY_ID,
 894                 .init           = pci_siig20x_init,
 895                 .setup          = pci_default_setup,
 896         },
 897         {
 898                 .vendor         = PCI_VENDOR_ID_SIIG,
 899                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 900                 .subvendor      = PCI_ANY_ID,
 901                 .subdevice      = PCI_ANY_ID,
 902                 .init           = pci_siig20x_init,
 903                 .setup          = pci_default_setup,
 904         },
 905         /*
 906          * Titan cards
 907          */
 908         {
 909                 .vendor         = PCI_VENDOR_ID_TITAN,
 910                 .device         = PCI_DEVICE_ID_TITAN_400L,
 911                 .subvendor      = PCI_ANY_ID,
 912                 .subdevice      = PCI_ANY_ID,
 913                 .setup          = titan_400l_800l_setup,
 914         },
 915         {
 916                 .vendor         = PCI_VENDOR_ID_TITAN,
 917                 .device         = PCI_DEVICE_ID_TITAN_800L,
 918                 .subvendor      = PCI_ANY_ID,
 919                 .subdevice      = PCI_ANY_ID,
 920                 .setup          = titan_400l_800l_setup,
 921         },
 922         /*
 923          * Timedia cards
 924          */
 925         {
 926                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 927                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 928                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 929                 .subdevice      = PCI_ANY_ID,
 930                 .init           = pci_timedia_init,
 931                 .setup          = pci_timedia_setup,
 932         },
 933         {
 934                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 935                 .device         = PCI_ANY_ID,
 936                 .subvendor      = PCI_ANY_ID,
 937                 .subdevice      = PCI_ANY_ID,
 938                 .setup          = pci_timedia_setup,
 939         },
 940         /*
 941          * Xircom cards
 942          */
 943         {
 944                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 945                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 946                 .subvendor      = PCI_ANY_ID,
 947                 .subdevice      = PCI_ANY_ID,
 948                 .init           = pci_xircom_init,
 949                 .setup          = pci_default_setup,
 950         },
 951         /*
 952          * Netmos cards
 953          */
 954         {
 955                 .vendor         = PCI_VENDOR_ID_NETMOS,
 956                 .device         = PCI_ANY_ID,
 957                 .subvendor      = PCI_ANY_ID,
 958                 .subdevice      = PCI_ANY_ID,
 959                 .init           = pci_netmos_init,
 960                 .setup          = pci_default_setup,
 961         },
 962         /*
 963          * Default "match everything" terminator entry
 964          */
 965         {
 966                 .vendor         = PCI_ANY_ID,
 967                 .device         = PCI_ANY_ID,
 968                 .subvendor      = PCI_ANY_ID,
 969                 .subdevice      = PCI_ANY_ID,
 970                 .setup          = pci_default_setup,
 971         }
 972 };
 973
 974 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 975 {
 976         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 977 }
 978
 979 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 980 {
 981         struct pci_serial_quirk *quirk;
 982
 983         for (quirk = pci_serial_quirks; ; quirk++)
 984                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 985                     quirk_id_matches(quirk->device, dev->device) &&
 986                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 987                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 988                         break;
 989         return quirk;
 990 }
 991
 992 static _INLINE_ int
 993 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 994 {
 995         if (board->flags & FL_NOIRQ)
 996                 return 0;
 997         else
 998                 return dev->irq;
 999 }
1000
1001 /*
1002  * This is the configuration table for all of the PCI serial boards
1003  * which we support.  It is directly indexed by the pci_board_num_t enum
1004  * value, which is encoded in the pci_device_id PCI probe table's
1005  * driver_data member.
1006  *
1007  * The makeup of these names are:
1008  *  pbn_bn{_bt}_n_baud
1009  *
1010  *  bn   = PCI BAR number
1011  *  bt   = Index using PCI BARs
1012  *  n    = number of serial ports
1013  *  baud = baud rate
1014  *
1015  * This table is sorted by (in order): baud, bt, bn, n.
1016  *
1017  * Please note: in theory if n = 1, _bt infix should make no difference.
1018  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1019  */
1020 enum pci_board_num_t {
1021         pbn_default = 0,
1022
1023         pbn_b0_1_115200,
1024         pbn_b0_2_115200,
1025         pbn_b0_4_115200,
1026         pbn_b0_5_115200,
1027
1028         pbn_b0_1_921600,
1029         pbn_b0_2_921600,
1030         pbn_b0_4_921600,
1031
1032         pbn_b0_2_1130000,
1033
1034         pbn_b0_4_1152000,
1035
1036         pbn_b0_bt_1_115200,
1037         pbn_b0_bt_2_115200,
1038         pbn_b0_bt_8_115200,
1039
1040         pbn_b0_bt_1_460800,
1041         pbn_b0_bt_2_460800,
1042         pbn_b0_bt_4_460800,
1043
1044         pbn_b0_bt_1_921600,
1045         pbn_b0_bt_2_921600,
1046         pbn_b0_bt_4_921600,
1047         pbn_b0_bt_8_921600,
1048
1049         pbn_b1_1_115200,
1050         pbn_b1_2_115200,
1051         pbn_b1_4_115200,
1052         pbn_b1_8_115200,
1053
1054         pbn_b1_1_921600,
1055         pbn_b1_2_921600,
1056         pbn_b1_4_921600,
1057         pbn_b1_8_921600,
1058
1059         pbn_b1_bt_2_921600,
1060
1061         pbn_b1_1_1382400,
1062         pbn_b1_2_1382400,
1063         pbn_b1_4_1382400,
1064         pbn_b1_8_1382400,
1065
1066         pbn_b2_1_115200,
1067         pbn_b2_8_115200,
1068
1069         pbn_b2_1_460800,
1070         pbn_b2_4_460800,
1071         pbn_b2_8_460800,
1072         pbn_b2_16_460800,
1073
1074         pbn_b2_1_921600,
1075         pbn_b2_4_921600,
1076         pbn_b2_8_921600,
1077
1078         pbn_b2_bt_1_115200,
1079         pbn_b2_bt_2_115200,
1080         pbn_b2_bt_4_115200,
1081
1082         pbn_b2_bt_2_921600,
1083         pbn_b2_bt_4_921600,
1084
1085         pbn_b3_4_115200,
1086         pbn_b3_8_115200,
1087
1088         /*
1089          * Board-specific versions.
1090          */
1091         pbn_panacom,
1092         pbn_panacom2,
1093         pbn_panacom4,
1094         pbn_plx_romulus,
1095         pbn_oxsemi,
1096         pbn_intel_i960,
1097         pbn_sgi_ioc3,
1098         pbn_nec_nile4,
1099         pbn_computone_4,
1100         pbn_computone_6,
1101         pbn_computone_8,
1102         pbn_sbsxrsio,
1103         pbn_exar_XR17C152,
1104         pbn_exar_XR17C154,
1105         pbn_exar_XR17C158,
1106 };
1107
1108 /*
1109  * uart_offset - the space between channels
1110  * reg_shift   - describes how the UART registers are mapped
1111  *               to PCI memory by the card.
1112  * For example IER register on SBS, Inc. PMC-OctPro is located at
1113  * offset 0x10 from the UART base, while UART_IER is defined as 1
1114  * in include/linux/serial_reg.h,
1115  * see first lines of serial_in() and serial_out() in 8250.c
1116 */
1117
1118 static struct pci_board pci_boards[] __devinitdata = {
1119         [pbn_default] = {
1120                 .flags          = FL_BASE0,
1121                 .num_ports      = 1,
1122                 .base_baud      = 115200,
1123                 .uart_offset    = 8,
1124         },
1125         [pbn_b0_1_115200] = {
1126                 .flags          = FL_BASE0,
1127                 .num_ports      = 1,
1128                 .base_baud      = 115200,
1129                 .uart_offset    = 8,
1130         },
1131         [pbn_b0_2_115200] = {
1132                 .flags          = FL_BASE0,
1133                 .num_ports      = 2,
1134                 .base_baud      = 115200,
1135                 .uart_offset    = 8,
1136         },
1137         [pbn_b0_4_115200] = {
1138                 .flags          = FL_BASE0,
1139                 .num_ports      = 4,
1140                 .base_baud      = 115200,
1141                 .uart_offset    = 8,
1142         },
1143         [pbn_b0_5_115200] = {
1144                 .flags          = FL_BASE0,
1145                 .num_ports      = 5,
1146                 .base_baud      = 115200,
1147                 .uart_offset    = 8,
1148         },
1149
1150         [pbn_b0_1_921600] = {
1151                 .flags          = FL_BASE0,
1152                 .num_ports      = 1,
1153                 .base_baud      = 921600,
1154                 .uart_offset    = 8,
1155         },
1156         [pbn_b0_2_921600] = {
1157                 .flags          = FL_BASE0,
1158                 .num_ports      = 2,
1159                 .base_baud      = 921600,
1160                 .uart_offset    = 8,
1161         },
1162         [pbn_b0_4_921600] = {
1163                 .flags          = FL_BASE0,
1164                 .num_ports      = 4,
1165                 .base_baud      = 921600,
1166                 .uart_offset    = 8,
1167         },
1168
1169         [pbn_b0_2_1130000] = {
1170                 .flags          = FL_BASE0,
1171                 .num_ports      = 2,
1172                 .base_baud      = 1130000,
1173                 .uart_offset    = 8,
1174         },
1175
1176         [pbn_b0_4_1152000] = {
1177                 .flags          = FL_BASE0,
1178                 .num_ports      = 4,
1179                 .base_baud      = 1152000,
1180                 .uart_offset    = 8,
1181         },
1182
1183         [pbn_b0_bt_1_115200] = {
1184                 .flags          = FL_BASE0|FL_BASE_BARS,
1185                 .num_ports      = 1,
1186                 .base_baud      = 115200,
1187                 .uart_offset    = 8,
1188         },
1189         [pbn_b0_bt_2_115200] = {
1190                 .flags          = FL_BASE0|FL_BASE_BARS,
1191                 .num_ports      = 2,
1192                 .base_baud      = 115200,
1193                 .uart_offset    = 8,
1194         },
1195         [pbn_b0_bt_8_115200] = {
1196                 .flags          = FL_BASE0|FL_BASE_BARS,
1197                 .num_ports      = 8,
1198                 .base_baud      = 115200,
1199                 .uart_offset    = 8,
1200         },
1201
1202         [pbn_b0_bt_1_460800] = {
1203                 .flags          = FL_BASE0|FL_BASE_BARS,
1204                 .num_ports      = 1,
1205                 .base_baud      = 460800,
1206                 .uart_offset    = 8,
1207         },
1208         [pbn_b0_bt_2_460800] = {
1209                 .flags          = FL_BASE0|FL_BASE_BARS,
1210                 .num_ports      = 2,
1211                 .base_baud      = 460800,
1212                 .uart_offset    = 8,
1213         },
1214         [pbn_b0_bt_4_460800] = {
1215                 .flags          = FL_BASE0|FL_BASE_BARS,
1216                 .num_ports      = 4,
1217                 .base_baud      = 460800,
1218                 .uart_offset    = 8,
1219         },
1220
1221         [pbn_b0_bt_1_921600] = {
1222                 .flags          = FL_BASE0|FL_BASE_BARS,
1223                 .num_ports      = 1,
1224                 .base_baud      = 921600,
1225                 .uart_offset    = 8,
1226         },
1227         [pbn_b0_bt_2_921600] = {
1228                 .flags          = FL_BASE0|FL_BASE_BARS,
1229                 .num_ports      = 2,
1230                 .base_baud      = 921600,
1231                 .uart_offset    = 8,
1232         },
1233         [pbn_b0_bt_4_921600] = {
1234                 .flags          = FL_BASE0|FL_BASE_BARS,
1235                 .num_ports      = 4,
1236                 .base_baud      = 921600,
1237                 .uart_offset    = 8,
1238         },
1239         [pbn_b0_bt_8_921600] = {
1240                 .flags          = FL_BASE0|FL_BASE_BARS,
1241                 .num_ports      = 8,
1242                 .base_baud      = 921600,
1243                 .uart_offset    = 8,
1244         },
1245
1246         [pbn_b1_1_115200] = {
1247                 .flags          = FL_BASE1,
1248                 .num_ports      = 1,
1249                 .base_baud      = 115200,
1250                 .uart_offset    = 8,
1251         },
1252         [pbn_b1_2_115200] = {
1253                 .flags          = FL_BASE1,
1254                 .num_ports      = 2,
1255                 .base_baud      = 115200,
1256                 .uart_offset    = 8,
1257         },
1258         [pbn_b1_4_115200] = {
1259                 .flags          = FL_BASE1,
1260                 .num_ports      = 4,
1261                 .base_baud      = 115200,
1262                 .uart_offset    = 8,
1263         },
1264         [pbn_b1_8_115200] = {
1265                 .flags          = FL_BASE1,
1266                 .num_ports      = 8,
1267                 .base_baud      = 115200,
1268                 .uart_offset    = 8,
1269         },
1270
1271         [pbn_b1_1_921600] = {
1272                 .flags          = FL_BASE1,
1273                 .num_ports      = 1,
1274                 .base_baud      = 921600,
1275                 .uart_offset    = 8,
1276         },
1277         [pbn_b1_2_921600] = {
1278                 .flags          = FL_BASE1,
1279                 .num_ports      = 2,
1280                 .base_baud      = 921600,
1281                 .uart_offset    = 8,
1282         },
1283         [pbn_b1_4_921600] = {
1284                 .flags          = FL_BASE1,
1285                 .num_ports      = 4,
1286                 .base_baud      = 921600,
1287                 .uart_offset    = 8,
1288         },
1289         [pbn_b1_8_921600] = {
1290                 .flags          = FL_BASE1,
1291                 .num_ports      = 8,
1292                 .base_baud      = 921600,
1293                 .uart_offset    = 8,
1294         },
1295
1296         [pbn_b1_bt_2_921600] = {
1297                 .flags          = FL_BASE1|FL_BASE_BARS,
1298                 .num_ports      = 2,
1299                 .base_baud      = 921600,
1300                 .uart_offset    = 8,
1301         },
1302
1303         [pbn_b1_1_1382400] = {
1304                 .flags          = FL_BASE1,
1305                 .num_ports      = 1,
1306                 .base_baud      = 1382400,
1307                 .uart_offset    = 8,
1308         },
1309         [pbn_b1_2_1382400] = {
1310                 .flags          = FL_BASE1,
1311                 .num_ports      = 2,
1312                 .base_baud      = 1382400,
1313                 .uart_offset    = 8,
1314         },
1315         [pbn_b1_4_1382400] = {
1316                 .flags          = FL_BASE1,
1317                 .num_ports      = 4,
1318                 .base_baud      = 1382400,
1319                 .uart_offset    = 8,
1320         },
1321         [pbn_b1_8_1382400] = {
1322                 .flags          = FL_BASE1,
1323                 .num_ports      = 8,
1324                 .base_baud      = 1382400,
1325                 .uart_offset    = 8,
1326         },
1327
1328         [pbn_b2_1_115200] = {
1329                 .flags          = FL_BASE2,
1330                 .num_ports      = 1,
1331                 .base_baud      = 115200,
1332                 .uart_offset    = 8,
1333         },
1334         [pbn_b2_8_115200] = {
1335                 .flags          = FL_BASE2,
1336                 .num_ports      = 8,
1337                 .base_baud      = 115200,
1338                 .uart_offset    = 8,
1339         },
1340
1341         [pbn_b2_1_460800] = {
1342                 .flags          = FL_BASE2,
1343                 .num_ports      = 1,
1344                 .base_baud      = 460800,
1345                 .uart_offset    = 8,
1346         },
1347         [pbn_b2_4_460800] = {
1348                 .flags          = FL_BASE2,
1349                 .num_ports      = 4,
1350                 .base_baud      = 460800,
1351                 .uart_offset    = 8,
1352         },
1353         [pbn_b2_8_460800] = {
1354                 .flags          = FL_BASE2,
1355                 .num_ports      = 8,
1356                 .base_baud      = 460800,
1357                 .uart_offset    = 8,
1358         },
1359         [pbn_b2_16_460800] = {
1360                 .flags          = FL_BASE2,
1361                 .num_ports      = 16,
1362                 .base_baud      = 460800,
1363                 .uart_offset    = 8,
1364          },
1365
1366         [pbn_b2_1_921600] = {
1367                 .flags          = FL_BASE2,
1368                 .num_ports      = 1,
1369                 .base_baud      = 921600,
1370                 .uart_offset    = 8,
1371         },
1372         [pbn_b2_4_921600] = {
1373                 .flags          = FL_BASE2,
1374                 .num_ports      = 4,
1375                 .base_baud      = 921600,
1376                 .uart_offset    = 8,
1377         },
1378         [pbn_b2_8_921600] = {
1379                 .flags          = FL_BASE2,
1380                 .num_ports      = 8,
1381                 .base_baud      = 921600,
1382                 .uart_offset    = 8,
1383         },
1384
1385         [pbn_b2_bt_1_115200] = {
1386                 .flags          = FL_BASE2|FL_BASE_BARS,
1387                 .num_ports      = 1,
1388                 .base_baud      = 115200,
1389                 .uart_offset    = 8,
1390         },
1391         [pbn_b2_bt_2_115200] = {
1392                 .flags          = FL_BASE2|FL_BASE_BARS,
1393                 .num_ports      = 2,
1394                 .base_baud      = 115200,
1395                 .uart_offset    = 8,
1396         },
1397         [pbn_b2_bt_4_115200] = {
1398                 .flags          = FL_BASE2|FL_BASE_BARS,
1399                 .num_ports      = 4,
1400                 .base_baud      = 115200,
1401                 .uart_offset    = 8,
1402         },
1403
1404         [pbn_b2_bt_2_921600] = {
1405                 .flags          = FL_BASE2|FL_BASE_BARS,
1406                 .num_ports      = 2,
1407                 .base_baud      = 921600,
1408                 .uart_offset    = 8,
1409         },
1410         [pbn_b2_bt_4_921600] = {
1411                 .flags          = FL_BASE2|FL_BASE_BARS,
1412                 .num_ports      = 4,
1413                 .base_baud      = 921600,
1414                 .uart_offset    = 8,
1415         },
1416
1417         [pbn_b3_4_115200] = {
1418                 .flags          = FL_BASE3,
1419                 .num_ports      = 4,
1420                 .base_baud      = 115200,
1421                 .uart_offset    = 8,
1422         },
1423         [pbn_b3_8_115200] = {
1424                 .flags          = FL_BASE3,
1425                 .num_ports      = 8,
1426                 .base_baud      = 115200,
1427                 .uart_offset    = 8,
1428         },
1429
1430         /*
1431          * Entries following this are board-specific.
1432          */
1433
1434         /*
1435          * Panacom - IOMEM
1436          */
1437         [pbn_panacom] = {
1438                 .flags          = FL_BASE2,
1439                 .num_ports      = 2,
1440                 .base_baud      = 921600,
1441                 .uart_offset    = 0x400,
1442                 .reg_shift      = 7,
1443         },
1444         [pbn_panacom2] = {
1445                 .flags          = FL_BASE2|FL_BASE_BARS,
1446                 .num_ports      = 2,
1447                 .base_baud      = 921600,
1448                 .uart_offset    = 0x400,
1449                 .reg_shift      = 7,
1450         },
1451         [pbn_panacom4] = {
1452                 .flags          = FL_BASE2|FL_BASE_BARS,
1453                 .num_ports      = 4,
1454                 .base_baud      = 921600,
1455                 .uart_offset    = 0x400,
1456                 .reg_shift      = 7,
1457         },
1458
1459         /* I think this entry is broken - the first_offset looks wrong --rmk */
1460         [pbn_plx_romulus] = {
1461                 .flags          = FL_BASE2,
1462                 .num_ports      = 4,
1463                 .base_baud      = 921600,
1464                 .uart_offset    = 8 << 2,
1465                 .reg_shift      = 2,
1466                 .first_offset   = 0x03,
1467         },
1468
1469         /*
1470          * This board uses the size of PCI Base region 0 to
1471          * signal now many ports are available
1472          */
1473         [pbn_oxsemi] = {
1474                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1475                 .num_ports      = 32,
1476                 .base_baud      = 115200,
1477                 .uart_offset    = 8,
1478         },
1479
1480         /*
1481          * EKF addition for i960 Boards form EKF with serial port.
1482          * Max 256 ports.
1483          */
1484         [pbn_intel_i960] = {
1485                 .flags          = FL_BASE0,
1486                 .num_ports      = 32,
1487                 .base_baud      = 921600,
1488                 .uart_offset    = 8 << 2,
1489                 .reg_shift      = 2,
1490                 .first_offset   = 0x10000,
1491         },
1492         [pbn_sgi_ioc3] = {
1493                 .flags          = FL_BASE0|FL_NOIRQ,
1494                 .num_ports      = 1,
1495                 .base_baud      = 458333,
1496                 .uart_offset    = 8,
1497                 .reg_shift      = 0,
1498                 .first_offset   = 0x20178,
1499         },
1500
1501         /*
1502          * NEC Vrc-5074 (Nile 4) builtin UART.
1503          */
1504         [pbn_nec_nile4] = {
1505                 .flags          = FL_BASE0,
1506                 .num_ports      = 1,
1507                 .base_baud      = 520833,
1508                 .uart_offset    = 8 << 3,
1509                 .reg_shift      = 3,
1510                 .first_offset   = 0x300,
1511         },
1512
1513         /*
1514          * Computone - uses IOMEM.
1515          */
1516         [pbn_computone_4] = {
1517                 .flags          = FL_BASE0,
1518                 .num_ports      = 4,
1519                 .base_baud      = 921600,
1520                 .uart_offset    = 0x40,
1521                 .reg_shift      = 2,
1522                 .first_offset   = 0x200,
1523         },
1524         [pbn_computone_6] = {
1525                 .flags          = FL_BASE0,
1526                 .num_ports      = 6,
1527                 .base_baud      = 921600,
1528                 .uart_offset    = 0x40,
1529                 .reg_shift      = 2,
1530                 .first_offset   = 0x200,
1531         },
1532         [pbn_computone_8] = {
1533                 .flags          = FL_BASE0,
1534                 .num_ports      = 8,
1535                 .base_baud      = 921600,
1536                 .uart_offset    = 0x40,
1537                 .reg_shift      = 2,
1538                 .first_offset   = 0x200,
1539         },
1540         [pbn_sbsxrsio] = {
1541                 .flags          = FL_BASE0,
1542                 .num_ports      = 8,
1543                 .base_baud      = 460800,
1544                 .uart_offset    = 256,
1545                 .reg_shift      = 4,
1546         },
1547         /*
1548          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1549          *  Only basic 16550A support.
1550          *  XR17C15[24] are not tested, but they should work.
1551          */
1552         [pbn_exar_XR17C152] = {
1553                 .flags          = FL_BASE0,
1554                 .num_ports      = 2,
1555                 .base_baud      = 921600,
1556                 .uart_offset    = 0x200,
1557         },
1558         [pbn_exar_XR17C154] = {
1559                 .flags          = FL_BASE0,
1560                 .num_ports      = 4,
1561                 .base_baud      = 921600,
1562                 .uart_offset    = 0x200,
1563         },
1564         [pbn_exar_XR17C158] = {
1565                 .flags          = FL_BASE0,
1566                 .num_ports      = 8,
1567                 .base_baud      = 921600,
1568                 .uart_offset    = 0x200,
1569         },
1570 };
1571
1572 /*
1573  * Given a complete unknown PCI device, try to use some heuristics to
1574  * guess what the configuration might be, based on the pitiful PCI
1575  * serial specs.  Returns 0 on success, 1 on failure.
1576  */
1577 static int __devinit
1578 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1579 {
1580         int num_iomem, num_port, first_port = -1, i;
1581
1582         /*
1583          * If it is not a communications device or the programming
1584          * interface is greater than 6, give up.
1585          *
1586          * (Should we try to make guesses for multiport serial devices
1587          * later?)
1588          */
1589         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1590              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1591             (dev->class & 0xff) > 6)
1592                 return -ENODEV;
1593
1594         num_iomem = num_port = 0;
1595         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1596                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1597                         num_port++;
1598                         if (first_port == -1)
1599                                 first_port = i;
1600                 }
1601                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1602                         num_iomem++;
1603         }
1604
1605         /*
1606          * If there is 1 or 0 iomem regions, and exactly one port,
1607          * use it.  We guess the number of ports based on the IO
1608          * region size.
1609          */
1610         if (num_iomem <= 1 && num_port == 1) {
1611                 board->flags = first_port;
1612                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1613                 return 0;
1614         }
1615
1616         /*
1617          * Now guess if we've got a board which indexes by BARs.
1618          * Each IO BAR should be 8 bytes, and they should follow
1619          * consecutively.
1620          */
1621         first_port = -1;
1622         num_port = 0;
1623         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1624                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1625                     pci_resource_len(dev, i) == 8 &&
1626                     (first_port == -1 || (first_port + num_port) == i)) {
1627                         num_port++;
1628                         if (first_port == -1)
1629                                 first_port = i;
1630                 }
1631         }
1632
1633         if (num_port > 1) {
1634                 board->flags = first_port | FL_BASE_BARS;
1635                 board->num_ports = num_port;
1636                 return 0;
1637         }
1638
1639         return -ENODEV;
1640 }
1641
1642 static inline int
1643 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1644 {
1645         return
1646             board->num_ports == guessed->num_ports &&
1647             board->base_baud == guessed->base_baud &&
1648             board->uart_offset == guessed->uart_offset &&
1649             board->reg_shift == guessed->reg_shift &&
1650             board->first_offset == guessed->first_offset;
1651 }
1652
1653 /*
1654  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1655  * to the arrangement of serial ports on a PCI card.
1656  */
1657 static int __devinit
1658 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1659 {
1660         struct serial_private *priv;
1661         struct pci_board *board, tmp;
1662         struct pci_serial_quirk *quirk;
1663         int rc, nr_ports, i;
1664
1665         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1666                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1667                         ent->driver_data);
1668                 return -EINVAL;
1669         }
1670
1671         board = &pci_boards[ent->driver_data];
1672
1673         rc = pci_enable_device(dev);
1674         if (rc)
1675                 return rc;
1676
1677         if (ent->driver_data == pbn_default) {
1678                 /*
1679                  * Use a copy of the pci_board entry for this;
1680                  * avoid changing entries in the table.
1681                  */
1682                 memcpy(&tmp, board, sizeof(struct pci_board));
1683                 board = &tmp;
1684
1685                 /*
1686                  * We matched one of our class entries.  Try to
1687                  * determine the parameters of this board.
1688                  */
1689                 rc = serial_pci_guess_board(dev, board);
1690                 if (rc)
1691                         goto disable;
1692         } else {
1693                 /*
1694                  * We matched an explicit entry.  If we are able to
1695                  * detect this boards settings with our heuristic,
1696                  * then we no longer need this entry.
1697                  */
1698                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1699                 rc = serial_pci_guess_board(dev, &tmp);
1700                 if (rc == 0 && serial_pci_matches(board, &tmp))
1701                         moan_device("Redundant entry in serial pci_table.",
1702                                     dev);
1703         }
1704
1705         nr_ports = board->num_ports;
1706
1707         /*
1708          * Find an init and setup quirks.
1709          */
1710         quirk = find_quirk(dev);
1711
1712         /*
1713          * Run the new-style initialization function.
1714          * The initialization function returns:
1715          *  <0  - error
1716          *   0  - use board->num_ports
1717          *  >0  - number of ports
1718          */
1719         if (quirk->init) {
1720                 rc = quirk->init(dev);
1721                 if (rc < 0)
1722                         goto disable;
1723                 if (rc)
1724                         nr_ports = rc;
1725         }
1726
1727         priv = kmalloc(sizeof(struct serial_private) +
1728                        sizeof(unsigned int) * nr_ports,
1729                        GFP_KERNEL);
1730         if (!priv) {
1731                 rc = -ENOMEM;
1732                 goto deinit;
1733         }
1734
1735         memset(priv, 0, sizeof(struct serial_private) +
1736                         sizeof(unsigned int) * nr_ports);
1737
1738         priv->quirk = quirk;
1739         pci_set_drvdata(dev, priv);
1740
1741         for (i = 0; i < nr_ports; i++) {
1742                 struct uart_port serial_port;
1743                 memset(&serial_port, 0, sizeof(struct uart_port));
1744
1745                 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF |
1746                                     UPF_SHARE_IRQ;
1747                 serial_port.uartclk = board->base_baud * 16;
1748                 serial_port.irq = get_pci_irq(dev, board, i);
1749                 serial_port.dev = &dev->dev;
1750                 if (quirk->setup(dev, board, &serial_port, i))
1751                         break;
1752 #ifdef SERIAL_DEBUG_PCI
1753                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1754                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1755 #endif
1756
1757                 priv->line[i] = serial8250_register_port(&serial_port);
1758                 if (priv->line[i] < 0) {
1759                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1760                         break;
1761                 }
1762         }
1763
1764         priv->nr = i;
1765
1766         return 0;
1767
1768  deinit:
1769         if (quirk->exit)
1770                 quirk->exit(dev);
1771  disable:
1772         pci_disable_device(dev);
1773         return rc;
1774 }
1775
1776 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1777 {
1778         struct serial_private *priv = pci_get_drvdata(dev);
1779         struct pci_serial_quirk *quirk;
1780         int i;
1781
1782         pci_set_drvdata(dev, NULL);
1783
1784         for (i = 0; i < priv->nr; i++)
1785                 serial8250_unregister_port(priv->line[i]);
1786
1787         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1788                 if (priv->remapped_bar[i])
1789                         iounmap(priv->remapped_bar[i]);
1790                 priv->remapped_bar[i] = NULL;
1791         }
1792
1793         /*
1794          * Find the exit quirks.
1795          */
1796         quirk = find_quirk(dev);
1797         if (quirk->exit)
1798                 quirk->exit(dev);
1799
1800         pci_disable_device(dev);
1801
1802         kfree(priv);
1803 }
1804
1805 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1806 {
1807         struct serial_private *priv = pci_get_drvdata(dev);
1808
1809         if (priv) {
1810                 int i;
1811
1812                 for (i = 0; i < priv->nr; i++)
1813                         serial8250_suspend_port(priv->line[i]);
1814         }
1815         pci_save_state(dev);
1816         pci_set_power_state(dev, pci_choose_state(dev, state));
1817         return 0;
1818 }
1819
1820 static int pciserial_resume_one(struct pci_dev *dev)
1821 {
1822         struct serial_private *priv = pci_get_drvdata(dev);
1823
1824         pci_set_power_state(dev, PCI_D0);
1825         pci_restore_state(dev);
1826
1827         if (priv) {
1828                 int i;
1829
1830                 /*
1831                  * The device may have been disabled.  Re-enable it.
1832                  */
1833                 pci_enable_device(dev);
1834
1835                 /*
1836                  * Ensure that the board is correctly configured.
1837                  */
1838                 if (priv->quirk->init)
1839                         priv->quirk->init(dev);
1840
1841                 for (i = 0; i < priv->nr; i++)
1842                         serial8250_resume_port(priv->line[i]);
1843         }
1844         return 0;
1845 }
1846
1847 static struct pci_device_id serial_pci_tbl[] = {
1848         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1849                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1851                 pbn_b1_8_1382400 },
1852         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1853                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1855                 pbn_b1_4_1382400 },
1856         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1857                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1859                 pbn_b1_2_1382400 },
1860         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1863                 pbn_b1_8_1382400 },
1864         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1867                 pbn_b1_4_1382400 },
1868         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1871                 pbn_b1_2_1382400 },
1872         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1875                 pbn_b1_8_921600 },
1876         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1879                 pbn_b1_8_921600 },
1880         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1883                 pbn_b1_4_921600 },
1884         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1885                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1887                 pbn_b1_4_921600 },
1888         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1889                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1891                 pbn_b1_2_921600 },
1892         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1893                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1894                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1895                 pbn_b1_8_921600 },
1896         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1897                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1899                 pbn_b1_8_921600 },
1900         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1901                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1903                 pbn_b1_4_921600 },
1904
1905         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1906                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1907                 pbn_b2_bt_1_115200 },
1908         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1910                 pbn_b2_bt_2_115200 },
1911         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1913                 pbn_b2_bt_4_115200 },
1914         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1916                 pbn_b2_bt_2_115200 },
1917         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1919                 pbn_b2_bt_4_115200 },
1920         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1922                 pbn_b2_8_115200 },
1923         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925                 pbn_b2_8_115200 },
1926
1927         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1929                 pbn_b2_bt_2_115200 },
1930         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1932                 pbn_b2_bt_2_921600 },
1933         /*
1934          * VScom SPCOM800, from sl@s.pl
1935          */
1936         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1938                 pbn_b2_8_921600 },
1939         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1941                 pbn_b2_4_921600 },
1942         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1943                 PCI_SUBVENDOR_ID_KEYSPAN,
1944                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1945                 pbn_panacom },
1946         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948                 pbn_panacom4 },
1949         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951                 pbn_panacom2 },
1952         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1953                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1954                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1955                 pbn_b2_4_460800 },
1956         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1957                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1958                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1959                 pbn_b2_8_460800 },
1960         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1961                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1962                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1963                 pbn_b2_16_460800 },
1964         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1965                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1966                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1967                 pbn_b2_16_460800 },
1968         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1969                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1970                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1971                 pbn_b2_4_460800 },
1972         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1973                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1974                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1975                 pbn_b2_8_460800 },
1976         /*
1977          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1978          * (Exoray@isys.ca)
1979          */
1980         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1981                 0x10b5, 0x106a, 0, 0,
1982                 pbn_plx_romulus },
1983         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985                 pbn_b1_4_115200 },
1986         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988                 pbn_b1_2_115200 },
1989         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991                 pbn_b1_8_115200 },
1992         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994                 pbn_b1_8_115200 },
1995         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1996                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1997                 pbn_b0_4_921600 },
1998         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1999                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2000                 pbn_b0_4_1152000 },
2001
2002                 /*
2003                  * The below card is a little controversial since it is the
2004                  * subject of a PCI vendor/device ID clash.  (See
2005                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2006                  * For now just used the hex ID 0x950a.
2007                  */
2008         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010                 pbn_b0_2_1130000 },
2011         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013                 pbn_b0_4_115200 },
2014         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016                 pbn_b0_bt_2_921600 },
2017
2018         /*
2019          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2020          * from skokodyn@yahoo.com
2021          */
2022         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2023                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2024                 pbn_sbsxrsio },
2025         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2026                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2027                 pbn_sbsxrsio },
2028         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2029                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2030                 pbn_sbsxrsio },
2031         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2032                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2033                 pbn_sbsxrsio },
2034
2035         /*
2036          * Digitan DS560-558, from jimd@esoft.com
2037          */
2038         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040                 pbn_b1_1_115200 },
2041
2042         /*
2043          * Titan Electronic cards
2044          *  The 400L and 800L have a custom setup quirk.
2045          */
2046         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2048                 pbn_b0_1_921600 },
2049         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2051                 pbn_b0_2_921600 },
2052         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054                 pbn_b0_4_921600 },
2055         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2056                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2057                 pbn_b0_4_921600 },
2058         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2059                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2060                 pbn_b1_1_921600 },
2061         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2062                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2063                 pbn_b1_bt_2_921600 },
2064         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2065                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2066                 pbn_b0_bt_4_921600 },
2067         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2068                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2069                 pbn_b0_bt_8_921600 },
2070
2071         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2072                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073                 pbn_b2_1_460800 },
2074         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2075                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076                 pbn_b2_1_460800 },
2077         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079                 pbn_b2_1_460800 },
2080         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082                 pbn_b2_bt_2_921600 },
2083         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085                 pbn_b2_bt_2_921600 },
2086         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088                 pbn_b2_bt_2_921600 },
2089         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2091                 pbn_b2_bt_4_921600 },
2092         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2093                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2094                 pbn_b2_bt_4_921600 },
2095         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2097                 pbn_b2_bt_4_921600 },
2098         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100                 pbn_b0_1_921600 },
2101         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103                 pbn_b0_1_921600 },
2104         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106                 pbn_b0_1_921600 },
2107         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109                 pbn_b0_bt_2_921600 },
2110         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112                 pbn_b0_bt_2_921600 },
2113         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2115                 pbn_b0_bt_2_921600 },
2116         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2117                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118                 pbn_b0_bt_4_921600 },
2119         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121                 pbn_b0_bt_4_921600 },
2122         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124                 pbn_b0_bt_4_921600 },
2125
2126         /*
2127          * Computone devices submitted by Doug McNash dmcnash@computone.com
2128          */
2129         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2130                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2131                 0, 0, pbn_computone_4 },
2132         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2133                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2134                 0, 0, pbn_computone_8 },
2135         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2136                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2137                 0, 0, pbn_computone_6 },
2138
2139         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_oxsemi },
2142         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2143                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2144                 pbn_b0_bt_1_921600 },
2145
2146         /*
2147          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2148          */
2149         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151                 pbn_b0_bt_8_115200 },
2152         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154                 pbn_b0_bt_8_115200 },
2155
2156         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158                 pbn_b0_bt_2_115200 },
2159         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161                 pbn_b0_bt_2_115200 },
2162         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164                 pbn_b0_bt_2_115200 },
2165         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167                 pbn_b0_bt_4_460800 },
2168         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170                 pbn_b0_bt_4_460800 },
2171         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173                 pbn_b0_bt_2_460800 },
2174         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2176                 pbn_b0_bt_2_460800 },
2177         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2179                 pbn_b0_bt_2_460800 },
2180         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182                 pbn_b0_bt_1_115200 },
2183         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2185                 pbn_b0_bt_1_460800 },
2186
2187         /*
2188          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2189          */
2190         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192                 pbn_b1_1_1382400 },
2193
2194         /*
2195          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2196          */
2197         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2199                 pbn_b1_1_1382400 },
2200
2201         /*
2202          * RAStel 2 port modem, gerg@moreton.com.au
2203          */
2204         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2206                 pbn_b2_bt_2_115200 },
2207
2208         /*
2209          * EKF addition for i960 Boards form EKF with serial port
2210          */
2211         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2212                 0xE4BF, PCI_ANY_ID, 0, 0,
2213                 pbn_intel_i960 },
2214
2215         /*
2216          * Xircom Cardbus/Ethernet combos
2217          */
2218         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220                 pbn_b0_1_115200 },
2221         /*
2222          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2223          */
2224         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2226                 pbn_b0_1_115200 },
2227
2228         /*
2229          * Untested PCI modems, sent in from various folks...
2230          */
2231
2232         /*
2233          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2234          */
2235         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2236                 0x1048, 0x1500, 0, 0,
2237                 pbn_b1_1_115200 },
2238
2239         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2240                 0xFF00, 0, 0, 0,
2241                 pbn_sgi_ioc3 },
2242
2243         /*
2244          * HP Diva card
2245          */
2246         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2247                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2248                 pbn_b1_1_115200 },
2249         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251                 pbn_b0_5_115200 },
2252         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2254                 pbn_b2_1_115200 },
2255
2256         /*
2257          * NEC Vrc-5074 (Nile 4) builtin UART.
2258          */
2259         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2261                 pbn_nec_nile4 },
2262
2263         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2265                 pbn_b3_4_115200 },
2266         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2268                 pbn_b3_8_115200 },
2269
2270         /*
2271          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2272          */
2273         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2274                 PCI_ANY_ID, PCI_ANY_ID,
2275                 0,
2276                 0, pbn_exar_XR17C152 },
2277         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2278                 PCI_ANY_ID, PCI_ANY_ID,
2279                 0,
2280                 0, pbn_exar_XR17C154 },
2281         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2282                 PCI_ANY_ID, PCI_ANY_ID,
2283                 0,
2284                 0, pbn_exar_XR17C158 },
2285
2286         /*
2287          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2288          */
2289         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291                 pbn_b0_1_115200 },
2292
2293         /*
2294          * These entries match devices with class COMMUNICATION_SERIAL,
2295          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2296          */
2297         {       PCI_ANY_ID, PCI_ANY_ID,
2298                 PCI_ANY_ID, PCI_ANY_ID,
2299                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2300                 0xffff00, pbn_default },
2301         {       PCI_ANY_ID, PCI_ANY_ID,
2302                 PCI_ANY_ID, PCI_ANY_ID,
2303                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2304                 0xffff00, pbn_default },
2305         {       PCI_ANY_ID, PCI_ANY_ID,
2306                 PCI_ANY_ID, PCI_ANY_ID,
2307                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2308                 0xffff00, pbn_default },
2309         { 0, }
2310 };
2311
2312 static struct pci_driver serial_pci_driver = {
2313         .name           = "serial",
2314         .probe          = pciserial_init_one,
2315         .remove         = __devexit_p(pciserial_remove_one),
2316         .suspend        = pciserial_suspend_one,
2317         .resume         = pciserial_resume_one,
2318         .id_table       = serial_pci_tbl,
2319 };
2320
2321 static int __init serial8250_pci_init(void)
2322 {
2323         return pci_register_driver(&serial_pci_driver);
2324 }
2325
2326 static void __exit serial8250_pci_exit(void)
2327 {
2328         pci_unregister_driver(&serial_pci_driver);
2329 }
2330
2331 module_init(serial8250_pci_init);
2332 module_exit(serial8250_pci_exit);
2333
2334 MODULE_LICENSE("GPL");
2335 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2336 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);