git.oblomov.eu Git - linux-2.6/blob - drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/tty.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/8250_pci.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/byteorder.h>
  29 #include <asm/io.h>
  30
  31 #include "8250.h"
  32
  33 #undef SERIAL_DEBUG_PCI
  34
  35 /*
  36  * init function returns:
  37  *  > 0 - number of ports
  38  *  = 0 - use board->num_ports
  39  *  < 0 - error
  40  */
  41 struct pci_serial_quirk {
  42         u32     vendor;
  43         u32     device;
  44         u32     subvendor;
  45         u32     subdevice;
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *, struct pciserial_board *,
  48                          struct uart_port *, int);
  49         void    (*exit)(struct pci_dev *dev);
  50 };
  51
  52 #define PCI_NUM_BAR_RESOURCES   6
  53
  54 struct serial_private {
  55         struct pci_dev          *dev;
  56         unsigned int            nr;
  57         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  58         struct pci_serial_quirk *quirk;
  59         int                     line[0];
  60 };
  61
  62 static void moan_device(const char *str, struct pci_dev *dev)
  63 {
  64         printk(KERN_WARNING "%s: %s\n"
  65                KERN_WARNING "Please send the output of lspci -vv, this\n"
  66                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                KERN_WARNING "manufacturer and name of serial board or\n"
  68                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * AFAVLAB uses a different mixture of BARs and offsets
 110  * Not that ugly ;) -- HW
 111  */
 112 static int
 113 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 114               struct uart_port *port, int idx)
 115 {
 116         unsigned int bar, offset = board->first_offset;
 117
 118         bar = FL_GET_BASE(board->flags);
 119         if (idx < 4)
 120                 bar += idx;
 121         else {
 122                 bar = 4;
 123                 offset += (idx - 4) * board->uart_offset;
 124         }
 125
 126         return setup_port(priv, port, bar, offset, board->reg_shift);
 127 }
 128
 129 /*
 130  * HP's Remote Management Console.  The Diva chip came in several
 131  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 132  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 133  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 134  * one Diva chip, but it has been expanded to 5 UARTs.
 135  */
 136 static int pci_hp_diva_init(struct pci_dev *dev)
 137 {
 138         int rc = 0;
 139
 140         switch (dev->subsystem_device) {
 141         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 142         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 143         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 144         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 145                 rc = 3;
 146                 break;
 147         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 148                 rc = 2;
 149                 break;
 150         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 151                 rc = 4;
 152                 break;
 153         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 154         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 155                 rc = 1;
 156                 break;
 157         }
 158
 159         return rc;
 160 }
 161
 162 /*
 163  * HP's Diva chip puts the 4th/5th serial port further out, and
 164  * some serial ports are supposed to be hidden on certain models.
 165  */
 166 static int
 167 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 168               struct uart_port *port, int idx)
 169 {
 170         unsigned int offset = board->first_offset;
 171         unsigned int bar = FL_GET_BASE(board->flags);
 172
 173         switch (priv->dev->subsystem_device) {
 174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                 if (idx == 3)
 176                         idx++;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 179                 if (idx > 0)
 180                         idx++;
 181                 if (idx > 2)
 182                         idx++;
 183                 break;
 184         }
 185         if (idx > 2)
 186                 offset = 0x18;
 187
 188         offset += idx * board->uart_offset;
 189
 190         return setup_port(priv, port, bar, offset, board->reg_shift);
 191 }
 192
 193 /*
 194  * Added for EKF Intel i960 serial boards
 195  */
 196 static int pci_inteli960ni_init(struct pci_dev *dev)
 197 {
 198         unsigned long oldval;
 199
 200         if (!(dev->subsystem_device & 0x1000))
 201                 return -ENODEV;
 202
 203         /* is firmware started? */
 204         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 205         if (oldval == 0x00001000L) { /* RESET value */
 206                 printk(KERN_DEBUG "Local i960 firmware missing");
 207                 return -ENODEV;
 208         }
 209         return 0;
 210 }
 211
 212 /*
 213  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 214  * that the card interrupt be explicitly enabled or disabled.  This
 215  * seems to be mainly needed on card using the PLX which also use I/O
 216  * mapped memory.
 217  */
 218 static int pci_plx9050_init(struct pci_dev *dev)
 219 {
 220         u8 irq_config;
 221         void __iomem *p;
 222
 223         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 224                 moan_device("no memory in bar 0", dev);
 225                 return 0;
 226         }
 227
 228         irq_config = 0x41;
 229         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 230             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 231                 irq_config = 0x43;
 232         }
 233         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 234             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 235                 /*
 236                  * As the megawolf cards have the int pins active
 237                  * high, and have 2 UART chips, both ints must be
 238                  * enabled on the 9050. Also, the UARTS are set in
 239                  * 16450 mode by default, so we have to enable the
 240                  * 16C950 'enhanced' mode so that we can use the
 241                  * deep FIFOs
 242                  */
 243                 irq_config = 0x5b;
 244         }
 245
 246         /*
 247          * enable/disable interrupts
 248          */
 249         p = ioremap(pci_resource_start(dev, 0), 0x80);
 250         if (p == NULL)
 251                 return -ENOMEM;
 252         writel(irq_config, p + 0x4c);
 253
 254         /*
 255          * Read the register back to ensure that it took effect.
 256          */
 257         readl(p + 0x4c);
 258         iounmap(p);
 259
 260         return 0;
 261 }
 262
 263 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 264 {
 265         u8 __iomem *p;
 266
 267         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 268                 return;
 269
 270         /*
 271          * disable interrupts
 272          */
 273         p = ioremap(pci_resource_start(dev, 0), 0x80);
 274         if (p != NULL) {
 275                 writel(0, p + 0x4c);
 276
 277                 /*
 278                  * Read the register back to ensure that it took effect.
 279                  */
 280                 readl(p + 0x4c);
 281                 iounmap(p);
 282         }
 283 }
 284
 285 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 286 static int
 287 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 288                 struct uart_port *port, int idx)
 289 {
 290         unsigned int bar, offset = board->first_offset;
 291
 292         bar = 0;
 293
 294         if (idx < 4) {
 295                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 296                 offset += idx * board->uart_offset;
 297         } else if (idx < 8) {
 298                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 299                 offset += idx * board->uart_offset + 0xC00;
 300         } else /* we have only 8 ports on PMC-OCTALPRO */
 301                 return 1;
 302
 303         return setup_port(priv, port, bar, offset, board->reg_shift);
 304 }
 305
 306 /*
 307 * This does initialization for PMC OCTALPRO cards:
 308 * maps the device memory, resets the UARTs (needed, bc
 309 * if the module is removed and inserted again, the card
 310 * is in the sleep mode) and enables global interrupt.
 311 */
 312
 313 /* global control register offset for SBS PMC-OctalPro */
 314 #define OCT_REG_CR_OFF          0x500
 315
 316 static int sbs_init(struct pci_dev *dev)
 317 {
 318         u8 __iomem *p;
 319
 320         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 321
 322         if (p == NULL)
 323                 return -ENOMEM;
 324         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 325         writeb(0x10,p + OCT_REG_CR_OFF);
 326         udelay(50);
 327         writeb(0x0,p + OCT_REG_CR_OFF);
 328
 329         /* Set bit-2 (INTENABLE) of Control Register */
 330         writeb(0x4, p + OCT_REG_CR_OFF);
 331         iounmap(p);
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * Disables the global interrupt of PMC-OctalPro
 338  */
 339
 340 static void __devexit sbs_exit(struct pci_dev *dev)
 341 {
 342         u8 __iomem *p;
 343
 344         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 345         if (p != NULL) {
 346                 writeb(0, p + OCT_REG_CR_OFF);
 347         }
 348         iounmap(p);
 349 }
 350
 351 /*
 352  * SIIG serial cards have an PCI interface chip which also controls
 353  * the UART clocking frequency. Each UART can be clocked independently
 354  * (except cards equiped with 4 UARTs) and initial clocking settings
 355  * are stored in the EEPROM chip. It can cause problems because this
 356  * version of serial driver doesn't support differently clocked UART's
 357  * on single PCI card. To prevent this, initialization functions set
 358  * high frequency clocking for all UART's on given card. It is safe (I
 359  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 360  * with other OSes (like M$ DOS).
 361  *
 362  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 363  *
 364  * There is two family of SIIG serial cards with different PCI
 365  * interface chip and different configuration methods:
 366  *     - 10x cards have control registers in IO and/or memory space;
 367  *     - 20x cards have control registers in standard PCI configuration space.
 368  *
 369  * Note: all 10x cards have PCI device ids 0x10..
 370  *       all 20x cards have PCI device ids 0x20..
 371  *
 372  * There are also Quartet Serial cards which use Oxford Semiconductor
 373  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 374  *
 375  * Note: some SIIG cards are probed by the parport_serial object.
 376  */
 377
 378 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 379 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 380
 381 static int pci_siig10x_init(struct pci_dev *dev)
 382 {
 383         u16 data;
 384         void __iomem *p;
 385
 386         switch (dev->device & 0xfff8) {
 387         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 388                 data = 0xffdf;
 389                 break;
 390         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 391                 data = 0xf7ff;
 392                 break;
 393         default:                        /* 1S1P, 4S */
 394                 data = 0xfffb;
 395                 break;
 396         }
 397
 398         p = ioremap(pci_resource_start(dev, 0), 0x80);
 399         if (p == NULL)
 400                 return -ENOMEM;
 401
 402         writew(readw(p + 0x28) & data, p + 0x28);
 403         readw(p + 0x28);
 404         iounmap(p);
 405         return 0;
 406 }
 407
 408 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 409 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 410
 411 static int pci_siig20x_init(struct pci_dev *dev)
 412 {
 413         u8 data;
 414
 415         /* Change clock frequency for the first UART. */
 416         pci_read_config_byte(dev, 0x6f, &data);
 417         pci_write_config_byte(dev, 0x6f, data & 0xef);
 418
 419         /* If this card has 2 UART, we have to do the same with second UART. */
 420         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 421             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 422                 pci_read_config_byte(dev, 0x73, &data);
 423                 pci_write_config_byte(dev, 0x73, data & 0xef);
 424         }
 425         return 0;
 426 }
 427
 428 static int pci_siig_init(struct pci_dev *dev)
 429 {
 430         unsigned int type = dev->device & 0xff00;
 431
 432         if (type == 0x1000)
 433                 return pci_siig10x_init(dev);
 434         else if (type == 0x2000)
 435                 return pci_siig20x_init(dev);
 436
 437         moan_device("Unknown SIIG card", dev);
 438         return -ENODEV;
 439 }
 440
 441 static int pci_siig_setup(struct serial_private *priv,
 442                           struct pciserial_board *board,
 443                           struct uart_port *port, int idx)
 444 {
 445         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 446
 447         if (idx > 3) {
 448                 bar = 4;
 449                 offset = (idx - 4) * 8;
 450         }
 451
 452         return setup_port(priv, port, bar, offset, 0);
 453 }
 454
 455 /*
 456  * Timedia has an explosion of boards, and to avoid the PCI table from
 457  * growing *huge*, we use this function to collapse some 70 entries
 458  * in the PCI table into one, for sanity's and compactness's sake.
 459  */
 460 static const unsigned short timedia_single_port[] = {
 461         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 462 };
 463
 464 static const unsigned short timedia_dual_port[] = {
 465         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 466         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 467         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 468         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 469         0xD079, 0
 470 };
 471
 472 static const unsigned short timedia_quad_port[] = {
 473         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 474         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 475         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 476         0xB157, 0
 477 };
 478
 479 static const unsigned short timedia_eight_port[] = {
 480         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 481         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 482 };
 483
 484 static const struct timedia_struct {
 485         int num;
 486         const unsigned short *ids;
 487 } timedia_data[] = {
 488         { 1, timedia_single_port },
 489         { 2, timedia_dual_port },
 490         { 4, timedia_quad_port },
 491         { 8, timedia_eight_port }
 492 };
 493
 494 static int pci_timedia_init(struct pci_dev *dev)
 495 {
 496         const unsigned short *ids;
 497         int i, j;
 498
 499         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 500                 ids = timedia_data[i].ids;
 501                 for (j = 0; ids[j]; j++)
 502                         if (dev->subsystem_device == ids[j])
 503                                 return timedia_data[i].num;
 504         }
 505         return 0;
 506 }
 507
 508 /*
 509  * Timedia/SUNIX uses a mixture of BARs and offsets
 510  * Ugh, this is ugly as all hell --- TYT
 511  */
 512 static int
 513 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 514                   struct uart_port *port, int idx)
 515 {
 516         unsigned int bar = 0, offset = board->first_offset;
 517
 518         switch (idx) {
 519         case 0:
 520                 bar = 0;
 521                 break;
 522         case 1:
 523                 offset = board->uart_offset;
 524                 bar = 0;
 525                 break;
 526         case 2:
 527                 bar = 1;
 528                 break;
 529         case 3:
 530                 offset = board->uart_offset;
 531                 /* FALLTHROUGH */
 532         case 4: /* BAR 2 */
 533         case 5: /* BAR 3 */
 534         case 6: /* BAR 4 */
 535         case 7: /* BAR 5 */
 536                 bar = idx - 2;
 537         }
 538
 539         return setup_port(priv, port, bar, offset, board->reg_shift);
 540 }
 541
 542 /*
 543  * Some Titan cards are also a little weird
 544  */
 545 static int
 546 titan_400l_800l_setup(struct serial_private *priv,
 547                       struct pciserial_board *board,
 548                       struct uart_port *port, int idx)
 549 {
 550         unsigned int bar, offset = board->first_offset;
 551
 552         switch (idx) {
 553         case 0:
 554                 bar = 1;
 555                 break;
 556         case 1:
 557                 bar = 2;
 558                 break;
 559         default:
 560                 bar = 4;
 561                 offset = (idx - 2) * board->uart_offset;
 562         }
 563
 564         return setup_port(priv, port, bar, offset, board->reg_shift);
 565 }
 566
 567 static int pci_xircom_init(struct pci_dev *dev)
 568 {
 569         msleep(100);
 570         return 0;
 571 }
 572
 573 static int pci_netmos_init(struct pci_dev *dev)
 574 {
 575         /* subdevice 0x00PS means <P> parallel, <S> serial */
 576         unsigned int num_serial = dev->subsystem_device & 0xf;
 577
 578         if (num_serial == 0)
 579                 return -ENODEV;
 580         return num_serial;
 581 }
 582
 583 /*
 584  * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
 585  *
 586  * These chips are available with optionally one parallel port and up to
 587  * two serial ports. Unfortunately they all have the same product id.
 588  *
 589  * Basic configuration is done over a region of 32 I/O ports. The base
 590  * ioport is called INTA or INTC, depending on docs/other drivers.
 591  *
 592  * The region of the 32 I/O ports is configured in POSIO0R...
 593  */
 594
 595 /* registers */
 596 #define ITE_887x_MISCR          0x9c
 597 #define ITE_887x_INTCBAR        0x78
 598 #define ITE_887x_UARTBAR        0x7c
 599 #define ITE_887x_PS0BAR         0x10
 600 #define ITE_887x_POSIO0         0x60
 601
 602 /* I/O space size */
 603 #define ITE_887x_IOSIZE         32
 604 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 605 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 606 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 607 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 608 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 609 #define ITE_887x_POSIO_SPEED            (3 << 29)
 610 /* enable IO_Space bit */
 611 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 612
 613 static int pci_ite887x_init(struct pci_dev *dev)
 614 {
 615         /* inta_addr are the configuration addresses of the ITE */
 616         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 617                                                         0x200, 0x280, 0 };
 618         int ret, i, type;
 619         struct resource *iobase = NULL;
 620         u32 miscr, uartbar, ioport;
 621
 622         /* search for the base-ioport */
 623         i = 0;
 624         while (inta_addr[i] && iobase == NULL) {
 625                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 626                                                                 "ite887x");
 627                 if (iobase != NULL) {
 628                         /* write POSIO0R - speed | size | ioport */
 629                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 630                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 631                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 632                         /* write INTCBAR - ioport */
 633                         pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
 634                         ret = inb(inta_addr[i]);
 635                         if (ret != 0xff) {
 636                                 /* ioport connected */
 637                                 break;
 638                         }
 639                         release_region(iobase->start, ITE_887x_IOSIZE);
 640                         iobase = NULL;
 641                 }
 642                 i++;
 643         }
 644
 645         if (!inta_addr[i]) {
 646                 printk(KERN_ERR "ite887x: could not find iobase\n");
 647                 return -ENODEV;
 648         }
 649
 650         /* start of undocumented type checking (see parport_pc.c) */
 651         type = inb(iobase->start + 0x18) & 0x0f;
 652
 653         switch (type) {
 654         case 0x2:       /* ITE8871 (1P) */
 655         case 0xa:       /* ITE8875 (1P) */
 656                 ret = 0;
 657                 break;
 658         case 0xe:       /* ITE8872 (2S1P) */
 659                 ret = 2;
 660                 break;
 661         case 0x6:       /* ITE8873 (1S) */
 662                 ret = 1;
 663                 break;
 664         case 0x8:       /* ITE8874 (2S) */
 665                 ret = 2;
 666                 break;
 667         default:
 668                 moan_device("Unknown ITE887x", dev);
 669                 ret = -ENODEV;
 670         }
 671
 672         /* configure all serial ports */
 673         for (i = 0; i < ret; i++) {
 674                 /* read the I/O port from the device */
 675                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 676                                                                 &ioport);
 677                 ioport &= 0x0000FF00;   /* the actual base address */
 678                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 679                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 680                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 681
 682                 /* write the ioport to the UARTBAR */
 683                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 684                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 685                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 686                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 687
 688                 /* get current config */
 689                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 690                 /* disable interrupts (UARTx_Routing[3:0]) */
 691                 miscr &= ~(0xf << (12 - 4 * i));
 692                 /* activate the UART (UARTx_En) */
 693                 miscr |= 1 << (23 - i);
 694                 /* write new config with activated UART */
 695                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 696         }
 697
 698         if (ret <= 0) {
 699                 /* the device has no UARTs if we get here */
 700                 release_region(iobase->start, ITE_887x_IOSIZE);
 701         }
 702
 703         return ret;
 704 }
 705
 706 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 707 {
 708         u32 ioport;
 709         /* the ioport is bit 0-15 in POSIO0R */
 710         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 711         ioport &= 0xffff;
 712         release_region(ioport, ITE_887x_IOSIZE);
 713 }
 714
 715 static int
 716 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 717                   struct uart_port *port, int idx)
 718 {
 719         unsigned int bar, offset = board->first_offset, maxnr;
 720
 721         bar = FL_GET_BASE(board->flags);
 722         if (board->flags & FL_BASE_BARS)
 723                 bar += idx;
 724         else
 725                 offset += idx * board->uart_offset;
 726
 727         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 728                 (board->reg_shift + 3);
 729
 730         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 731                 return 1;
 732
 733         return setup_port(priv, port, bar, offset, board->reg_shift);
 734 }
 735
 736 /* This should be in linux/pci_ids.h */
 737 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 738 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 739 #define PCI_DEVICE_ID_OCTPRO            0x0001
 740 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 741 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 742 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 743 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 744
 745 /*
 746  * Master list of serial port init/setup/exit quirks.
 747  * This does not describe the general nature of the port.
 748  * (ie, baud base, number and location of ports, etc)
 749  *
 750  * This list is ordered alphabetically by vendor then device.
 751  * Specific entries must come before more generic entries.
 752  */
 753 static struct pci_serial_quirk pci_serial_quirks[] = {
 754         /*
 755          * AFAVLAB cards - these may be called via parport_serial
 756          *  It is not clear whether this applies to all products.
 757          */
 758         {
 759                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 760                 .device         = PCI_ANY_ID,
 761                 .subvendor      = PCI_ANY_ID,
 762                 .subdevice      = PCI_ANY_ID,
 763                 .setup          = afavlab_setup,
 764         },
 765         /*
 766          * HP Diva
 767          */
 768         {
 769                 .vendor         = PCI_VENDOR_ID_HP,
 770                 .device         = PCI_DEVICE_ID_HP_DIVA,
 771                 .subvendor      = PCI_ANY_ID,
 772                 .subdevice      = PCI_ANY_ID,
 773                 .init           = pci_hp_diva_init,
 774                 .setup          = pci_hp_diva_setup,
 775         },
 776         /*
 777          * Intel
 778          */
 779         {
 780                 .vendor         = PCI_VENDOR_ID_INTEL,
 781                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 782                 .subvendor      = 0xe4bf,
 783                 .subdevice      = PCI_ANY_ID,
 784                 .init           = pci_inteli960ni_init,
 785                 .setup          = pci_default_setup,
 786         },
 787         /*
 788          * ITE
 789          */
 790         {
 791                 .vendor         = PCI_VENDOR_ID_ITE,
 792                 .device         = PCI_DEVICE_ID_ITE_8872,
 793                 .subvendor      = PCI_ANY_ID,
 794                 .subdevice      = PCI_ANY_ID,
 795                 .init           = pci_ite887x_init,
 796                 .setup          = pci_default_setup,
 797                 .exit           = __devexit_p(pci_ite887x_exit),
 798         },
 799         /*
 800          * Panacom
 801          */
 802         {
 803                 .vendor         = PCI_VENDOR_ID_PANACOM,
 804                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 805                 .subvendor      = PCI_ANY_ID,
 806                 .subdevice      = PCI_ANY_ID,
 807                 .init           = pci_plx9050_init,
 808                 .setup          = pci_default_setup,
 809                 .exit           = __devexit_p(pci_plx9050_exit),
 810         },
 811         {
 812                 .vendor         = PCI_VENDOR_ID_PANACOM,
 813                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 814                 .subvendor      = PCI_ANY_ID,
 815                 .subdevice      = PCI_ANY_ID,
 816                 .init           = pci_plx9050_init,
 817                 .setup          = pci_default_setup,
 818                 .exit           = __devexit_p(pci_plx9050_exit),
 819         },
 820         /*
 821          * PLX
 822          */
 823         {
 824                 .vendor         = PCI_VENDOR_ID_PLX,
 825                 .device         = PCI_DEVICE_ID_PLX_9030,
 826                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 827                 .subdevice      = PCI_ANY_ID,
 828                 .setup          = pci_default_setup,
 829         },
 830         {
 831                 .vendor         = PCI_VENDOR_ID_PLX,
 832                 .device         = PCI_DEVICE_ID_PLX_9050,
 833                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 834                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 835                 .init           = pci_plx9050_init,
 836                 .setup          = pci_default_setup,
 837                 .exit           = __devexit_p(pci_plx9050_exit),
 838         },
 839         {
 840                 .vendor         = PCI_VENDOR_ID_PLX,
 841                 .device         = PCI_DEVICE_ID_PLX_9050,
 842                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 843                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 844                 .init           = pci_plx9050_init,
 845                 .setup          = pci_default_setup,
 846                 .exit           = __devexit_p(pci_plx9050_exit),
 847         },
 848         {
 849                 .vendor         = PCI_VENDOR_ID_PLX,
 850                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 851                 .subvendor      = PCI_VENDOR_ID_PLX,
 852                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 853                 .init           = pci_plx9050_init,
 854                 .setup          = pci_default_setup,
 855                 .exit           = __devexit_p(pci_plx9050_exit),
 856         },
 857         /*
 858          * SBS Technologies, Inc., PMC-OCTALPRO 232
 859          */
 860         {
 861                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 862                 .device         = PCI_DEVICE_ID_OCTPRO,
 863                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 864                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 865                 .init           = sbs_init,
 866                 .setup          = sbs_setup,
 867                 .exit           = __devexit_p(sbs_exit),
 868         },
 869         /*
 870          * SBS Technologies, Inc., PMC-OCTALPRO 422
 871          */
 872         {
 873                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 874                 .device         = PCI_DEVICE_ID_OCTPRO,
 875                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 876                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 877                 .init           = sbs_init,
 878                 .setup          = sbs_setup,
 879                 .exit           = __devexit_p(sbs_exit),
 880         },
 881         /*
 882          * SBS Technologies, Inc., P-Octal 232
 883          */
 884         {
 885                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 886                 .device         = PCI_DEVICE_ID_OCTPRO,
 887                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 888                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 889                 .init           = sbs_init,
 890                 .setup          = sbs_setup,
 891                 .exit           = __devexit_p(sbs_exit),
 892         },
 893         /*
 894          * SBS Technologies, Inc., P-Octal 422
 895          */
 896         {
 897                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 898                 .device         = PCI_DEVICE_ID_OCTPRO,
 899                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 900                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 901                 .init           = sbs_init,
 902                 .setup          = sbs_setup,
 903                 .exit           = __devexit_p(sbs_exit),
 904         },
 905         /*
 906          * SIIG cards - these may be called via parport_serial
 907          */
 908         {
 909                 .vendor         = PCI_VENDOR_ID_SIIG,
 910                 .device         = PCI_ANY_ID,
 911                 .subvendor      = PCI_ANY_ID,
 912                 .subdevice      = PCI_ANY_ID,
 913                 .init           = pci_siig_init,
 914                 .setup          = pci_siig_setup,
 915         },
 916         /*
 917          * Titan cards
 918          */
 919         {
 920                 .vendor         = PCI_VENDOR_ID_TITAN,
 921                 .device         = PCI_DEVICE_ID_TITAN_400L,
 922                 .subvendor      = PCI_ANY_ID,
 923                 .subdevice      = PCI_ANY_ID,
 924                 .setup          = titan_400l_800l_setup,
 925         },
 926         {
 927                 .vendor         = PCI_VENDOR_ID_TITAN,
 928                 .device         = PCI_DEVICE_ID_TITAN_800L,
 929                 .subvendor      = PCI_ANY_ID,
 930                 .subdevice      = PCI_ANY_ID,
 931                 .setup          = titan_400l_800l_setup,
 932         },
 933         /*
 934          * Timedia cards
 935          */
 936         {
 937                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 938                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 939                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 940                 .subdevice      = PCI_ANY_ID,
 941                 .init           = pci_timedia_init,
 942                 .setup          = pci_timedia_setup,
 943         },
 944         {
 945                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 946                 .device         = PCI_ANY_ID,
 947                 .subvendor      = PCI_ANY_ID,
 948                 .subdevice      = PCI_ANY_ID,
 949                 .setup          = pci_timedia_setup,
 950         },
 951         /*
 952          * Xircom cards
 953          */
 954         {
 955                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 956                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 957                 .subvendor      = PCI_ANY_ID,
 958                 .subdevice      = PCI_ANY_ID,
 959                 .init           = pci_xircom_init,
 960                 .setup          = pci_default_setup,
 961         },
 962         /*
 963          * Netmos cards - these may be called via parport_serial
 964          */
 965         {
 966                 .vendor         = PCI_VENDOR_ID_NETMOS,
 967                 .device         = PCI_ANY_ID,
 968                 .subvendor      = PCI_ANY_ID,
 969                 .subdevice      = PCI_ANY_ID,
 970                 .init           = pci_netmos_init,
 971                 .setup          = pci_default_setup,
 972         },
 973         /*
 974          * Default "match everything" terminator entry
 975          */
 976         {
 977                 .vendor         = PCI_ANY_ID,
 978                 .device         = PCI_ANY_ID,
 979                 .subvendor      = PCI_ANY_ID,
 980                 .subdevice      = PCI_ANY_ID,
 981                 .setup          = pci_default_setup,
 982         }
 983 };
 984
 985 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 986 {
 987         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 988 }
 989
 990 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 991 {
 992         struct pci_serial_quirk *quirk;
 993
 994         for (quirk = pci_serial_quirks; ; quirk++)
 995                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 996                     quirk_id_matches(quirk->device, dev->device) &&
 997                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 998                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 999                         break;
1000         return quirk;
1001 }
1002
1003 static inline int get_pci_irq(struct pci_dev *dev,
1004                                 struct pciserial_board *board)
1005 {
1006         if (board->flags & FL_NOIRQ)
1007                 return 0;
1008         else
1009                 return dev->irq;
1010 }
1011
1012 /*
1013  * This is the configuration table for all of the PCI serial boards
1014  * which we support.  It is directly indexed by the pci_board_num_t enum
1015  * value, which is encoded in the pci_device_id PCI probe table's
1016  * driver_data member.
1017  *
1018  * The makeup of these names are:
1019  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1020  *
1021  *  bn          = PCI BAR number
1022  *  bt          = Index using PCI BARs
1023  *  n           = number of serial ports
1024  *  baud        = baud rate
1025  *  offsetinhex = offset for each sequential port (in hex)
1026  *
1027  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1028  *
1029  * Please note: in theory if n = 1, _bt infix should make no difference.
1030  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1031  */
1032 enum pci_board_num_t {
1033         pbn_default = 0,
1034
1035         pbn_b0_1_115200,
1036         pbn_b0_2_115200,
1037         pbn_b0_4_115200,
1038         pbn_b0_5_115200,
1039
1040         pbn_b0_1_921600,
1041         pbn_b0_2_921600,
1042         pbn_b0_4_921600,
1043
1044         pbn_b0_2_1130000,
1045
1046         pbn_b0_4_1152000,
1047
1048         pbn_b0_2_1843200,
1049         pbn_b0_4_1843200,
1050
1051         pbn_b0_2_1843200_200,
1052         pbn_b0_4_1843200_200,
1053         pbn_b0_8_1843200_200,
1054
1055         pbn_b0_bt_1_115200,
1056         pbn_b0_bt_2_115200,
1057         pbn_b0_bt_8_115200,
1058
1059         pbn_b0_bt_1_460800,
1060         pbn_b0_bt_2_460800,
1061         pbn_b0_bt_4_460800,
1062
1063         pbn_b0_bt_1_921600,
1064         pbn_b0_bt_2_921600,
1065         pbn_b0_bt_4_921600,
1066         pbn_b0_bt_8_921600,
1067
1068         pbn_b1_1_115200,
1069         pbn_b1_2_115200,
1070         pbn_b1_4_115200,
1071         pbn_b1_8_115200,
1072
1073         pbn_b1_1_921600,
1074         pbn_b1_2_921600,
1075         pbn_b1_4_921600,
1076         pbn_b1_8_921600,
1077
1078         pbn_b1_2_1250000,
1079
1080         pbn_b1_bt_1_115200,
1081         pbn_b1_bt_2_921600,
1082
1083         pbn_b1_1_1382400,
1084         pbn_b1_2_1382400,
1085         pbn_b1_4_1382400,
1086         pbn_b1_8_1382400,
1087
1088         pbn_b2_1_115200,
1089         pbn_b2_2_115200,
1090         pbn_b2_4_115200,
1091         pbn_b2_8_115200,
1092
1093         pbn_b2_1_460800,
1094         pbn_b2_4_460800,
1095         pbn_b2_8_460800,
1096         pbn_b2_16_460800,
1097
1098         pbn_b2_1_921600,
1099         pbn_b2_4_921600,
1100         pbn_b2_8_921600,
1101
1102         pbn_b2_bt_1_115200,
1103         pbn_b2_bt_2_115200,
1104         pbn_b2_bt_4_115200,
1105
1106         pbn_b2_bt_2_921600,
1107         pbn_b2_bt_4_921600,
1108
1109         pbn_b3_2_115200,
1110         pbn_b3_4_115200,
1111         pbn_b3_8_115200,
1112
1113         /*
1114          * Board-specific versions.
1115          */
1116         pbn_panacom,
1117         pbn_panacom2,
1118         pbn_panacom4,
1119         pbn_exsys_4055,
1120         pbn_plx_romulus,
1121         pbn_oxsemi,
1122         pbn_intel_i960,
1123         pbn_sgi_ioc3,
1124         pbn_computone_4,
1125         pbn_computone_6,
1126         pbn_computone_8,
1127         pbn_sbsxrsio,
1128         pbn_exar_XR17C152,
1129         pbn_exar_XR17C154,
1130         pbn_exar_XR17C158,
1131         pbn_pasemi_1682M,
1132 };
1133
1134 /*
1135  * uart_offset - the space between channels
1136  * reg_shift   - describes how the UART registers are mapped
1137  *               to PCI memory by the card.
1138  * For example IER register on SBS, Inc. PMC-OctPro is located at
1139  * offset 0x10 from the UART base, while UART_IER is defined as 1
1140  * in include/linux/serial_reg.h,
1141  * see first lines of serial_in() and serial_out() in 8250.c
1142 */
1143
1144 static struct pciserial_board pci_boards[] __devinitdata = {
1145         [pbn_default] = {
1146                 .flags          = FL_BASE0,
1147                 .num_ports      = 1,
1148                 .base_baud      = 115200,
1149                 .uart_offset    = 8,
1150         },
1151         [pbn_b0_1_115200] = {
1152                 .flags          = FL_BASE0,
1153                 .num_ports      = 1,
1154                 .base_baud      = 115200,
1155                 .uart_offset    = 8,
1156         },
1157         [pbn_b0_2_115200] = {
1158                 .flags          = FL_BASE0,
1159                 .num_ports      = 2,
1160                 .base_baud      = 115200,
1161                 .uart_offset    = 8,
1162         },
1163         [pbn_b0_4_115200] = {
1164                 .flags          = FL_BASE0,
1165                 .num_ports      = 4,
1166                 .base_baud      = 115200,
1167                 .uart_offset    = 8,
1168         },
1169         [pbn_b0_5_115200] = {
1170                 .flags          = FL_BASE0,
1171                 .num_ports      = 5,
1172                 .base_baud      = 115200,
1173                 .uart_offset    = 8,
1174         },
1175
1176         [pbn_b0_1_921600] = {
1177                 .flags          = FL_BASE0,
1178                 .num_ports      = 1,
1179                 .base_baud      = 921600,
1180                 .uart_offset    = 8,
1181         },
1182         [pbn_b0_2_921600] = {
1183                 .flags          = FL_BASE0,
1184                 .num_ports      = 2,
1185                 .base_baud      = 921600,
1186                 .uart_offset    = 8,
1187         },
1188         [pbn_b0_4_921600] = {
1189                 .flags          = FL_BASE0,
1190                 .num_ports      = 4,
1191                 .base_baud      = 921600,
1192                 .uart_offset    = 8,
1193         },
1194
1195         [pbn_b0_2_1130000] = {
1196                 .flags          = FL_BASE0,
1197                 .num_ports      = 2,
1198                 .base_baud      = 1130000,
1199                 .uart_offset    = 8,
1200         },
1201
1202         [pbn_b0_4_1152000] = {
1203                 .flags          = FL_BASE0,
1204                 .num_ports      = 4,
1205                 .base_baud      = 1152000,
1206                 .uart_offset    = 8,
1207         },
1208
1209         [pbn_b0_2_1843200] = {
1210                 .flags          = FL_BASE0,
1211                 .num_ports      = 2,
1212                 .base_baud      = 1843200,
1213                 .uart_offset    = 8,
1214         },
1215         [pbn_b0_4_1843200] = {
1216                 .flags          = FL_BASE0,
1217                 .num_ports      = 4,
1218                 .base_baud      = 1843200,
1219                 .uart_offset    = 8,
1220         },
1221
1222         [pbn_b0_2_1843200_200] = {
1223                 .flags          = FL_BASE0,
1224                 .num_ports      = 2,
1225                 .base_baud      = 1843200,
1226                 .uart_offset    = 0x200,
1227         },
1228         [pbn_b0_4_1843200_200] = {
1229                 .flags          = FL_BASE0,
1230                 .num_ports      = 4,
1231                 .base_baud      = 1843200,
1232                 .uart_offset    = 0x200,
1233         },
1234         [pbn_b0_8_1843200_200] = {
1235                 .flags          = FL_BASE0,
1236                 .num_ports      = 8,
1237                 .base_baud      = 1843200,
1238                 .uart_offset    = 0x200,
1239         },
1240
1241         [pbn_b0_bt_1_115200] = {
1242                 .flags          = FL_BASE0|FL_BASE_BARS,
1243                 .num_ports      = 1,
1244                 .base_baud      = 115200,
1245                 .uart_offset    = 8,
1246         },
1247         [pbn_b0_bt_2_115200] = {
1248                 .flags          = FL_BASE0|FL_BASE_BARS,
1249                 .num_ports      = 2,
1250                 .base_baud      = 115200,
1251                 .uart_offset    = 8,
1252         },
1253         [pbn_b0_bt_8_115200] = {
1254                 .flags          = FL_BASE0|FL_BASE_BARS,
1255                 .num_ports      = 8,
1256                 .base_baud      = 115200,
1257                 .uart_offset    = 8,
1258         },
1259
1260         [pbn_b0_bt_1_460800] = {
1261                 .flags          = FL_BASE0|FL_BASE_BARS,
1262                 .num_ports      = 1,
1263                 .base_baud      = 460800,
1264                 .uart_offset    = 8,
1265         },
1266         [pbn_b0_bt_2_460800] = {
1267                 .flags          = FL_BASE0|FL_BASE_BARS,
1268                 .num_ports      = 2,
1269                 .base_baud      = 460800,
1270                 .uart_offset    = 8,
1271         },
1272         [pbn_b0_bt_4_460800] = {
1273                 .flags          = FL_BASE0|FL_BASE_BARS,
1274                 .num_ports      = 4,
1275                 .base_baud      = 460800,
1276                 .uart_offset    = 8,
1277         },
1278
1279         [pbn_b0_bt_1_921600] = {
1280                 .flags          = FL_BASE0|FL_BASE_BARS,
1281                 .num_ports      = 1,
1282                 .base_baud      = 921600,
1283                 .uart_offset    = 8,
1284         },
1285         [pbn_b0_bt_2_921600] = {
1286                 .flags          = FL_BASE0|FL_BASE_BARS,
1287                 .num_ports      = 2,
1288                 .base_baud      = 921600,
1289                 .uart_offset    = 8,
1290         },
1291         [pbn_b0_bt_4_921600] = {
1292                 .flags          = FL_BASE0|FL_BASE_BARS,
1293                 .num_ports      = 4,
1294                 .base_baud      = 921600,
1295                 .uart_offset    = 8,
1296         },
1297         [pbn_b0_bt_8_921600] = {
1298                 .flags          = FL_BASE0|FL_BASE_BARS,
1299                 .num_ports      = 8,
1300                 .base_baud      = 921600,
1301                 .uart_offset    = 8,
1302         },
1303
1304         [pbn_b1_1_115200] = {
1305                 .flags          = FL_BASE1,
1306                 .num_ports      = 1,
1307                 .base_baud      = 115200,
1308                 .uart_offset    = 8,
1309         },
1310         [pbn_b1_2_115200] = {
1311                 .flags          = FL_BASE1,
1312                 .num_ports      = 2,
1313                 .base_baud      = 115200,
1314                 .uart_offset    = 8,
1315         },
1316         [pbn_b1_4_115200] = {
1317                 .flags          = FL_BASE1,
1318                 .num_ports      = 4,
1319                 .base_baud      = 115200,
1320                 .uart_offset    = 8,
1321         },
1322         [pbn_b1_8_115200] = {
1323                 .flags          = FL_BASE1,
1324                 .num_ports      = 8,
1325                 .base_baud      = 115200,
1326                 .uart_offset    = 8,
1327         },
1328
1329         [pbn_b1_1_921600] = {
1330                 .flags          = FL_BASE1,
1331                 .num_ports      = 1,
1332                 .base_baud      = 921600,
1333                 .uart_offset    = 8,
1334         },
1335         [pbn_b1_2_921600] = {
1336                 .flags          = FL_BASE1,
1337                 .num_ports      = 2,
1338                 .base_baud      = 921600,
1339                 .uart_offset    = 8,
1340         },
1341         [pbn_b1_4_921600] = {
1342                 .flags          = FL_BASE1,
1343                 .num_ports      = 4,
1344                 .base_baud      = 921600,
1345                 .uart_offset    = 8,
1346         },
1347         [pbn_b1_8_921600] = {
1348                 .flags          = FL_BASE1,
1349                 .num_ports      = 8,
1350                 .base_baud      = 921600,
1351                 .uart_offset    = 8,
1352         },
1353         [pbn_b1_2_1250000] = {
1354                 .flags          = FL_BASE1,
1355                 .num_ports      = 2,
1356                 .base_baud      = 1250000,
1357                 .uart_offset    = 8,
1358         },
1359
1360         [pbn_b1_bt_1_115200] = {
1361                 .flags          = FL_BASE1|FL_BASE_BARS,
1362                 .num_ports      = 1,
1363                 .base_baud      = 115200,
1364                 .uart_offset    = 8,
1365         },
1366
1367         [pbn_b1_bt_2_921600] = {
1368                 .flags          = FL_BASE1|FL_BASE_BARS,
1369                 .num_ports      = 2,
1370                 .base_baud      = 921600,
1371                 .uart_offset    = 8,
1372         },
1373
1374         [pbn_b1_1_1382400] = {
1375                 .flags          = FL_BASE1,
1376                 .num_ports      = 1,
1377                 .base_baud      = 1382400,
1378                 .uart_offset    = 8,
1379         },
1380         [pbn_b1_2_1382400] = {
1381                 .flags          = FL_BASE1,
1382                 .num_ports      = 2,
1383                 .base_baud      = 1382400,
1384                 .uart_offset    = 8,
1385         },
1386         [pbn_b1_4_1382400] = {
1387                 .flags          = FL_BASE1,
1388                 .num_ports      = 4,
1389                 .base_baud      = 1382400,
1390                 .uart_offset    = 8,
1391         },
1392         [pbn_b1_8_1382400] = {
1393                 .flags          = FL_BASE1,
1394                 .num_ports      = 8,
1395                 .base_baud      = 1382400,
1396                 .uart_offset    = 8,
1397         },
1398
1399         [pbn_b2_1_115200] = {
1400                 .flags          = FL_BASE2,
1401                 .num_ports      = 1,
1402                 .base_baud      = 115200,
1403                 .uart_offset    = 8,
1404         },
1405         [pbn_b2_2_115200] = {
1406                 .flags          = FL_BASE2,
1407                 .num_ports      = 2,
1408                 .base_baud      = 115200,
1409                 .uart_offset    = 8,
1410         },
1411         [pbn_b2_4_115200] = {
1412                 .flags          = FL_BASE2,
1413                 .num_ports      = 4,
1414                 .base_baud      = 115200,
1415                 .uart_offset    = 8,
1416         },
1417         [pbn_b2_8_115200] = {
1418                 .flags          = FL_BASE2,
1419                 .num_ports      = 8,
1420                 .base_baud      = 115200,
1421                 .uart_offset    = 8,
1422         },
1423
1424         [pbn_b2_1_460800] = {
1425                 .flags          = FL_BASE2,
1426                 .num_ports      = 1,
1427                 .base_baud      = 460800,
1428                 .uart_offset    = 8,
1429         },
1430         [pbn_b2_4_460800] = {
1431                 .flags          = FL_BASE2,
1432                 .num_ports      = 4,
1433                 .base_baud      = 460800,
1434                 .uart_offset    = 8,
1435         },
1436         [pbn_b2_8_460800] = {
1437                 .flags          = FL_BASE2,
1438                 .num_ports      = 8,
1439                 .base_baud      = 460800,
1440                 .uart_offset    = 8,
1441         },
1442         [pbn_b2_16_460800] = {
1443                 .flags          = FL_BASE2,
1444                 .num_ports      = 16,
1445                 .base_baud      = 460800,
1446                 .uart_offset    = 8,
1447          },
1448
1449         [pbn_b2_1_921600] = {
1450                 .flags          = FL_BASE2,
1451                 .num_ports      = 1,
1452                 .base_baud      = 921600,
1453                 .uart_offset    = 8,
1454         },
1455         [pbn_b2_4_921600] = {
1456                 .flags          = FL_BASE2,
1457                 .num_ports      = 4,
1458                 .base_baud      = 921600,
1459                 .uart_offset    = 8,
1460         },
1461         [pbn_b2_8_921600] = {
1462                 .flags          = FL_BASE2,
1463                 .num_ports      = 8,
1464                 .base_baud      = 921600,
1465                 .uart_offset    = 8,
1466         },
1467
1468         [pbn_b2_bt_1_115200] = {
1469                 .flags          = FL_BASE2|FL_BASE_BARS,
1470                 .num_ports      = 1,
1471                 .base_baud      = 115200,
1472                 .uart_offset    = 8,
1473         },
1474         [pbn_b2_bt_2_115200] = {
1475                 .flags          = FL_BASE2|FL_BASE_BARS,
1476                 .num_ports      = 2,
1477                 .base_baud      = 115200,
1478                 .uart_offset    = 8,
1479         },
1480         [pbn_b2_bt_4_115200] = {
1481                 .flags          = FL_BASE2|FL_BASE_BARS,
1482                 .num_ports      = 4,
1483                 .base_baud      = 115200,
1484                 .uart_offset    = 8,
1485         },
1486
1487         [pbn_b2_bt_2_921600] = {
1488                 .flags          = FL_BASE2|FL_BASE_BARS,
1489                 .num_ports      = 2,
1490                 .base_baud      = 921600,
1491                 .uart_offset    = 8,
1492         },
1493         [pbn_b2_bt_4_921600] = {
1494                 .flags          = FL_BASE2|FL_BASE_BARS,
1495                 .num_ports      = 4,
1496                 .base_baud      = 921600,
1497                 .uart_offset    = 8,
1498         },
1499
1500         [pbn_b3_2_115200] = {
1501                 .flags          = FL_BASE3,
1502                 .num_ports      = 2,
1503                 .base_baud      = 115200,
1504                 .uart_offset    = 8,
1505         },
1506         [pbn_b3_4_115200] = {
1507                 .flags          = FL_BASE3,
1508                 .num_ports      = 4,
1509                 .base_baud      = 115200,
1510                 .uart_offset    = 8,
1511         },
1512         [pbn_b3_8_115200] = {
1513                 .flags          = FL_BASE3,
1514                 .num_ports      = 8,
1515                 .base_baud      = 115200,
1516                 .uart_offset    = 8,
1517         },
1518
1519         /*
1520          * Entries following this are board-specific.
1521          */
1522
1523         /*
1524          * Panacom - IOMEM
1525          */
1526         [pbn_panacom] = {
1527                 .flags          = FL_BASE2,
1528                 .num_ports      = 2,
1529                 .base_baud      = 921600,
1530                 .uart_offset    = 0x400,
1531                 .reg_shift      = 7,
1532         },
1533         [pbn_panacom2] = {
1534                 .flags          = FL_BASE2|FL_BASE_BARS,
1535                 .num_ports      = 2,
1536                 .base_baud      = 921600,
1537                 .uart_offset    = 0x400,
1538                 .reg_shift      = 7,
1539         },
1540         [pbn_panacom4] = {
1541                 .flags          = FL_BASE2|FL_BASE_BARS,
1542                 .num_ports      = 4,
1543                 .base_baud      = 921600,
1544                 .uart_offset    = 0x400,
1545                 .reg_shift      = 7,
1546         },
1547
1548         [pbn_exsys_4055] = {
1549                 .flags          = FL_BASE2,
1550                 .num_ports      = 4,
1551                 .base_baud      = 115200,
1552                 .uart_offset    = 8,
1553         },
1554
1555         /* I think this entry is broken - the first_offset looks wrong --rmk */
1556         [pbn_plx_romulus] = {
1557                 .flags          = FL_BASE2,
1558                 .num_ports      = 4,
1559                 .base_baud      = 921600,
1560                 .uart_offset    = 8 << 2,
1561                 .reg_shift      = 2,
1562                 .first_offset   = 0x03,
1563         },
1564
1565         /*
1566          * This board uses the size of PCI Base region 0 to
1567          * signal now many ports are available
1568          */
1569         [pbn_oxsemi] = {
1570                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1571                 .num_ports      = 32,
1572                 .base_baud      = 115200,
1573                 .uart_offset    = 8,
1574         },
1575
1576         /*
1577          * EKF addition for i960 Boards form EKF with serial port.
1578          * Max 256 ports.
1579          */
1580         [pbn_intel_i960] = {
1581                 .flags          = FL_BASE0,
1582                 .num_ports      = 32,
1583                 .base_baud      = 921600,
1584                 .uart_offset    = 8 << 2,
1585                 .reg_shift      = 2,
1586                 .first_offset   = 0x10000,
1587         },
1588         [pbn_sgi_ioc3] = {
1589                 .flags          = FL_BASE0|FL_NOIRQ,
1590                 .num_ports      = 1,
1591                 .base_baud      = 458333,
1592                 .uart_offset    = 8,
1593                 .reg_shift      = 0,
1594                 .first_offset   = 0x20178,
1595         },
1596
1597         /*
1598          * Computone - uses IOMEM.
1599          */
1600         [pbn_computone_4] = {
1601                 .flags          = FL_BASE0,
1602                 .num_ports      = 4,
1603                 .base_baud      = 921600,
1604                 .uart_offset    = 0x40,
1605                 .reg_shift      = 2,
1606                 .first_offset   = 0x200,
1607         },
1608         [pbn_computone_6] = {
1609                 .flags          = FL_BASE0,
1610                 .num_ports      = 6,
1611                 .base_baud      = 921600,
1612                 .uart_offset    = 0x40,
1613                 .reg_shift      = 2,
1614                 .first_offset   = 0x200,
1615         },
1616         [pbn_computone_8] = {
1617                 .flags          = FL_BASE0,
1618                 .num_ports      = 8,
1619                 .base_baud      = 921600,
1620                 .uart_offset    = 0x40,
1621                 .reg_shift      = 2,
1622                 .first_offset   = 0x200,
1623         },
1624         [pbn_sbsxrsio] = {
1625                 .flags          = FL_BASE0,
1626                 .num_ports      = 8,
1627                 .base_baud      = 460800,
1628                 .uart_offset    = 256,
1629                 .reg_shift      = 4,
1630         },
1631         /*
1632          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1633          *  Only basic 16550A support.
1634          *  XR17C15[24] are not tested, but they should work.
1635          */
1636         [pbn_exar_XR17C152] = {
1637                 .flags          = FL_BASE0,
1638                 .num_ports      = 2,
1639                 .base_baud      = 921600,
1640                 .uart_offset    = 0x200,
1641         },
1642         [pbn_exar_XR17C154] = {
1643                 .flags          = FL_BASE0,
1644                 .num_ports      = 4,
1645                 .base_baud      = 921600,
1646                 .uart_offset    = 0x200,
1647         },
1648         [pbn_exar_XR17C158] = {
1649                 .flags          = FL_BASE0,
1650                 .num_ports      = 8,
1651                 .base_baud      = 921600,
1652                 .uart_offset    = 0x200,
1653         },
1654         /*
1655          * PA Semi PWRficient PA6T-1682M on-chip UART
1656          */
1657         [pbn_pasemi_1682M] = {
1658                 .flags          = FL_BASE0,
1659                 .num_ports      = 1,
1660                 .base_baud      = 8333333,
1661         },
1662 };
1663
1664 static const struct pci_device_id softmodem_blacklist[] = {
1665         { PCI_VDEVICE ( AL, 0x5457 ), }, /* ALi Corporation M5457 AC'97 Modem */
1666 };
1667
1668 /*
1669  * Given a complete unknown PCI device, try to use some heuristics to
1670  * guess what the configuration might be, based on the pitiful PCI
1671  * serial specs.  Returns 0 on success, 1 on failure.
1672  */
1673 static int __devinit
1674 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1675 {
1676         const struct pci_device_id *blacklist;
1677         int num_iomem, num_port, first_port = -1, i;
1678
1679         /*
1680          * If it is not a communications device or the programming
1681          * interface is greater than 6, give up.
1682          *
1683          * (Should we try to make guesses for multiport serial devices
1684          * later?)
1685          */
1686         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1687              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1688             (dev->class & 0xff) > 6)
1689                 return -ENODEV;
1690
1691         /*
1692          * Do not access blacklisted devices that are known not to
1693          * feature serial ports.
1694          */
1695         for (blacklist = softmodem_blacklist;
1696              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1697              blacklist++) {
1698                 if (dev->vendor == blacklist->vendor &&
1699                     dev->device == blacklist->device)
1700                         return -ENODEV;
1701         }
1702
1703         num_iomem = num_port = 0;
1704         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1705                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1706                         num_port++;
1707                         if (first_port == -1)
1708                                 first_port = i;
1709                 }
1710                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1711                         num_iomem++;
1712         }
1713
1714         /*
1715          * If there is 1 or 0 iomem regions, and exactly one port,
1716          * use it.  We guess the number of ports based on the IO
1717          * region size.
1718          */
1719         if (num_iomem <= 1 && num_port == 1) {
1720                 board->flags = first_port;
1721                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1722                 return 0;
1723         }
1724
1725         /*
1726          * Now guess if we've got a board which indexes by BARs.
1727          * Each IO BAR should be 8 bytes, and they should follow
1728          * consecutively.
1729          */
1730         first_port = -1;
1731         num_port = 0;
1732         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1733                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1734                     pci_resource_len(dev, i) == 8 &&
1735                     (first_port == -1 || (first_port + num_port) == i)) {
1736                         num_port++;
1737                         if (first_port == -1)
1738                                 first_port = i;
1739                 }
1740         }
1741
1742         if (num_port > 1) {
1743                 board->flags = first_port | FL_BASE_BARS;
1744                 board->num_ports = num_port;
1745                 return 0;
1746         }
1747
1748         return -ENODEV;
1749 }
1750
1751 static inline int
1752 serial_pci_matches(struct pciserial_board *board,
1753                    struct pciserial_board *guessed)
1754 {
1755         return
1756             board->num_ports == guessed->num_ports &&
1757             board->base_baud == guessed->base_baud &&
1758             board->uart_offset == guessed->uart_offset &&
1759             board->reg_shift == guessed->reg_shift &&
1760             board->first_offset == guessed->first_offset;
1761 }
1762
1763 struct serial_private *
1764 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1765 {
1766         struct uart_port serial_port;
1767         struct serial_private *priv;
1768         struct pci_serial_quirk *quirk;
1769         int rc, nr_ports, i;
1770
1771         nr_ports = board->num_ports;
1772
1773         /*
1774          * Find an init and setup quirks.
1775          */
1776         quirk = find_quirk(dev);
1777
1778         /*
1779          * Run the new-style initialization function.
1780          * The initialization function returns:
1781          *  <0  - error
1782          *   0  - use board->num_ports
1783          *  >0  - number of ports
1784          */
1785         if (quirk->init) {
1786                 rc = quirk->init(dev);
1787                 if (rc < 0) {
1788                         priv = ERR_PTR(rc);
1789                         goto err_out;
1790                 }
1791                 if (rc)
1792                         nr_ports = rc;
1793         }
1794
1795         priv = kzalloc(sizeof(struct serial_private) +
1796                        sizeof(unsigned int) * nr_ports,
1797                        GFP_KERNEL);
1798         if (!priv) {
1799                 priv = ERR_PTR(-ENOMEM);
1800                 goto err_deinit;
1801         }
1802
1803         priv->dev = dev;
1804         priv->quirk = quirk;
1805
1806         memset(&serial_port, 0, sizeof(struct uart_port));
1807         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1808         serial_port.uartclk = board->base_baud * 16;
1809         serial_port.irq = get_pci_irq(dev, board);
1810         serial_port.dev = &dev->dev;
1811
1812         for (i = 0; i < nr_ports; i++) {
1813                 if (quirk->setup(priv, board, &serial_port, i))
1814                         break;
1815
1816 #ifdef SERIAL_DEBUG_PCI
1817                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1818                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1819 #endif
1820
1821                 priv->line[i] = serial8250_register_port(&serial_port);
1822                 if (priv->line[i] < 0) {
1823                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1824                         break;
1825                 }
1826         }
1827
1828         priv->nr = i;
1829
1830         return priv;
1831
1832  err_deinit:
1833         if (quirk->exit)
1834                 quirk->exit(dev);
1835  err_out:
1836         return priv;
1837 }
1838 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1839
1840 void pciserial_remove_ports(struct serial_private *priv)
1841 {
1842         struct pci_serial_quirk *quirk;
1843         int i;
1844
1845         for (i = 0; i < priv->nr; i++)
1846                 serial8250_unregister_port(priv->line[i]);
1847
1848         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1849                 if (priv->remapped_bar[i])
1850                         iounmap(priv->remapped_bar[i]);
1851                 priv->remapped_bar[i] = NULL;
1852         }
1853
1854         /*
1855          * Find the exit quirks.
1856          */
1857         quirk = find_quirk(priv->dev);
1858         if (quirk->exit)
1859                 quirk->exit(priv->dev);
1860
1861         kfree(priv);
1862 }
1863 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1864
1865 void pciserial_suspend_ports(struct serial_private *priv)
1866 {
1867         int i;
1868
1869         for (i = 0; i < priv->nr; i++)
1870                 if (priv->line[i] >= 0)
1871                         serial8250_suspend_port(priv->line[i]);
1872 }
1873 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1874
1875 void pciserial_resume_ports(struct serial_private *priv)
1876 {
1877         int i;
1878
1879         /*
1880          * Ensure that the board is correctly configured.
1881          */
1882         if (priv->quirk->init)
1883                 priv->quirk->init(priv->dev);
1884
1885         for (i = 0; i < priv->nr; i++)
1886                 if (priv->line[i] >= 0)
1887                         serial8250_resume_port(priv->line[i]);
1888 }
1889 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1890
1891 /*
1892  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1893  * to the arrangement of serial ports on a PCI card.
1894  */
1895 static int __devinit
1896 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1897 {
1898         struct serial_private *priv;
1899         struct pciserial_board *board, tmp;
1900         int rc;
1901
1902         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1903                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1904                         ent->driver_data);
1905                 return -EINVAL;
1906         }
1907
1908         board = &pci_boards[ent->driver_data];
1909
1910         rc = pci_enable_device(dev);
1911         if (rc)
1912                 return rc;
1913
1914         if (ent->driver_data == pbn_default) {
1915                 /*
1916                  * Use a copy of the pci_board entry for this;
1917                  * avoid changing entries in the table.
1918                  */
1919                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1920                 board = &tmp;
1921
1922                 /*
1923                  * We matched one of our class entries.  Try to
1924                  * determine the parameters of this board.
1925                  */
1926                 rc = serial_pci_guess_board(dev, board);
1927                 if (rc)
1928                         goto disable;
1929         } else {
1930                 /*
1931                  * We matched an explicit entry.  If we are able to
1932                  * detect this boards settings with our heuristic,
1933                  * then we no longer need this entry.
1934                  */
1935                 memcpy(&tmp, &pci_boards[pbn_default],
1936                        sizeof(struct pciserial_board));
1937                 rc = serial_pci_guess_board(dev, &tmp);
1938                 if (rc == 0 && serial_pci_matches(board, &tmp))
1939                         moan_device("Redundant entry in serial pci_table.",
1940                                     dev);
1941         }
1942
1943         priv = pciserial_init_ports(dev, board);
1944         if (!IS_ERR(priv)) {
1945                 pci_set_drvdata(dev, priv);
1946                 return 0;
1947         }
1948
1949         rc = PTR_ERR(priv);
1950
1951  disable:
1952         pci_disable_device(dev);
1953         return rc;
1954 }
1955
1956 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1957 {
1958         struct serial_private *priv = pci_get_drvdata(dev);
1959
1960         pci_set_drvdata(dev, NULL);
1961
1962         pciserial_remove_ports(priv);
1963
1964         pci_disable_device(dev);
1965 }
1966
1967 #ifdef CONFIG_PM
1968 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1969 {
1970         struct serial_private *priv = pci_get_drvdata(dev);
1971
1972         if (priv)
1973                 pciserial_suspend_ports(priv);
1974
1975         pci_save_state(dev);
1976         pci_set_power_state(dev, pci_choose_state(dev, state));
1977         return 0;
1978 }
1979
1980 static int pciserial_resume_one(struct pci_dev *dev)
1981 {
1982         struct serial_private *priv = pci_get_drvdata(dev);
1983
1984         pci_set_power_state(dev, PCI_D0);
1985         pci_restore_state(dev);
1986
1987         if (priv) {
1988                 /*
1989                  * The device may have been disabled.  Re-enable it.
1990                  */
1991                 pci_enable_device(dev);
1992
1993                 pciserial_resume_ports(priv);
1994         }
1995         return 0;
1996 }
1997 #endif
1998
1999 static struct pci_device_id serial_pci_tbl[] = {
2000         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2001                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2002                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2003                 pbn_b1_8_1382400 },
2004         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2005                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2006                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2007                 pbn_b1_4_1382400 },
2008         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2009                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2010                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2011                 pbn_b1_2_1382400 },
2012         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2013                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2014                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2015                 pbn_b1_8_1382400 },
2016         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2017                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2018                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2019                 pbn_b1_4_1382400 },
2020         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2021                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2022                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2023                 pbn_b1_2_1382400 },
2024         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2025                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2026                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2027                 pbn_b1_8_921600 },
2028         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2029                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2030                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2031                 pbn_b1_8_921600 },
2032         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2033                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2034                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2035                 pbn_b1_4_921600 },
2036         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2037                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2038                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2039                 pbn_b1_4_921600 },
2040         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2041                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2042                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2043                 pbn_b1_2_921600 },
2044         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2045                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2046                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2047                 pbn_b1_8_921600 },
2048         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2049                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2050                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2051                 pbn_b1_8_921600 },
2052         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2054                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2055                 pbn_b1_4_921600 },
2056         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2058                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2059                 pbn_b1_2_1250000 },
2060         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2062                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2063                 pbn_b0_2_1843200 },
2064         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2066                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2067                 pbn_b0_4_1843200 },
2068         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2069                 PCI_VENDOR_ID_AFAVLAB,
2070                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2071                 pbn_b0_4_1152000 },
2072         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2073                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2074                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2075                 pbn_b0_2_1843200_200 },
2076         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2077                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2078                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2079                 pbn_b0_4_1843200_200 },
2080         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2081                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2082                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2083                 pbn_b0_8_1843200_200 },
2084         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2085                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2086                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2087                 pbn_b0_2_1843200_200 },
2088         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2089                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2090                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2091                 pbn_b0_4_1843200_200 },
2092         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2093                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2094                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2095                 pbn_b0_8_1843200_200 },
2096         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2097                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2098                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2099                 pbn_b0_2_1843200_200 },
2100         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2101                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2102                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2103                 pbn_b0_4_1843200_200 },
2104         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2105                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2106                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2107                 pbn_b0_8_1843200_200 },
2108         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2109                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2110                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2111                 pbn_b0_2_1843200_200 },
2112         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2113                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2114                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2115                 pbn_b0_4_1843200_200 },
2116         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2117                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2118                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2119                 pbn_b0_8_1843200_200 },
2120
2121         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123                 pbn_b2_bt_1_115200 },
2124         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126                 pbn_b2_bt_2_115200 },
2127         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129                 pbn_b2_bt_4_115200 },
2130         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132                 pbn_b2_bt_2_115200 },
2133         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2135                 pbn_b2_bt_4_115200 },
2136         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138                 pbn_b2_8_115200 },
2139         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_b2_8_115200 },
2142
2143         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145                 pbn_b2_bt_2_115200 },
2146         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148                 pbn_b2_bt_2_921600 },
2149         /*
2150          * VScom SPCOM800, from sl@s.pl
2151          */
2152         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154                 pbn_b2_8_921600 },
2155         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157                 pbn_b2_4_921600 },
2158         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2159                 PCI_SUBVENDOR_ID_KEYSPAN,
2160                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2161                 pbn_panacom },
2162         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164                 pbn_panacom4 },
2165         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167                 pbn_panacom2 },
2168         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2169                 PCI_VENDOR_ID_ESDGMBH,
2170                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2171                 pbn_b2_4_115200 },
2172         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2173                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2174                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2175                 pbn_b2_4_460800 },
2176         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2177                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2178                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2179                 pbn_b2_8_460800 },
2180         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2181                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2182                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2183                 pbn_b2_16_460800 },
2184         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2185                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2186                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2187                 pbn_b2_16_460800 },
2188         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2189                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2190                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2191                 pbn_b2_4_460800 },
2192         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2193                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2194                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2195                 pbn_b2_8_460800 },
2196         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2197                 PCI_SUBVENDOR_ID_EXSYS,
2198                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2199                 pbn_exsys_4055 },
2200         /*
2201          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2202          * (Exoray@isys.ca)
2203          */
2204         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2205                 0x10b5, 0x106a, 0, 0,
2206                 pbn_plx_romulus },
2207         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209                 pbn_b1_4_115200 },
2210         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2212                 pbn_b1_2_115200 },
2213         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2215                 pbn_b1_8_115200 },
2216         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2218                 pbn_b1_8_115200 },
2219         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2220                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2221                 pbn_b0_4_921600 },
2222         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2223                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2224                 pbn_b0_4_1152000 },
2225
2226                 /*
2227                  * The below card is a little controversial since it is the
2228                  * subject of a PCI vendor/device ID clash.  (See
2229                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2230                  * For now just used the hex ID 0x950a.
2231                  */
2232         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234                 pbn_b0_2_1130000 },
2235         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2236                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237                 pbn_b0_4_115200 },
2238         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2240                 pbn_b0_bt_2_921600 },
2241
2242         /*
2243          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2244          * from skokodyn@yahoo.com
2245          */
2246         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2247                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2248                 pbn_sbsxrsio },
2249         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2250                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2251                 pbn_sbsxrsio },
2252         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2253                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2254                 pbn_sbsxrsio },
2255         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2256                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2257                 pbn_sbsxrsio },
2258
2259         /*
2260          * Digitan DS560-558, from jimd@esoft.com
2261          */
2262         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2264                 pbn_b1_1_115200 },
2265
2266         /*
2267          * Titan Electronic cards
2268          *  The 400L and 800L have a custom setup quirk.
2269          */
2270         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2272                 pbn_b0_1_921600 },
2273         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2275                 pbn_b0_2_921600 },
2276         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2278                 pbn_b0_4_921600 },
2279         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2281                 pbn_b0_4_921600 },
2282         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284                 pbn_b1_1_921600 },
2285         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2287                 pbn_b1_bt_2_921600 },
2288         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2290                 pbn_b0_bt_4_921600 },
2291         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2293                 pbn_b0_bt_8_921600 },
2294
2295         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2297                 pbn_b2_1_460800 },
2298         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2300                 pbn_b2_1_460800 },
2301         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2303                 pbn_b2_1_460800 },
2304         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2306                 pbn_b2_bt_2_921600 },
2307         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2309                 pbn_b2_bt_2_921600 },
2310         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2312                 pbn_b2_bt_2_921600 },
2313         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2315                 pbn_b2_bt_4_921600 },
2316         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2318                 pbn_b2_bt_4_921600 },
2319         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2321                 pbn_b2_bt_4_921600 },
2322         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2324                 pbn_b0_1_921600 },
2325         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2327                 pbn_b0_1_921600 },
2328         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2330                 pbn_b0_1_921600 },
2331         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333                 pbn_b0_bt_2_921600 },
2334         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336                 pbn_b0_bt_2_921600 },
2337         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339                 pbn_b0_bt_2_921600 },
2340         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2342                 pbn_b0_bt_4_921600 },
2343         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345                 pbn_b0_bt_4_921600 },
2346         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2348                 pbn_b0_bt_4_921600 },
2349         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2351                 pbn_b0_bt_8_921600 },
2352         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2354                 pbn_b0_bt_8_921600 },
2355         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2357                 pbn_b0_bt_8_921600 },
2358
2359         /*
2360          * Computone devices submitted by Doug McNash dmcnash@computone.com
2361          */
2362         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2363                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2364                 0, 0, pbn_computone_4 },
2365         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2366                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2367                 0, 0, pbn_computone_8 },
2368         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2369                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2370                 0, 0, pbn_computone_6 },
2371
2372         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2373                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2374                 pbn_oxsemi },
2375         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2376                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2377                 pbn_b0_bt_1_921600 },
2378
2379         /*
2380          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2381          */
2382         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2384                 pbn_b0_bt_8_115200 },
2385         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2387                 pbn_b0_bt_8_115200 },
2388
2389         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391                 pbn_b0_bt_2_115200 },
2392         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394                 pbn_b0_bt_2_115200 },
2395         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397                 pbn_b0_bt_2_115200 },
2398         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2400                 pbn_b0_bt_4_460800 },
2401         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2403                 pbn_b0_bt_4_460800 },
2404         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2406                 pbn_b0_bt_2_460800 },
2407         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2409                 pbn_b0_bt_2_460800 },
2410         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2412                 pbn_b0_bt_2_460800 },
2413         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2415                 pbn_b0_bt_1_115200 },
2416         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2418                 pbn_b0_bt_1_460800 },
2419
2420         /*
2421          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2422          * Cards are identified by their subsystem vendor IDs, which
2423          * (in hex) match the model number.
2424          *
2425          * Note that JC140x are RS422/485 cards which require ox950
2426          * ACR = 0x10, and as such are not currently fully supported.
2427          */
2428         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2429                 0x1204, 0x0004, 0, 0,
2430                 pbn_b0_4_921600 },
2431         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2432                 0x1208, 0x0004, 0, 0,
2433                 pbn_b0_4_921600 },
2434 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2435                 0x1402, 0x0002, 0, 0,
2436                 pbn_b0_2_921600 }, */
2437 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2438                 0x1404, 0x0004, 0, 0,
2439                 pbn_b0_4_921600 }, */
2440         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2441                 0x1208, 0x0004, 0, 0,
2442                 pbn_b0_4_921600 },
2443
2444         /*
2445          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2446          */
2447         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2449                 pbn_b1_1_1382400 },
2450
2451         /*
2452          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2453          */
2454         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2456                 pbn_b1_1_1382400 },
2457
2458         /*
2459          * RAStel 2 port modem, gerg@moreton.com.au
2460          */
2461         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2463                 pbn_b2_bt_2_115200 },
2464
2465         /*
2466          * EKF addition for i960 Boards form EKF with serial port
2467          */
2468         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2469                 0xE4BF, PCI_ANY_ID, 0, 0,
2470                 pbn_intel_i960 },
2471
2472         /*
2473          * Xircom Cardbus/Ethernet combos
2474          */
2475         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2477                 pbn_b0_1_115200 },
2478         /*
2479          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2480          */
2481         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2483                 pbn_b0_1_115200 },
2484
2485         /*
2486          * Untested PCI modems, sent in from various folks...
2487          */
2488
2489         /*
2490          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2491          */
2492         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2493                 0x1048, 0x1500, 0, 0,
2494                 pbn_b1_1_115200 },
2495
2496         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2497                 0xFF00, 0, 0, 0,
2498                 pbn_sgi_ioc3 },
2499
2500         /*
2501          * HP Diva card
2502          */
2503         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2504                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2505                 pbn_b1_1_115200 },
2506         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508                 pbn_b0_5_115200 },
2509         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2511                 pbn_b2_1_115200 },
2512
2513         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2515                 pbn_b3_2_115200 },
2516         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2517                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2518                 pbn_b3_4_115200 },
2519         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2521                 pbn_b3_8_115200 },
2522
2523         /*
2524          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2525          */
2526         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2527                 PCI_ANY_ID, PCI_ANY_ID,
2528                 0,
2529                 0, pbn_exar_XR17C152 },
2530         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2531                 PCI_ANY_ID, PCI_ANY_ID,
2532                 0,
2533                 0, pbn_exar_XR17C154 },
2534         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2535                 PCI_ANY_ID, PCI_ANY_ID,
2536                 0,
2537                 0, pbn_exar_XR17C158 },
2538
2539         /*
2540          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2541          */
2542         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2544                 pbn_b0_1_115200 },
2545         /*
2546          * ITE
2547          */
2548         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2549                 PCI_ANY_ID, PCI_ANY_ID,
2550                 0, 0,
2551                 pbn_b1_bt_1_115200 },
2552
2553         /*
2554          * IntaShield IS-200
2555          */
2556         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2558                 pbn_b2_2_115200 },
2559
2560         /*
2561          * Perle PCI-RAS cards
2562          */
2563         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2564                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2565                 0, 0, pbn_b2_4_921600 },
2566         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2567                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2568                 0, 0, pbn_b2_8_921600 },
2569         /*
2570          * PA Semi PA6T-1682M on-chip UART
2571          */
2572         {       PCI_VENDOR_ID_PASEMI, 0xa004,
2573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2574                 pbn_pasemi_1682M },
2575
2576         /*
2577          * These entries match devices with class COMMUNICATION_SERIAL,
2578          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2579          */
2580         {       PCI_ANY_ID, PCI_ANY_ID,
2581                 PCI_ANY_ID, PCI_ANY_ID,
2582                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2583                 0xffff00, pbn_default },
2584         {       PCI_ANY_ID, PCI_ANY_ID,
2585                 PCI_ANY_ID, PCI_ANY_ID,
2586                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2587                 0xffff00, pbn_default },
2588         {       PCI_ANY_ID, PCI_ANY_ID,
2589                 PCI_ANY_ID, PCI_ANY_ID,
2590                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2591                 0xffff00, pbn_default },
2592         { 0, }
2593 };
2594
2595 static struct pci_driver serial_pci_driver = {
2596         .name           = "serial",
2597         .probe          = pciserial_init_one,
2598         .remove         = __devexit_p(pciserial_remove_one),
2599 #ifdef CONFIG_PM
2600         .suspend        = pciserial_suspend_one,
2601         .resume         = pciserial_resume_one,
2602 #endif
2603         .id_table       = serial_pci_tbl,
2604 };
2605
2606 static int __init serial8250_pci_init(void)
2607 {
2608         return pci_register_driver(&serial_pci_driver);
2609 }
2610
2611 static void __exit serial8250_pci_exit(void)
2612 {
2613         pci_unregister_driver(&serial_pci_driver);
2614 }
2615
2616 module_init(serial8250_pci_init);
2617 module_exit(serial8250_pci_exit);
2618
2619 MODULE_LICENSE("GPL");
2620 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2621 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);