2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
28 /* Scan and identify a NAND device */
29 extern int nand_scan (struct mtd_info *mtd, int max_chips);
30 /* Free resources held by the NAND device */
31 extern void nand_release (struct mtd_info *mtd);
33 /* The maximum number of NAND chips in an array */
34 #define NAND_MAX_CHIPS 8
36 /* This constant declares the max. oobsize / page, which
37 * is supported now. If you add a chip with bigger oobsize/page
38 * adjust this accordingly.
40 #define NAND_MAX_OOBSIZE 64
41 #define NAND_MAX_PAGESIZE 2048
44 * Constants for hardware specific CLE/ALE/NCE function
46 * These are bits which can be or'ed to set/clear multiple
49 /* Select the chip by setting nCE to low */
51 /* Select the command latch by setting CLE to high */
53 /* Select the address latch by setting ALE to high */
56 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
57 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
58 #define NAND_CTRL_CHANGE 0x80
61 * Standard NAND flash commands
63 #define NAND_CMD_READ0 0
64 #define NAND_CMD_READ1 1
65 #define NAND_CMD_RNDOUT 5
66 #define NAND_CMD_PAGEPROG 0x10
67 #define NAND_CMD_READOOB 0x50
68 #define NAND_CMD_ERASE1 0x60
69 #define NAND_CMD_STATUS 0x70
70 #define NAND_CMD_STATUS_MULTI 0x71
71 #define NAND_CMD_SEQIN 0x80
72 #define NAND_CMD_RNDIN 0x85
73 #define NAND_CMD_READID 0x90
74 #define NAND_CMD_ERASE2 0xd0
75 #define NAND_CMD_RESET 0xff
77 /* Extended commands for large page devices */
78 #define NAND_CMD_READSTART 0x30
79 #define NAND_CMD_RNDOUTSTART 0xE0
80 #define NAND_CMD_CACHEDPROG 0x15
82 /* Extended commands for AG-AND device */
84 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
85 * there is no way to distinguish that from NAND_CMD_READ0
86 * until the remaining sequence of commands has been completed
87 * so add a high order bit and mask it off in the command.
89 #define NAND_CMD_DEPLETE1 0x100
90 #define NAND_CMD_DEPLETE2 0x38
91 #define NAND_CMD_STATUS_MULTI 0x71
92 #define NAND_CMD_STATUS_ERROR 0x72
93 /* multi-bank error status (banks 0-3) */
94 #define NAND_CMD_STATUS_ERROR0 0x73
95 #define NAND_CMD_STATUS_ERROR1 0x74
96 #define NAND_CMD_STATUS_ERROR2 0x75
97 #define NAND_CMD_STATUS_ERROR3 0x76
98 #define NAND_CMD_STATUS_RESET 0x7f
99 #define NAND_CMD_STATUS_CLEAR 0xff
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME,
121 * Constants for Hardware ECC
123 /* Reset Hardware ECC for read */
124 #define NAND_ECC_READ 0
125 /* Reset Hardware ECC for write */
126 #define NAND_ECC_WRITE 1
127 /* Enable Hardware ECC before syndrom is read back from flash */
128 #define NAND_ECC_READSYN 2
130 /* Bit mask for flags passed to do_nand_read_ecc */
131 #define NAND_GET_DEVICE 0x80
134 /* Option constants for bizarre disfunctionality and real
137 /* Chip can not auto increment pages */
138 #define NAND_NO_AUTOINCR 0x00000001
139 /* Buswitdh is 16 bit */
140 #define NAND_BUSWIDTH_16 0x00000002
141 /* Device supports partial programming without padding */
142 #define NAND_NO_PADDING 0x00000004
143 /* Chip has cache program function */
144 #define NAND_CACHEPRG 0x00000008
145 /* Chip has copy back function */
146 #define NAND_COPYBACK 0x00000010
147 /* AND Chip which has 4 banks and a confusing page / block
148 * assignment. See Renesas datasheet for further information */
149 #define NAND_IS_AND 0x00000020
150 /* Chip has a array of 4 pages which can be read without
151 * additional ready /busy waits */
152 #define NAND_4PAGE_ARRAY 0x00000040
153 /* Chip requires that BBT is periodically rewritten to prevent
154 * bits from adjacent blocks from 'leaking' in altering data.
155 * This happens with the Renesas AG-AND chips, possibly others. */
156 #define BBT_AUTO_REFRESH 0x00000080
157 /* Chip does not require ready check on read. True
158 * for all large page devices, as they do not support
160 #define NAND_NO_READRDY 0x00000100
162 /* Options valid for Samsung large page devices */
163 #define NAND_SAMSUNG_LP_OPTIONS \
164 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
166 /* Macros to identify the above */
167 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
168 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
169 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
170 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
172 /* Mask to zero out the chip options, which come from the id table */
173 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
175 /* Non chip related options */
176 /* Use a flash based bad block table. This option is passed to the
177 * default bad block table function. */
178 #define NAND_USE_FLASH_BBT 0x00010000
179 /* This option skips the bbt scan during initialization. */
180 #define NAND_SKIP_BBTSCAN 0x00020000
182 /* Options set by nand scan */
183 /* Nand scan has allocated controller struct */
184 #define NAND_CONTROLLER_ALLOC 0x80000000
188 * nand_state_t - chip states
189 * Enumeration for NAND flash chip state
205 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
206 * @lock: protection lock
207 * @active: the mtd device which holds the controller currently
208 * @wq: wait queue to sleep on if a NAND operation is in progress
209 * used instead of the per chip wait queue when a hw controller is available
211 struct nand_hw_control {
213 struct nand_chip *active;
214 wait_queue_head_t wq;
218 * struct nand_ecc_ctrl - Control structure for ecc
220 * @steps: number of ecc steps per page
221 * @size: data bytes per ecc step
222 * @bytes: ecc bytes per step
223 * @total: total number of ecc bytes per page
224 * @prepad: padding information for syndrome based ecc generators
225 * @postpad: padding information for syndrome based ecc generators
226 * @hwctl: function to control hardware ecc generator. Must only
227 * be provided if an hardware ECC is available
228 * @calculate: function for ecc calculation or readback from ecc hardware
229 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
230 * @read_page: function to read a page according to the ecc generator requirements
231 * @write_page: function to write a page according to the ecc generator requirements
233 struct nand_ecc_ctrl {
234 nand_ecc_modes_t mode;
241 struct nand_ecclayout *layout;
242 void (*hwctl)(struct mtd_info *mtd, int mode);
243 int (*calculate)(struct mtd_info *mtd,
246 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
249 int (*read_page)(struct mtd_info *mtd,
250 struct nand_chip *chip,
252 void (*write_page)(struct mtd_info *mtd,
253 struct nand_chip *chip,
255 int (*read_oob)(struct mtd_info *mtd,
256 struct nand_chip *chip,
259 int (*write_oob)(struct mtd_info *mtd,
260 struct nand_chip *chip,
265 * struct nand_buffers - buffer structure for read/write
266 * @ecccalc: buffer for calculated ecc
267 * @ecccode: buffer for ecc read from flash
268 * @oobwbuf: buffer for write oob data
269 * @databuf: buffer for data - dynamically sized
270 * @oobrbuf: buffer to read oob data
272 * Do not change the order of buffers. databuf and oobrbuf must be in
275 struct nand_buffers {
276 uint8_t ecccalc[NAND_MAX_OOBSIZE];
277 uint8_t ecccode[NAND_MAX_OOBSIZE];
278 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
279 uint8_t databuf[NAND_MAX_PAGESIZE];
280 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
284 * struct nand_chip - NAND Private Flash Chip Data
285 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
286 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
287 * @read_byte: [REPLACEABLE] read one byte from the chip
288 * @read_word: [REPLACEABLE] read one word from the chip
289 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
290 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
291 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
292 * @select_chip: [REPLACEABLE] select chip nr
293 * @block_bad: [REPLACEABLE] check, if the block is bad
294 * @block_markbad: [REPLACEABLE] mark the block bad
295 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
296 * ALE/CLE/nCE. Also used to write command and address
297 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
298 * If set to NULL no access to ready/busy is available and the ready/busy information
299 * is read from the chip status register
300 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
301 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
302 * @ecc: [BOARDSPECIFIC] ecc control ctructure
303 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
304 * @scan_bbt: [REPLACEABLE] function to scan bad block table
305 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
306 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
307 * @state: [INTERN] the current state of the NAND device
308 * @page_shift: [INTERN] number of address bits in a page (column address bits)
309 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
310 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
311 * @chip_shift: [INTERN] number of address bits in one chip
312 * @datbuf: [INTERN] internal buffer for one page + oob
313 * @oobbuf: [INTERN] oob buffer for one eraseblock
314 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
315 * @data_poi: [INTERN] pointer to a data buffer
316 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
317 * special functionality. See the defines for further explanation
318 * @badblockpos: [INTERN] position of the bad block marker in the oob area
319 * @numchips: [INTERN] number of physical chips
320 * @chipsize: [INTERN] the size of one chip for multichip arrays
321 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
322 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
323 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
324 * @bbt: [INTERN] bad block table pointer
325 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
326 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
327 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
328 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
329 * which is shared among multiple independend devices
330 * @priv: [OPTIONAL] pointer to private chip date
331 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
332 * (determine if errors are correctable)
336 void __iomem *IO_ADDR_R;
337 void __iomem *IO_ADDR_W;
339 uint8_t (*read_byte)(struct mtd_info *mtd);
340 u16 (*read_word)(struct mtd_info *mtd);
341 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
342 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
343 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
344 void (*select_chip)(struct mtd_info *mtd, int chip);
345 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
346 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
347 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
349 int (*dev_ready)(struct mtd_info *mtd);
350 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
351 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
352 void (*erase_cmd)(struct mtd_info *mtd, int page);
353 int (*scan_bbt)(struct mtd_info *mtd);
354 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
357 unsigned int options;
360 int phys_erase_shift;
364 unsigned long chipsize;
372 struct nand_hw_control *controller;
373 struct nand_ecclayout *ecclayout;
375 struct nand_ecc_ctrl ecc;
376 struct nand_buffers buffers;
377 struct nand_hw_control hwcontrol;
379 struct mtd_oob_ops ops;
382 struct nand_bbt_descr *bbt_td;
383 struct nand_bbt_descr *bbt_md;
385 struct nand_bbt_descr *badblock_pattern;
391 * NAND Flash Manufacturer ID Codes
393 #define NAND_MFR_TOSHIBA 0x98
394 #define NAND_MFR_SAMSUNG 0xec
395 #define NAND_MFR_FUJITSU 0x04
396 #define NAND_MFR_NATIONAL 0x8f
397 #define NAND_MFR_RENESAS 0x07
398 #define NAND_MFR_STMICRO 0x20
399 #define NAND_MFR_HYNIX 0xad
402 * struct nand_flash_dev - NAND Flash Device ID Structure
404 * @name: Identify the device type
405 * @id: device ID code
406 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
407 * If the pagesize is 0, then the real pagesize
408 * and the eraseize are determined from the
409 * extended id bytes in the chip
410 * @erasesize: Size of an erase block in the flash device.
411 * @chipsize: Total chipsize in Mega Bytes
412 * @options: Bitfield to store chip relevant options
414 struct nand_flash_dev {
417 unsigned long pagesize;
418 unsigned long chipsize;
419 unsigned long erasesize;
420 unsigned long options;
424 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
425 * @name: Manufacturer name
426 * @id: manufacturer ID code of device.
428 struct nand_manufacturers {
433 extern struct nand_flash_dev nand_flash_ids[];
434 extern struct nand_manufacturers nand_manuf_ids[];
437 * struct nand_bbt_descr - bad block table descriptor
438 * @options: options for this descriptor
439 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
440 * when bbt is searched, then we store the found bbts pages here.
441 * Its an array and supports up to 8 chips now
442 * @offs: offset of the pattern in the oob area of the page
443 * @veroffs: offset of the bbt version counter in the oob are of the page
444 * @version: version read from the bbt page during scan
445 * @len: length of the pattern, if 0 no pattern check is performed
446 * @maxblocks: maximum number of blocks to search for a bbt. This number of
447 * blocks is reserved at the end of the device where the tables are
449 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
450 * bad) block in the stored bbt
451 * @pattern: pattern to identify bad block table or factory marked good /
452 * bad blocks, can be NULL, if len = 0
454 * Descriptor for the bad block table marker and the descriptor for the
455 * pattern which identifies good and bad blocks. The assumption is made
456 * that the pattern and the version count are always located in the oob area
457 * of the first block.
459 struct nand_bbt_descr {
461 int pages[NAND_MAX_CHIPS];
464 uint8_t version[NAND_MAX_CHIPS];
467 int reserved_block_code;
471 /* Options for the bad block table descriptors */
473 /* The number of bits used per block in the bbt on the device */
474 #define NAND_BBT_NRBITS_MSK 0x0000000F
475 #define NAND_BBT_1BIT 0x00000001
476 #define NAND_BBT_2BIT 0x00000002
477 #define NAND_BBT_4BIT 0x00000004
478 #define NAND_BBT_8BIT 0x00000008
479 /* The bad block table is in the last good block of the device */
480 #define NAND_BBT_LASTBLOCK 0x00000010
481 /* The bbt is at the given page, else we must scan for the bbt */
482 #define NAND_BBT_ABSPAGE 0x00000020
483 /* The bbt is at the given page, else we must scan for the bbt */
484 #define NAND_BBT_SEARCH 0x00000040
485 /* bbt is stored per chip on multichip devices */
486 #define NAND_BBT_PERCHIP 0x00000080
487 /* bbt has a version counter at offset veroffs */
488 #define NAND_BBT_VERSION 0x00000100
489 /* Create a bbt if none axists */
490 #define NAND_BBT_CREATE 0x00000200
491 /* Search good / bad pattern through all pages of a block */
492 #define NAND_BBT_SCANALLPAGES 0x00000400
493 /* Scan block empty during good / bad block scan */
494 #define NAND_BBT_SCANEMPTY 0x00000800
495 /* Write bbt if neccecary */
496 #define NAND_BBT_WRITE 0x00001000
497 /* Read and write back block contents when writing bbt */
498 #define NAND_BBT_SAVECONTENT 0x00002000
499 /* Search good / bad pattern on the first and the second page */
500 #define NAND_BBT_SCAN2NDPAGE 0x00004000
502 /* The maximum number of blocks to scan for a bbt */
503 #define NAND_BBT_SCAN_MAXBLOCKS 4
505 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
506 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
507 extern int nand_default_bbt(struct mtd_info *mtd);
508 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
509 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
511 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
512 size_t * retlen, uint8_t * buf);
515 * Constants for oob configuration
517 #define NAND_SMALL_BADBLOCK_POS 5
518 #define NAND_LARGE_BADBLOCK_POS 0
521 * struct platform_nand_chip - chip level device structure
523 * @nr_chips: max. number of chips to scan for
524 * @chip_offs: chip number offset
525 * @nr_partitions: number of partitions pointed to by partitions (or zero)
526 * @partitions: mtd partition list
527 * @chip_delay: R/B delay value in us
528 * @options: Option flags, e.g. 16bit buswidth
529 * @ecclayout: ecc layout info structure
530 * @priv: hardware controller specific settings
532 struct platform_nand_chip {
536 struct mtd_partition *partitions;
537 struct nand_ecclayout *ecclayout;
539 unsigned int options;
544 * struct platform_nand_ctrl - controller level device structure
546 * @hwcontrol: platform specific hardware control structure
547 * @dev_ready: platform specific function to read ready/busy pin
548 * @select_chip: platform specific chip select function
549 * @priv_data: private data to transport driver specific settings
551 * All fields are optional and depend on the hardware driver requirements
553 struct platform_nand_ctrl {
554 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
555 int (*dev_ready)(struct mtd_info *mtd);
556 void (*select_chip)(struct mtd_info *mtd, int chip);
560 /* Some helpers to access the data structures */
562 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
564 struct nand_chip *chip = mtd->priv;
569 #endif /* __LINUX_MTD_NAND_H */