2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/netdevice.h>
25 #include <linux/rtnetlink.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/pci.h>
29 #include <linux/mii.h>
30 #include <linux/delay.h>
31 #include <linux/crc32.h>
32 #include <linux/dma-mapping.h>
35 #define net_drv(p, arg...) if (netif_msg_drv(p)) \
37 #define net_probe(p, arg...) if (netif_msg_probe(p)) \
39 #define net_link(p, arg...) if (netif_msg_link(p)) \
41 #define net_intr(p, arg...) if (netif_msg_intr(p)) \
43 #define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
46 #define PHY_MAX_ADDR 32
47 #define PHY_ID_ANY 0x1f
48 #define MII_REG_ANY 0x1f
50 #define DRV_VERSION "1.2"
51 #define DRV_NAME "sis190"
52 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
53 #define PFX DRV_NAME ": "
55 #define sis190_rx_skb netif_rx
56 #define sis190_rx_quota(count, quota) count
58 #define MAC_ADDR_LEN 6
60 #define NUM_TX_DESC 64 /* [8..1024] */
61 #define NUM_RX_DESC 64 /* [8..8192] */
62 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
63 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
64 #define RX_BUF_SIZE 1536
65 #define RX_BUF_MASK 0xfff8
67 #define SIS190_REGS_SIZE 0x80
68 #define SIS190_TX_TIMEOUT (6*HZ)
69 #define SIS190_PHY_TIMEOUT (10*HZ)
70 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
71 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
74 /* Enhanced PHY access register bit definitions */
75 #define EhnMIIread 0x0000
76 #define EhnMIIwrite 0x0020
77 #define EhnMIIdataShift 16
78 #define EhnMIIpmdShift 6 /* 7016 only */
79 #define EhnMIIregShift 11
80 #define EhnMIIreq 0x0010
81 #define EhnMIInotDone 0x0010
83 /* Write/read MMIO register */
84 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
85 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
86 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
87 #define SIS_R8(reg) readb (ioaddr + (reg))
88 #define SIS_R16(reg) readw (ioaddr + (reg))
89 #define SIS_R32(reg) readl (ioaddr + (reg))
91 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
93 enum sis190_registers {
95 TxDescStartAddr = 0x04,
96 rsv0 = 0x08, // reserved
97 TxSts = 0x0c, // unused (Control/Status)
99 RxDescStartAddr = 0x14,
100 rsv1 = 0x18, // reserved
101 RxSts = 0x1c, // unused
105 IntrTimer = 0x2c, // unused (Interupt Timer)
106 PMControl = 0x30, // unused (Power Mgmt Control/Status)
107 rsv2 = 0x34, // reserved
110 StationControl = 0x40,
112 GIoCR = 0x48, // unused (GMAC IO Compensation)
113 GIoCtrl = 0x4c, // unused (GMAC IO Control)
115 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
116 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
117 rsv3 = 0x5c, // reserved
121 // Undocumented = 0x6c,
123 RxWolData = 0x74, // unused (Rx WOL Data Access)
124 RxMPSControl = 0x78, // unused (Rx MPS Control)
125 rsv4 = 0x7c, // reserved
128 enum sis190_register_content {
130 SoftInt = 0x40000000, // unused
131 Timeup = 0x20000000, // unused
132 PauseFrame = 0x00080000, // unused
133 MagicPacket = 0x00040000, // unused
134 WakeupFrame = 0x00020000, // unused
135 LinkChange = 0x00010000,
136 RxQEmpty = 0x00000080,
138 TxQ1Empty = 0x00000020, // unused
139 TxQ1Int = 0x00000010,
140 TxQ0Empty = 0x00000008, // unused
141 TxQ0Int = 0x00000004,
147 CmdRxEnb = 0x08, // unused
149 RxBufEmpty = 0x01, // unused
152 Cfg9346_Lock = 0x00, // unused
153 Cfg9346_Unlock = 0xc0, // unused
156 AcceptErr = 0x20, // unused
157 AcceptRunt = 0x10, // unused
158 AcceptBroadcast = 0x0800,
159 AcceptMulticast = 0x0400,
160 AcceptMyPhys = 0x0200,
161 AcceptAllPhys = 0x0100,
165 RxCfgDMAShift = 8, // 0x1a in RxControl ?
168 TxInterFrameGapShift = 24,
169 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
171 LinkStatus = 0x02, // unused
172 FullDup = 0x01, // unused
175 TBILinkOK = 0x02000000, // unused
192 enum _DescStatusBit {
194 OWNbit = 0x80000000, // RXOWN/TXOWN
195 INTbit = 0x40000000, // RXINT/TXINT
196 CRCbit = 0x00020000, // CRCOFF/CRCEN
197 PADbit = 0x00010000, // PREADD/PADEN
199 RingEnd = 0x80000000,
201 LSEN = 0x08000000, // TSO ? -- FR
220 ColCountMask = 0x0000ffff,
234 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
243 RxSizeMask = 0x0000ffff
245 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
246 * provide two (unused with Linux) Tx queues. No publically
247 * available documentation alas.
251 enum sis190_eeprom_access_register_bits {
252 EECS = 0x00000001, // unused
253 EECLK = 0x00000002, // unused
254 EEDO = 0x00000008, // unused
255 EEDI = 0x00000004, // unused
258 EEWOP = 0x00000100 // unused
261 /* EEPROM Addresses */
262 enum sis190_eeprom_address {
263 EEPROMSignature = 0x00,
264 EEPROMCLK = 0x01, // unused
269 enum sis190_feature {
275 struct sis190_private {
276 void __iomem *mmio_addr;
277 struct pci_dev *pci_dev;
278 struct net_device *dev;
287 struct RxDesc *RxDescRing;
288 struct TxDesc *TxDescRing;
289 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
290 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
291 struct work_struct phy_task;
292 struct timer_list timer;
294 struct mii_if_info mii_if;
295 struct list_head first_phy;
300 struct list_head list;
307 enum sis190_phy_type {
314 static struct mii_chip_info {
319 } mii_chip_table[] = {
320 { "Atheros PHY", { 0x004d, 0xd010 }, LAN, 0 },
321 { "Atheros PHY AR8012", { 0x004d, 0xd020 }, LAN, 0 },
322 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
323 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
324 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
325 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
326 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
330 static const struct {
332 } sis_chip_info[] = {
333 { "SiS 190 PCI Fast Ethernet adapter" },
334 { "SiS 191 PCI Gigabit Ethernet adapter" },
337 static struct pci_device_id sis190_pci_tbl[] = {
338 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
339 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
343 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
345 static int rx_copybreak = 200;
351 MODULE_DESCRIPTION("SiS sis190/191 Gigabit Ethernet driver");
352 module_param(rx_copybreak, int, 0);
353 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
354 module_param_named(debug, debug.msg_enable, int, 0);
355 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
356 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
357 MODULE_VERSION(DRV_VERSION);
358 MODULE_LICENSE("GPL");
360 static const u32 sis190_intr_mask =
361 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
364 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
365 * The chips use a 64 element hash table based on the Ethernet CRC.
367 static const int multicast_filter_limit = 32;
369 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
373 SIS_W32(GMIIControl, ctl);
377 for (i = 0; i < 100; i++) {
378 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
384 printk(KERN_ERR PFX "PHY command failed !\n");
387 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
389 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
390 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
391 (((u32) val) << EhnMIIdataShift));
394 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
396 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
397 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
399 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
402 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
404 struct sis190_private *tp = netdev_priv(dev);
406 mdio_write(tp->mmio_addr, phy_id, reg, val);
409 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
411 struct sis190_private *tp = netdev_priv(dev);
413 return mdio_read(tp->mmio_addr, phy_id, reg);
416 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
418 mdio_read(ioaddr, phy_id, reg);
419 return mdio_read(ioaddr, phy_id, reg);
422 static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
427 if (!(SIS_R32(ROMControl) & 0x0002))
430 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
432 for (i = 0; i < 200; i++) {
433 if (!(SIS_R32(ROMInterface) & EEREQ)) {
434 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
443 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
445 SIS_W32(IntrMask, 0x00);
446 SIS_W32(IntrStatus, 0xffffffff);
450 static void sis190_asic_down(void __iomem *ioaddr)
452 /* Stop the chip's Tx and Rx DMA processes. */
454 SIS_W32(TxControl, 0x1a00);
455 SIS_W32(RxControl, 0x1a00);
457 sis190_irq_mask_and_ack(ioaddr);
460 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
462 desc->size |= cpu_to_le32(RingEnd);
465 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
467 u32 eor = le32_to_cpu(desc->size) & RingEnd;
470 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
472 desc->status = cpu_to_le32(OWNbit | INTbit);
475 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
478 desc->addr = cpu_to_le32(mapping);
479 sis190_give_to_asic(desc, rx_buf_sz);
482 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
485 desc->addr = cpu_to_le32(0xdeadbeef);
486 desc->size &= cpu_to_le32(RingEnd);
491 static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
494 u32 rx_buf_sz = tp->rx_buf_sz;
497 skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
501 mapping = pci_map_single(tp->pci_dev, skb->data, tp->rx_buf_sz,
503 sis190_map_to_asic(desc, mapping, rx_buf_sz);
505 sis190_make_unusable_by_asic(desc);
510 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
515 for (cur = start; cur < end; cur++) {
516 unsigned int i = cur % NUM_RX_DESC;
518 if (tp->Rx_skbuff[i])
521 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
523 if (!tp->Rx_skbuff[i])
529 static bool sis190_try_rx_copy(struct sis190_private *tp,
530 struct sk_buff **sk_buff, int pkt_size,
536 if (pkt_size >= rx_copybreak)
539 skb = netdev_alloc_skb(tp->dev, pkt_size + 2);
543 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, tp->rx_buf_sz,
546 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
553 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
555 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
557 if ((status & CRCOK) && !(status & ErrMask))
560 if (!(status & CRCOK))
561 stats->rx_crc_errors++;
562 else if (status & OVRUN)
563 stats->rx_over_errors++;
564 else if (status & (SHORT | LIMIT))
565 stats->rx_length_errors++;
566 else if (status & (MIIER | NIBON | COLON))
567 stats->rx_frame_errors++;
573 static int sis190_rx_interrupt(struct net_device *dev,
574 struct sis190_private *tp, void __iomem *ioaddr)
576 struct net_device_stats *stats = &dev->stats;
577 u32 rx_left, cur_rx = tp->cur_rx;
580 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
581 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
583 for (; rx_left > 0; rx_left--, cur_rx++) {
584 unsigned int entry = cur_rx % NUM_RX_DESC;
585 struct RxDesc *desc = tp->RxDescRing + entry;
588 if (le32_to_cpu(desc->status) & OWNbit)
591 status = le32_to_cpu(desc->PSize);
593 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
596 if (sis190_rx_pkt_err(status, stats) < 0)
597 sis190_give_to_asic(desc, tp->rx_buf_sz);
599 struct sk_buff *skb = tp->Rx_skbuff[entry];
600 dma_addr_t addr = le32_to_cpu(desc->addr);
601 int pkt_size = (status & RxSizeMask) - 4;
602 struct pci_dev *pdev = tp->pci_dev;
604 if (unlikely(pkt_size > tp->rx_buf_sz)) {
605 net_intr(tp, KERN_INFO
606 "%s: (frag) status = %08x.\n",
609 stats->rx_length_errors++;
610 sis190_give_to_asic(desc, tp->rx_buf_sz);
615 if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
616 pci_dma_sync_single_for_device(pdev, addr,
617 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
618 sis190_give_to_asic(desc, tp->rx_buf_sz);
620 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
622 tp->Rx_skbuff[entry] = NULL;
623 sis190_make_unusable_by_asic(desc);
626 skb_put(skb, pkt_size);
627 skb->protocol = eth_type_trans(skb, dev);
632 stats->rx_bytes += pkt_size;
633 if ((status & BCAST) == MCAST)
637 count = cur_rx - tp->cur_rx;
640 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
641 if (!delta && count && netif_msg_intr(tp))
642 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
643 tp->dirty_rx += delta;
645 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
646 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
651 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
656 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
658 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
660 memset(desc, 0x00, sizeof(*desc));
663 static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
665 #define TxErrMask (WND | TABRT | FIFO | LINK)
667 if (!unlikely(status & TxErrMask))
671 stats->tx_window_errors++;
673 stats->tx_aborted_errors++;
675 stats->tx_fifo_errors++;
677 stats->tx_carrier_errors++;
684 static void sis190_tx_interrupt(struct net_device *dev,
685 struct sis190_private *tp, void __iomem *ioaddr)
687 struct net_device_stats *stats = &dev->stats;
688 u32 pending, dirty_tx = tp->dirty_tx;
690 * It would not be needed if queueing was allowed to be enabled
691 * again too early (hint: think preempt and unclocked smp systems).
693 unsigned int queue_stopped;
696 pending = tp->cur_tx - dirty_tx;
697 queue_stopped = (pending == NUM_TX_DESC);
699 for (; pending; pending--, dirty_tx++) {
700 unsigned int entry = dirty_tx % NUM_TX_DESC;
701 struct TxDesc *txd = tp->TxDescRing + entry;
702 u32 status = le32_to_cpu(txd->status);
708 skb = tp->Tx_skbuff[entry];
710 if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
712 stats->tx_bytes += skb->len;
713 stats->collisions += ((status & ColCountMask) - 1);
716 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
717 tp->Tx_skbuff[entry] = NULL;
718 dev_kfree_skb_irq(skb);
721 if (tp->dirty_tx != dirty_tx) {
722 tp->dirty_tx = dirty_tx;
725 netif_wake_queue(dev);
730 * The interrupt handler does all of the Rx thread work and cleans up after
733 static irqreturn_t sis190_interrupt(int irq, void *__dev)
735 struct net_device *dev = __dev;
736 struct sis190_private *tp = netdev_priv(dev);
737 void __iomem *ioaddr = tp->mmio_addr;
738 unsigned int handled = 0;
741 status = SIS_R32(IntrStatus);
743 if ((status == 0xffffffff) || !status)
748 if (unlikely(!netif_running(dev))) {
749 sis190_asic_down(ioaddr);
753 SIS_W32(IntrStatus, status);
755 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
757 if (status & LinkChange) {
758 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
759 schedule_work(&tp->phy_task);
763 sis190_rx_interrupt(dev, tp, ioaddr);
765 if (status & TxQ0Int)
766 sis190_tx_interrupt(dev, tp, ioaddr);
768 return IRQ_RETVAL(handled);
771 #ifdef CONFIG_NET_POLL_CONTROLLER
772 static void sis190_netpoll(struct net_device *dev)
774 struct sis190_private *tp = netdev_priv(dev);
775 struct pci_dev *pdev = tp->pci_dev;
777 disable_irq(pdev->irq);
778 sis190_interrupt(pdev->irq, dev);
779 enable_irq(pdev->irq);
783 static void sis190_free_rx_skb(struct sis190_private *tp,
784 struct sk_buff **sk_buff, struct RxDesc *desc)
786 struct pci_dev *pdev = tp->pci_dev;
788 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
790 dev_kfree_skb(*sk_buff);
792 sis190_make_unusable_by_asic(desc);
795 static void sis190_rx_clear(struct sis190_private *tp)
799 for (i = 0; i < NUM_RX_DESC; i++) {
800 if (!tp->Rx_skbuff[i])
802 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
806 static void sis190_init_ring_indexes(struct sis190_private *tp)
808 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
811 static int sis190_init_ring(struct net_device *dev)
813 struct sis190_private *tp = netdev_priv(dev);
815 sis190_init_ring_indexes(tp);
817 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
818 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
820 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
823 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
832 static void sis190_set_rx_mode(struct net_device *dev)
834 struct sis190_private *tp = netdev_priv(dev);
835 void __iomem *ioaddr = tp->mmio_addr;
837 u32 mc_filter[2]; /* Multicast hash filter */
840 if (dev->flags & IFF_PROMISC) {
842 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
844 mc_filter[1] = mc_filter[0] = 0xffffffff;
845 } else if ((dev->mc_count > multicast_filter_limit) ||
846 (dev->flags & IFF_ALLMULTI)) {
847 /* Too many to filter perfectly -- accept all multicasts. */
848 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
849 mc_filter[1] = mc_filter[0] = 0xffffffff;
851 struct dev_mc_list *mclist;
854 rx_mode = AcceptBroadcast | AcceptMyPhys;
855 mc_filter[1] = mc_filter[0] = 0;
856 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
857 i++, mclist = mclist->next) {
859 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
860 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
861 rx_mode |= AcceptMulticast;
865 spin_lock_irqsave(&tp->lock, flags);
867 SIS_W16(RxMacControl, rx_mode | 0x2);
868 SIS_W32(RxHashTable, mc_filter[0]);
869 SIS_W32(RxHashTable + 4, mc_filter[1]);
871 spin_unlock_irqrestore(&tp->lock, flags);
874 static void sis190_soft_reset(void __iomem *ioaddr)
876 SIS_W32(IntrControl, 0x8000);
878 SIS_W32(IntrControl, 0x0);
879 sis190_asic_down(ioaddr);
882 static void sis190_hw_start(struct net_device *dev)
884 struct sis190_private *tp = netdev_priv(dev);
885 void __iomem *ioaddr = tp->mmio_addr;
887 sis190_soft_reset(ioaddr);
889 SIS_W32(TxDescStartAddr, tp->tx_dma);
890 SIS_W32(RxDescStartAddr, tp->rx_dma);
892 SIS_W32(IntrStatus, 0xffffffff);
893 SIS_W32(IntrMask, 0x0);
894 SIS_W32(GMIIControl, 0x0);
895 SIS_W32(TxMacControl, 0x60);
896 SIS_W16(RxMacControl, 0x02);
897 SIS_W32(RxHashTable, 0x0);
899 SIS_W32(RxWolCtrl, 0x0);
900 SIS_W32(RxWolData, 0x0);
904 sis190_set_rx_mode(dev);
906 /* Enable all known interrupts by setting the interrupt mask. */
907 SIS_W32(IntrMask, sis190_intr_mask);
909 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
910 SIS_W32(RxControl, 0x1a1d);
912 netif_start_queue(dev);
915 static void sis190_phy_task(struct work_struct *work)
917 struct sis190_private *tp =
918 container_of(work, struct sis190_private, phy_task);
919 struct net_device *dev = tp->dev;
920 void __iomem *ioaddr = tp->mmio_addr;
921 int phy_id = tp->mii_if.phy_id;
926 if (!netif_running(dev))
929 val = mdio_read(ioaddr, phy_id, MII_BMCR);
930 if (val & BMCR_RESET) {
931 // FIXME: needlessly high ? -- FR 02/07/2005
932 mod_timer(&tp->timer, jiffies + HZ/10);
933 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
934 BMSR_ANEGCOMPLETE)) {
935 netif_carrier_off(dev);
936 net_link(tp, KERN_WARNING "%s: auto-negotiating...\n",
938 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
946 { LPA_1000XFULL | LPA_SLCT, 0x07000c00 | 0x00001000,
947 "1000 Mbps Full Duplex" },
948 { LPA_1000XHALF | LPA_SLCT, 0x07000c00,
949 "1000 Mbps Half Duplex" },
950 { LPA_100FULL, 0x04000800 | 0x00001000,
951 "100 Mbps Full Duplex" },
952 { LPA_100HALF, 0x04000800,
953 "100 Mbps Half Duplex" },
954 { LPA_10FULL, 0x04000400 | 0x00001000,
955 "10 Mbps Full Duplex" },
956 { LPA_10HALF, 0x04000400,
957 "10 Mbps Half Duplex" },
958 { 0, 0x04000400, "unknown" }
962 val = mdio_read(ioaddr, phy_id, 0x1f);
963 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
965 val = mdio_read(ioaddr, phy_id, MII_LPA);
966 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
967 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
968 dev->name, val, adv);
972 for (p = reg31; p->val; p++) {
973 if ((val & p->val) == p->val)
977 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
979 if ((tp->features & F_HAS_RGMII) &&
980 (tp->features & F_PHY_BCM5461)) {
981 // Set Tx Delay in RGMII mode.
982 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
984 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
985 p->ctl |= 0x03000000;
988 SIS_W32(StationControl, p->ctl);
990 if (tp->features & F_HAS_RGMII) {
991 SIS_W32(RGDelay, 0x0441);
992 SIS_W32(RGDelay, 0x0440);
995 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
997 netif_carrier_on(dev);
1004 static void sis190_phy_timer(unsigned long __opaque)
1006 struct net_device *dev = (struct net_device *)__opaque;
1007 struct sis190_private *tp = netdev_priv(dev);
1009 if (likely(netif_running(dev)))
1010 schedule_work(&tp->phy_task);
1013 static inline void sis190_delete_timer(struct net_device *dev)
1015 struct sis190_private *tp = netdev_priv(dev);
1017 del_timer_sync(&tp->timer);
1020 static inline void sis190_request_timer(struct net_device *dev)
1022 struct sis190_private *tp = netdev_priv(dev);
1023 struct timer_list *timer = &tp->timer;
1026 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1027 timer->data = (unsigned long)dev;
1028 timer->function = sis190_phy_timer;
1032 static void sis190_set_rxbufsize(struct sis190_private *tp,
1033 struct net_device *dev)
1035 unsigned int mtu = dev->mtu;
1037 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1038 /* RxDesc->size has a licence to kill the lower bits */
1039 if (tp->rx_buf_sz & 0x07) {
1041 tp->rx_buf_sz &= RX_BUF_MASK;
1045 static int sis190_open(struct net_device *dev)
1047 struct sis190_private *tp = netdev_priv(dev);
1048 struct pci_dev *pdev = tp->pci_dev;
1051 sis190_set_rxbufsize(tp, dev);
1054 * Rx and Tx descriptors need 256 bytes alignment.
1055 * pci_alloc_consistent() guarantees a stronger alignment.
1057 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1058 if (!tp->TxDescRing)
1061 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1062 if (!tp->RxDescRing)
1065 rc = sis190_init_ring(dev);
1069 sis190_request_timer(dev);
1071 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
1073 goto err_release_timer_2;
1075 sis190_hw_start(dev);
1079 err_release_timer_2:
1080 sis190_delete_timer(dev);
1081 sis190_rx_clear(tp);
1083 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1086 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1091 static void sis190_tx_clear(struct sis190_private *tp)
1095 for (i = 0; i < NUM_TX_DESC; i++) {
1096 struct sk_buff *skb = tp->Tx_skbuff[i];
1101 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1102 tp->Tx_skbuff[i] = NULL;
1105 tp->dev->stats.tx_dropped++;
1107 tp->cur_tx = tp->dirty_tx = 0;
1110 static void sis190_down(struct net_device *dev)
1112 struct sis190_private *tp = netdev_priv(dev);
1113 void __iomem *ioaddr = tp->mmio_addr;
1114 unsigned int poll_locked = 0;
1116 sis190_delete_timer(dev);
1118 netif_stop_queue(dev);
1121 spin_lock_irq(&tp->lock);
1123 sis190_asic_down(ioaddr);
1125 spin_unlock_irq(&tp->lock);
1127 synchronize_irq(dev->irq);
1132 synchronize_sched();
1134 } while (SIS_R32(IntrMask));
1136 sis190_tx_clear(tp);
1137 sis190_rx_clear(tp);
1140 static int sis190_close(struct net_device *dev)
1142 struct sis190_private *tp = netdev_priv(dev);
1143 struct pci_dev *pdev = tp->pci_dev;
1147 free_irq(dev->irq, dev);
1149 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1150 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1152 tp->TxDescRing = NULL;
1153 tp->RxDescRing = NULL;
1158 static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1160 struct sis190_private *tp = netdev_priv(dev);
1161 void __iomem *ioaddr = tp->mmio_addr;
1162 u32 len, entry, dirty_tx;
1163 struct TxDesc *desc;
1166 if (unlikely(skb->len < ETH_ZLEN)) {
1167 if (skb_padto(skb, ETH_ZLEN)) {
1168 dev->stats.tx_dropped++;
1176 entry = tp->cur_tx % NUM_TX_DESC;
1177 desc = tp->TxDescRing + entry;
1179 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1180 netif_stop_queue(dev);
1181 net_tx_err(tp, KERN_ERR PFX
1182 "%s: BUG! Tx Ring full when queue awake!\n",
1184 return NETDEV_TX_BUSY;
1187 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1189 tp->Tx_skbuff[entry] = skb;
1191 desc->PSize = cpu_to_le32(len);
1192 desc->addr = cpu_to_le32(mapping);
1194 desc->size = cpu_to_le32(len);
1195 if (entry == (NUM_TX_DESC - 1))
1196 desc->size |= cpu_to_le32(RingEnd);
1200 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1206 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1208 dirty_tx = tp->dirty_tx;
1209 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1210 netif_stop_queue(dev);
1212 if (dirty_tx != tp->dirty_tx)
1213 netif_wake_queue(dev);
1216 return NETDEV_TX_OK;
1219 static void sis190_free_phy(struct list_head *first_phy)
1221 struct sis190_phy *cur, *next;
1223 list_for_each_entry_safe(cur, next, first_phy, list) {
1229 * sis190_default_phy - Select default PHY for sis190 mac.
1230 * @dev: the net device to probe for
1232 * Select first detected PHY with link as default.
1233 * If no one is link on, select PHY whose types is HOME as default.
1234 * If HOME doesn't exist, select LAN.
1236 static u16 sis190_default_phy(struct net_device *dev)
1238 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1239 struct sis190_private *tp = netdev_priv(dev);
1240 struct mii_if_info *mii_if = &tp->mii_if;
1241 void __iomem *ioaddr = tp->mmio_addr;
1244 phy_home = phy_default = phy_lan = NULL;
1246 list_for_each_entry(phy, &tp->first_phy, list) {
1247 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1249 // Link ON & Not select default PHY & not ghost PHY.
1250 if ((status & BMSR_LSTATUS) &&
1252 (phy->type != UNKNOWN)) {
1255 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1256 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1257 status | BMCR_ANENABLE | BMCR_ISOLATE);
1258 if (phy->type == HOME)
1260 else if (phy->type == LAN)
1267 phy_default = phy_home;
1269 phy_default = phy_lan;
1271 phy_default = list_entry(&tp->first_phy,
1272 struct sis190_phy, list);
1275 if (mii_if->phy_id != phy_default->phy_id) {
1276 mii_if->phy_id = phy_default->phy_id;
1277 net_probe(tp, KERN_INFO
1278 "%s: Using transceiver at address %d as default.\n",
1279 pci_name(tp->pci_dev), mii_if->phy_id);
1282 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1283 status &= (~BMCR_ISOLATE);
1285 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1286 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1291 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1292 struct sis190_phy *phy, unsigned int phy_id,
1295 void __iomem *ioaddr = tp->mmio_addr;
1296 struct mii_chip_info *p;
1298 INIT_LIST_HEAD(&phy->list);
1299 phy->status = mii_status;
1300 phy->phy_id = phy_id;
1302 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1303 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1305 for (p = mii_chip_table; p->type; p++) {
1306 if ((p->id[0] == phy->id[0]) &&
1307 (p->id[1] == (phy->id[1] & 0xfff0))) {
1313 phy->type = (p->type == MIX) ?
1314 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1315 LAN : HOME) : p->type;
1316 tp->features |= p->feature;
1317 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
1318 pci_name(tp->pci_dev), p->name, phy_id);
1320 phy->type = UNKNOWN;
1321 net_probe(tp, KERN_INFO
1322 "%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",
1323 pci_name(tp->pci_dev),
1324 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
1328 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1330 if (tp->features & F_PHY_88E1111) {
1331 void __iomem *ioaddr = tp->mmio_addr;
1332 int phy_id = tp->mii_if.phy_id;
1338 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1340 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1342 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1348 * sis190_mii_probe - Probe MII PHY for sis190
1349 * @dev: the net device to probe for
1351 * Search for total of 32 possible mii phy addresses.
1352 * Identify and set current phy if found one,
1353 * return error if it failed to found.
1355 static int __devinit sis190_mii_probe(struct net_device *dev)
1357 struct sis190_private *tp = netdev_priv(dev);
1358 struct mii_if_info *mii_if = &tp->mii_if;
1359 void __iomem *ioaddr = tp->mmio_addr;
1363 INIT_LIST_HEAD(&tp->first_phy);
1365 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1366 struct sis190_phy *phy;
1369 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1371 // Try next mii if the current one is not accessible.
1372 if (status == 0xffff || status == 0x0000)
1375 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1377 sis190_free_phy(&tp->first_phy);
1382 sis190_init_phy(dev, tp, phy, phy_id, status);
1384 list_add(&tp->first_phy, &phy->list);
1387 if (list_empty(&tp->first_phy)) {
1388 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
1389 pci_name(tp->pci_dev));
1394 /* Select default PHY for mac */
1395 sis190_default_phy(dev);
1397 sis190_mii_probe_88e1111_fixup(tp);
1400 mii_if->mdio_read = __mdio_read;
1401 mii_if->mdio_write = __mdio_write;
1402 mii_if->phy_id_mask = PHY_ID_ANY;
1403 mii_if->reg_num_mask = MII_REG_ANY;
1408 static void sis190_mii_remove(struct net_device *dev)
1410 struct sis190_private *tp = netdev_priv(dev);
1412 sis190_free_phy(&tp->first_phy);
1415 static void sis190_release_board(struct pci_dev *pdev)
1417 struct net_device *dev = pci_get_drvdata(pdev);
1418 struct sis190_private *tp = netdev_priv(dev);
1420 iounmap(tp->mmio_addr);
1421 pci_release_regions(pdev);
1422 pci_disable_device(pdev);
1426 static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1428 struct sis190_private *tp;
1429 struct net_device *dev;
1430 void __iomem *ioaddr;
1433 dev = alloc_etherdev(sizeof(*tp));
1435 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1440 SET_NETDEV_DEV(dev, &pdev->dev);
1442 tp = netdev_priv(dev);
1444 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1446 rc = pci_enable_device(pdev);
1448 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1449 goto err_free_dev_1;
1454 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1455 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1457 goto err_pci_disable_2;
1459 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1460 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1462 goto err_pci_disable_2;
1465 rc = pci_request_regions(pdev, DRV_NAME);
1467 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1469 goto err_pci_disable_2;
1472 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1474 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1476 goto err_free_res_3;
1479 pci_set_master(pdev);
1481 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1483 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1486 goto err_free_res_3;
1490 tp->mmio_addr = ioaddr;
1492 sis190_irq_mask_and_ack(ioaddr);
1494 sis190_soft_reset(ioaddr);
1499 pci_release_regions(pdev);
1501 pci_disable_device(pdev);
1509 static void sis190_tx_timeout(struct net_device *dev)
1511 struct sis190_private *tp = netdev_priv(dev);
1512 void __iomem *ioaddr = tp->mmio_addr;
1515 /* Disable Tx, if not already */
1516 tmp8 = SIS_R8(TxControl);
1517 if (tmp8 & CmdTxEnb)
1518 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1521 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1522 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1524 /* Disable interrupts by clearing the interrupt mask. */
1525 SIS_W32(IntrMask, 0x0000);
1527 /* Stop a shared interrupt from scavenging while we are. */
1528 spin_lock_irq(&tp->lock);
1529 sis190_tx_clear(tp);
1530 spin_unlock_irq(&tp->lock);
1532 /* ...and finally, reset everything. */
1533 sis190_hw_start(dev);
1535 netif_wake_queue(dev);
1538 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1540 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1543 static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1544 struct net_device *dev)
1546 struct sis190_private *tp = netdev_priv(dev);
1547 void __iomem *ioaddr = tp->mmio_addr;
1551 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1554 /* Check to see if there is a sane EEPROM */
1555 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1557 if ((sig == 0xffff) || (sig == 0x0000)) {
1558 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1559 pci_name(pdev), sig);
1563 /* Get MAC address from EEPROM */
1564 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1565 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1567 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(w);
1570 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1576 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
1578 * @dev: network device to get address for
1580 * SiS96x model, use APC CMOS RAM to store MAC address.
1581 * APC CMOS RAM is accessed through ISA bridge.
1582 * MAC address is read into @net_dev->dev_addr.
1584 static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1585 struct net_device *dev)
1587 static const u16 __devinitdata ids[] = { 0x0965, 0x0966, 0x0968 };
1588 struct sis190_private *tp = netdev_priv(dev);
1589 struct pci_dev *isa_bridge;
1593 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1596 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1597 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1603 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1608 /* Enable port 78h & 79h to access APC Registers. */
1609 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1610 reg = (tmp8 & ~0x02);
1611 pci_write_config_byte(isa_bridge, 0x48, reg);
1613 pci_read_config_byte(isa_bridge, 0x48, ®);
1615 for (i = 0; i < MAC_ADDR_LEN; i++) {
1616 outb(0x9 + i, 0x78);
1617 dev->dev_addr[i] = inb(0x79);
1623 sis190_set_rgmii(tp, reg);
1625 /* Restore the value to ISA Bridge */
1626 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1627 pci_dev_put(isa_bridge);
1633 * sis190_init_rxfilter - Initialize the Rx filter
1634 * @dev: network device to initialize
1636 * Set receive filter address to our MAC address
1637 * and enable packet filtering.
1639 static inline void sis190_init_rxfilter(struct net_device *dev)
1641 struct sis190_private *tp = netdev_priv(dev);
1642 void __iomem *ioaddr = tp->mmio_addr;
1646 ctl = SIS_R16(RxMacControl);
1648 * Disable packet filtering before setting filter.
1649 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1650 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1652 SIS_W16(RxMacControl, ctl & ~0x0f00);
1654 for (i = 0; i < MAC_ADDR_LEN; i++)
1655 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1657 SIS_W16(RxMacControl, ctl);
1661 static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
1662 struct net_device *dev)
1666 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1670 pci_read_config_byte(pdev, 0x73, ®);
1672 if (reg & 0x00000001)
1673 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1678 static void sis190_set_speed_auto(struct net_device *dev)
1680 struct sis190_private *tp = netdev_priv(dev);
1681 void __iomem *ioaddr = tp->mmio_addr;
1682 int phy_id = tp->mii_if.phy_id;
1685 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1687 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1689 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1691 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1692 ADVERTISE_100FULL | ADVERTISE_10FULL |
1693 ADVERTISE_100HALF | ADVERTISE_10HALF);
1695 // Enable 1000 Full Mode.
1696 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1698 // Enable auto-negotiation and restart auto-negotiation.
1699 mdio_write(ioaddr, phy_id, MII_BMCR,
1700 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1703 static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1705 struct sis190_private *tp = netdev_priv(dev);
1707 return mii_ethtool_gset(&tp->mii_if, cmd);
1710 static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1712 struct sis190_private *tp = netdev_priv(dev);
1714 return mii_ethtool_sset(&tp->mii_if, cmd);
1717 static void sis190_get_drvinfo(struct net_device *dev,
1718 struct ethtool_drvinfo *info)
1720 struct sis190_private *tp = netdev_priv(dev);
1722 strcpy(info->driver, DRV_NAME);
1723 strcpy(info->version, DRV_VERSION);
1724 strcpy(info->bus_info, pci_name(tp->pci_dev));
1727 static int sis190_get_regs_len(struct net_device *dev)
1729 return SIS190_REGS_SIZE;
1732 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1735 struct sis190_private *tp = netdev_priv(dev);
1736 unsigned long flags;
1738 if (regs->len > SIS190_REGS_SIZE)
1739 regs->len = SIS190_REGS_SIZE;
1741 spin_lock_irqsave(&tp->lock, flags);
1742 memcpy_fromio(p, tp->mmio_addr, regs->len);
1743 spin_unlock_irqrestore(&tp->lock, flags);
1746 static int sis190_nway_reset(struct net_device *dev)
1748 struct sis190_private *tp = netdev_priv(dev);
1750 return mii_nway_restart(&tp->mii_if);
1753 static u32 sis190_get_msglevel(struct net_device *dev)
1755 struct sis190_private *tp = netdev_priv(dev);
1757 return tp->msg_enable;
1760 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1762 struct sis190_private *tp = netdev_priv(dev);
1764 tp->msg_enable = value;
1767 static const struct ethtool_ops sis190_ethtool_ops = {
1768 .get_settings = sis190_get_settings,
1769 .set_settings = sis190_set_settings,
1770 .get_drvinfo = sis190_get_drvinfo,
1771 .get_regs_len = sis190_get_regs_len,
1772 .get_regs = sis190_get_regs,
1773 .get_link = ethtool_op_get_link,
1774 .get_msglevel = sis190_get_msglevel,
1775 .set_msglevel = sis190_set_msglevel,
1776 .nway_reset = sis190_nway_reset,
1779 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1781 struct sis190_private *tp = netdev_priv(dev);
1783 return !netif_running(dev) ? -EINVAL :
1784 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1787 static const struct net_device_ops sis190_netdev_ops = {
1788 .ndo_open = sis190_open,
1789 .ndo_stop = sis190_close,
1790 .ndo_do_ioctl = sis190_ioctl,
1791 .ndo_start_xmit = sis190_start_xmit,
1792 .ndo_tx_timeout = sis190_tx_timeout,
1793 .ndo_set_multicast_list = sis190_set_rx_mode,
1794 .ndo_change_mtu = eth_change_mtu,
1795 .ndo_set_mac_address = eth_mac_addr,
1796 .ndo_validate_addr = eth_validate_addr,
1797 #ifdef CONFIG_NET_POLL_CONTROLLER
1798 .ndo_poll_controller = sis190_netpoll,
1802 static int __devinit sis190_init_one(struct pci_dev *pdev,
1803 const struct pci_device_id *ent)
1805 static int printed_version = 0;
1806 struct sis190_private *tp;
1807 struct net_device *dev;
1808 void __iomem *ioaddr;
1811 if (!printed_version) {
1812 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1813 printed_version = 1;
1816 dev = sis190_init_board(pdev);
1822 pci_set_drvdata(pdev, dev);
1824 tp = netdev_priv(dev);
1825 ioaddr = tp->mmio_addr;
1827 rc = sis190_get_mac_addr(pdev, dev);
1829 goto err_release_board;
1831 sis190_init_rxfilter(dev);
1833 INIT_WORK(&tp->phy_task, sis190_phy_task);
1835 dev->netdev_ops = &sis190_netdev_ops;
1837 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1838 dev->irq = pdev->irq;
1839 dev->base_addr = (unsigned long) 0xdead;
1840 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1842 spin_lock_init(&tp->lock);
1844 rc = sis190_mii_probe(dev);
1846 goto err_release_board;
1848 rc = register_netdev(dev);
1850 goto err_remove_mii;
1852 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), %pM\n",
1853 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1854 ioaddr, dev->irq, dev->dev_addr);
1856 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1857 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1859 netif_carrier_off(dev);
1861 sis190_set_speed_auto(dev);
1866 sis190_mii_remove(dev);
1868 sis190_release_board(pdev);
1872 static void __devexit sis190_remove_one(struct pci_dev *pdev)
1874 struct net_device *dev = pci_get_drvdata(pdev);
1876 sis190_mii_remove(dev);
1877 flush_scheduled_work();
1878 unregister_netdev(dev);
1879 sis190_release_board(pdev);
1880 pci_set_drvdata(pdev, NULL);
1883 static struct pci_driver sis190_pci_driver = {
1885 .id_table = sis190_pci_tbl,
1886 .probe = sis190_init_one,
1887 .remove = __devexit_p(sis190_remove_one),
1890 static int __init sis190_init_module(void)
1892 return pci_register_driver(&sis190_pci_driver);
1895 static void __exit sis190_cleanup_module(void)
1897 pci_unregister_driver(&sis190_pci_driver);
1900 module_init(sis190_init_module);
1901 module_exit(sis190_cleanup_module);