2 * Include file for Gigabit Ethernet device driver for Network
3 * Interface Cards (NICs) utilizing the Tamarack Microelectronics
4 * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
10 #include <linux/version.h>
11 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/ioport.h>
16 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/types.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/version.h>
25 #include <asm/bitops.h>
26 /*#include <asm/spinlock.h>*/
28 #define DrvVer "2.09d"
34 /* GMII based PHY IDs */
36 #define MARVELL 0x0141
37 #define ICPLUS_PHY 0x243
39 /* NIC Physical Layer Device MII register fields. */
40 #define MII_PHY_SELECTOR_IEEE8023 0x0001
41 #define MII_PHY_TECHABILITYFIELD 0x1FE0
43 /* GMII_PHY_1000 need to set to prefer master */
44 #define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
46 /* NIC Physical Layer Device GMII constants. */
47 #define GMII_PREAMBLE 0xFFFFFFFF
50 #define GMII_WRITE 0x1
51 #define GMII_TA_READ_MASK 0x1
52 #define GMII_TA_WRITE 0x2
54 /* I/O register offsets. */
57 RX_DMA_STATUS = 0x08, // Unused + reserved
58 TFD_LIST_PTR_0 = 0x10,
59 TFD_LIST_PTR_1 = 0x14,
60 TX_DMA_BURST_THRESH = 0x18,
61 TX_DMA_URGENT_THRESH = 0x19,
62 TX_DMA_POLL_PERIOD = 0x1a,
63 RFD_LIST_PTR_0 = 0x1c,
64 RFD_LIST_PTR_1 = 0x20,
65 RX_DMA_BURST_THRESH = 0x24,
66 RX_DMA_URGENT_THRESH = 0x25,
67 RX_DMA_POLL_PERIOD = 0x26,
70 FIFO_CTRL = 0x38, // Unused
71 FLOW_OFF_THRESH = 0x3c,
72 FLOW_ON_THRESH = 0x3e,
75 EXPROM_ADDR = 0x4c, // Unused
76 EXPROM_DATA = 0x50, // Unused
77 WAKE_EVENT = 0x51, // Unused
78 COUNTDOWN = 0x54, // Unused
79 INT_STATUS_ACK = 0x5a,
81 INT_STATUS = 0x5e, // Unused
84 VLAN_TAG = 0x70, // Unused
85 PHY_SET = 0x75, // JES20040127EEPROM
87 STATION_ADDRESS_0 = 0x78,
88 STATION_ADDRESS_1 = 0x7a,
89 STATION_ADDRESS_2 = 0x7c,
90 MAX_FRAME_SIZE = 0x86,
94 RMON_STATISTICS_MASK = 0x98,
95 STATISTICS_MASK = 0x9c,
96 RX_JUMBO_FRAMES = 0xbc, // Unused
97 TCP_CHECKSUM_ERRORS = 0xc0, // Unused
98 IP_CHECKSUM_ERRORS = 0xc2, // Unused
99 UDP_CHECKSUM_ERRORS = 0xc4, // Unused
100 TX_JUMBO_FRAMES = 0xf4 // Unused
103 /* Ethernet MIB statistic register offsets. */
104 #define IPG_OCTETRCVOK 0xA8
105 #define IPG_MCSTOCTETRCVDOK 0xAC
106 #define IPG_BCSTOCTETRCVOK 0xB0
107 #define IPG_FRAMESRCVDOK 0xB4
108 #define IPG_MCSTFRAMESRCVDOK 0xB8
109 #define IPG_BCSTFRAMESRCVDOK 0xBE
110 #define IPG_MACCONTROLFRAMESRCVD 0xC6
111 #define IPG_FRAMETOOLONGERRRORS 0xC8
112 #define IPG_INRANGELENGTHERRORS 0xCA
113 #define IPG_FRAMECHECKSEQERRORS 0xCC
114 #define IPG_FRAMESLOSTRXERRORS 0xCE
115 #define IPG_OCTETXMTOK 0xD0
116 #define IPG_MCSTOCTETXMTOK 0xD4
117 #define IPG_BCSTOCTETXMTOK 0xD8
118 #define IPG_FRAMESXMTDOK 0xDC
119 #define IPG_MCSTFRAMESXMTDOK 0xE0
120 #define IPG_FRAMESWDEFERREDXMT 0xE4
121 #define IPG_LATECOLLISIONS 0xE8
122 #define IPG_MULTICOLFRAMES 0xEC
123 #define IPG_SINGLECOLFRAMES 0xF0
124 #define IPG_BCSTFRAMESXMTDOK 0xF6
125 #define IPG_CARRIERSENSEERRORS 0xF8
126 #define IPG_MACCONTROLFRAMESXMTDOK 0xFA
127 #define IPG_FRAMESABORTXSCOLLS 0xFC
128 #define IPG_FRAMESWEXDEFERRAL 0xFE
130 /* RMON statistic register offsets. */
131 #define IPG_ETHERSTATSCOLLISIONS 0x100
132 #define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
133 #define IPG_ETHERSTATSPKTSTRANSMIT 0x108
134 #define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
135 #define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
136 #define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
137 #define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
138 #define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
139 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
140 #define IPG_ETHERSTATSCRCALIGNERRORS 0x124
141 #define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
142 #define IPG_ETHERSTATSFRAGMENTS 0x12C
143 #define IPG_ETHERSTATSJABBERS 0x130
144 #define IPG_ETHERSTATSOCTETS 0x134
145 #define IPG_ETHERSTATSPKTS 0x138
146 #define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
147 #define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
148 #define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
149 #define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
150 #define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
151 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
153 /* RMON statistic register equivalents. */
154 #define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
155 #define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
156 #define IPG_ETHERSTATSMULTICASTPKTS 0xB8
157 #define IPG_ETHERSTATSBROADCASTPKTS 0xBE
158 #define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
159 #define IPG_ETHERSTATSDROPEVENTS 0xCE
161 /* Serial EEPROM offsets */
162 #define IPG_EEPROM_CONFIGPARAM 0x00
163 #define IPG_EEPROM_ASICCTRL 0x01
164 #define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
165 #define IPG_EEPROM_SUBSYSTEMID 0x03
166 #define IPG_EEPROM_STATIONADDRESS0 0x10
167 #define IPG_EEPROM_STATIONADDRESS1 0x11
168 #define IPG_EEPROM_STATIONADDRESS2 0x12
170 /* Register & data structure bit masks */
172 /* PCI register masks. */
175 #define IPG_PIB_RSVD_MASK 0xFFFFFE01
176 #define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
177 #define IPG_PIB_IOBASEADDRIND 0x00000001
180 #define IPG_PMB_RSVD_MASK 0xFFFFFE07
181 #define IPG_PMB_MEMBASEADDRIND 0x00000001
182 #define IPG_PMB_MEMMAPTYPE 0x00000006
183 #define IPG_PMB_MEMMAPTYPE0 0x00000002
184 #define IPG_PMB_MEMMAPTYPE1 0x00000004
185 #define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
188 #define IPG_CS_RSVD_MASK 0xFFB0
189 #define IPG_CS_CAPABILITIES 0x0010
190 #define IPG_CS_66MHZCAPABLE 0x0020
191 #define IPG_CS_FASTBACK2BACK 0x0080
192 #define IPG_CS_DATAPARITYREPORTED 0x0100
193 #define IPG_CS_DEVSELTIMING 0x0600
194 #define IPG_CS_SIGNALEDTARGETABORT 0x0800
195 #define IPG_CS_RECEIVEDTARGETABORT 0x1000
196 #define IPG_CS_RECEIVEDMASTERABORT 0x2000
197 #define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
198 #define IPG_CS_DETECTEDPARITYERROR 0x8000
200 /* TFD data structure masks. */
203 #define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF
204 #define IPG_TFC_FRAMEID 0x000000000000FFFF
205 #define IPG_TFC_WORDALIGN 0x0000000000030000
206 #define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000
207 #define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000
208 #define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000
209 #define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000
210 #define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000
211 #define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000
212 #define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000
213 #define IPG_TFC_TXINDICATE 0x0000000000400000
214 #define IPG_TFC_TXDMAINDICATE 0x0000000000800000
215 #define IPG_TFC_FRAGCOUNT 0x000000000F000000
216 #define IPG_TFC_VLANTAGINSERT 0x0000000010000000
217 #define IPG_TFC_TFDDONE 0x0000000080000000
218 #define IPG_TFC_VID 0x00000FFF00000000
219 #define IPG_TFC_CFI 0x0000100000000000
220 #define IPG_TFC_USERPRIORITY 0x0000E00000000000
222 /* TFDList, FragInfo */
223 #define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
224 #define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF
225 #define IPG_TFI_FRAGLEN 0xFFFF000000000000LL
227 /* RFD data structure masks. */
230 #define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF
231 #define IPG_RFS_RXFRAMELEN 0x000000000000FFFF
232 #define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000
233 #define IPG_RFS_RXRUNTFRAME 0x0000000000020000
234 #define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000
235 #define IPG_RFS_RXFCSERROR 0x0000000000080000
236 #define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000
237 #define IPG_RFS_RXLENGTHERROR 0x0000000000200000
238 #define IPG_RFS_VLANDETECTED 0x0000000000400000
239 #define IPG_RFS_TCPDETECTED 0x0000000000800000
240 #define IPG_RFS_TCPERROR 0x0000000001000000
241 #define IPG_RFS_UDPDETECTED 0x0000000002000000
242 #define IPG_RFS_UDPERROR 0x0000000004000000
243 #define IPG_RFS_IPDETECTED 0x0000000008000000
244 #define IPG_RFS_IPERROR 0x0000000010000000
245 #define IPG_RFS_FRAMESTART 0x0000000020000000
246 #define IPG_RFS_FRAMEEND 0x0000000040000000
247 #define IPG_RFS_RFDDONE 0x0000000080000000
248 #define IPG_RFS_TCI 0x0000FFFF00000000
250 /* RFDList, FragInfo */
251 #define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
252 #define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF
253 #define IPG_RFI_FRAGLEN 0xFFFF000000000000LL
255 /* I/O Register masks. */
257 /* RMON Statistics Mask */
258 #define IPG_RZ_ALL 0x0FFFFFFF
260 /* Statistics Mask */
261 #define IPG_SM_ALL 0x0FFFFFFF
262 #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
263 #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
264 #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
265 #define IPG_SM_RXJUMBOFRAMES 0x00000008
266 #define IPG_SM_TCPCHECKSUMERRORS 0x00000010
267 #define IPG_SM_IPCHECKSUMERRORS 0x00000020
268 #define IPG_SM_UDPCHECKSUMERRORS 0x00000040
269 #define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
270 #define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
271 #define IPG_SM_INRANGELENGTHERRORS 0x00000200
272 #define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
273 #define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
274 #define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
275 #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
276 #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
277 #define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
278 #define IPG_SM_LATECOLLISIONS 0x00010000
279 #define IPG_SM_MULTICOLFRAMES 0x00020000
280 #define IPG_SM_SINGLECOLFRAMES 0x00040000
281 #define IPG_SM_TXJUMBOFRAMES 0x00080000
282 #define IPG_SM_CARRIERSENSEERRORS 0x00100000
283 #define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
284 #define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
285 #define IPG_SM_FRAMESWEXDEFERAL 0x00800000
288 #define IPG_CD_RSVD_MASK 0x0700FFFF
289 #define IPG_CD_COUNT 0x0000FFFF
290 #define IPG_CD_COUNTDOWNSPEED 0x01000000
291 #define IPG_CD_COUNTDOWNMODE 0x02000000
292 #define IPG_CD_COUNTINTENABLED 0x04000000
294 /* TxDMABurstThresh */
295 #define IPG_TB_RSVD_MASK 0xFF
297 /* TxDMAUrgentThresh */
298 #define IPG_TU_RSVD_MASK 0xFF
300 /* TxDMAPollPeriod */
301 #define IPG_TP_RSVD_MASK 0xFF
303 /* RxDMAUrgentThresh */
304 #define IPG_RU_RSVD_MASK 0xFF
306 /* RxDMAPollPeriod */
307 #define IPG_RP_RSVD_MASK 0xFF
310 #define IPG_RM_RSVD_MASK 0x3F
311 #define IPG_RM_RECEIVEUNICAST 0x01
312 #define IPG_RM_RECEIVEMULTICAST 0x02
313 #define IPG_RM_RECEIVEBROADCAST 0x04
314 #define IPG_RM_RECEIVEALLFRAMES 0x08
315 #define IPG_RM_RECEIVEMULTICASTHASH 0x10
316 #define IPG_RM_RECEIVEIPMULTICAST 0x20
318 /* PhySet JES20040127EEPROM*/
319 #define IPG_PS_MEM_LENB9B 0x01
320 #define IPG_PS_MEM_LEN9 0x02
321 #define IPG_PS_NON_COMPDET 0x04
324 #define IPG_PC_RSVD_MASK 0xFF
325 #define IPG_PC_MGMTCLK_LO 0x00
326 #define IPG_PC_MGMTCLK_HI 0x01
327 #define IPG_PC_MGMTCLK 0x01
328 #define IPG_PC_MGMTDATA 0x02
329 #define IPG_PC_MGMTDIR 0x04
330 #define IPG_PC_DUPLEX_POLARITY 0x08
331 #define IPG_PC_DUPLEX_STATUS 0x10
332 #define IPG_PC_LINK_POLARITY 0x20
333 #define IPG_PC_LINK_SPEED 0xC0
334 #define IPG_PC_LINK_SPEED_10MBPS 0x40
335 #define IPG_PC_LINK_SPEED_100MBPS 0x80
336 #define IPG_PC_LINK_SPEED_1000MBPS 0xC0
339 #define IPG_DC_RSVD_MASK 0xC07D9818
340 #define IPG_DC_RX_DMA_COMPLETE 0x00000008
341 #define IPG_DC_RX_DMA_POLL_NOW 0x00000010
342 #define IPG_DC_TX_DMA_COMPLETE 0x00000800
343 #define IPG_DC_TX_DMA_POLL_NOW 0x00001000
344 #define IPG_DC_TX_DMA_IN_PROG 0x00008000
345 #define IPG_DC_RX_EARLY_DISABLE 0x00010000
346 #define IPG_DC_MWI_DISABLE 0x00040000
347 #define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
348 #define IPG_DC_TX_BURST_LIMIT 0x00700000
349 #define IPG_DC_TARGET_ABORT 0x40000000
350 #define IPG_DC_MASTER_ABORT 0x80000000
353 #define IPG_AC_RSVD_MASK 0x07FFEFF2
354 #define IPG_AC_EXP_ROM_SIZE 0x00000002
355 #define IPG_AC_PHY_SPEED10 0x00000010
356 #define IPG_AC_PHY_SPEED100 0x00000020
357 #define IPG_AC_PHY_SPEED1000 0x00000040
358 #define IPG_AC_PHY_MEDIA 0x00000080
359 #define IPG_AC_FORCED_CFG 0x00000700
360 #define IPG_AC_D3RESETDISABLE 0x00000800
361 #define IPG_AC_SPEED_UP_MODE 0x00002000
362 #define IPG_AC_LED_MODE 0x00004000
363 #define IPG_AC_RST_OUT_POLARITY 0x00008000
364 #define IPG_AC_GLOBAL_RESET 0x00010000
365 #define IPG_AC_RX_RESET 0x00020000
366 #define IPG_AC_TX_RESET 0x00040000
367 #define IPG_AC_DMA 0x00080000
368 #define IPG_AC_FIFO 0x00100000
369 #define IPG_AC_NETWORK 0x00200000
370 #define IPG_AC_HOST 0x00400000
371 #define IPG_AC_AUTO_INIT 0x00800000
372 #define IPG_AC_RST_OUT 0x01000000
373 #define IPG_AC_INT_REQUEST 0x02000000
374 #define IPG_AC_RESET_BUSY 0x04000000
375 #define IPG_AC_LED_SPEED 0x08000000 //JES20040127EEPROM
376 #define IPG_AC_LED_MODE_BIT_1 0x20000000 //JES20040127EEPROM
379 #define IPG_EC_RSVD_MASK 0x83FF
380 #define IPG_EC_EEPROM_ADDR 0x00FF
381 #define IPG_EC_EEPROM_OPCODE 0x0300
382 #define IPG_EC_EEPROM_SUBCOMMAD 0x0000
383 #define IPG_EC_EEPROM_WRITEOPCODE 0x0100
384 #define IPG_EC_EEPROM_READOPCODE 0x0200
385 #define IPG_EC_EEPROM_ERASEOPCODE 0x0300
386 #define IPG_EC_EEPROM_BUSY 0x8000
389 #define IPG_FC_RSVD_MASK 0xC001
390 #define IPG_FC_RAM_TEST_MODE 0x0001
391 #define IPG_FC_TRANSMITTING 0x4000
392 #define IPG_FC_RECEIVING 0x8000
395 #define IPG_TS_RSVD_MASK 0xFFFF00DD
396 #define IPG_TS_TX_ERROR 0x00000001
397 #define IPG_TS_LATE_COLLISION 0x00000004
398 #define IPG_TS_TX_MAX_COLL 0x00000008
399 #define IPG_TS_TX_UNDERRUN 0x00000010
400 #define IPG_TS_TX_IND_REQD 0x00000040
401 #define IPG_TS_TX_COMPLETE 0x00000080
402 #define IPG_TS_TX_FRAMEID 0xFFFF0000
405 #define IPG_WE_WAKE_PKT_ENABLE 0x01
406 #define IPG_WE_MAGIC_PKT_ENABLE 0x02
407 #define IPG_WE_LINK_EVT_ENABLE 0x04
408 #define IPG_WE_WAKE_POLARITY 0x08
409 #define IPG_WE_WAKE_PKT_EVT 0x10
410 #define IPG_WE_MAGIC_PKT_EVT 0x20
411 #define IPG_WE_LINK_EVT 0x40
412 #define IPG_WE_WOL_ENABLE 0x80
415 #define IPG_IE_RSVD_MASK 0x1FFE
416 #define IPG_IE_HOST_ERROR 0x0002
417 #define IPG_IE_TX_COMPLETE 0x0004
418 #define IPG_IE_MAC_CTRL_FRAME 0x0008
419 #define IPG_IE_RX_COMPLETE 0x0010
420 #define IPG_IE_RX_EARLY 0x0020
421 #define IPG_IE_INT_REQUESTED 0x0040
422 #define IPG_IE_UPDATE_STATS 0x0080
423 #define IPG_IE_LINK_EVENT 0x0100
424 #define IPG_IE_TX_DMA_COMPLETE 0x0200
425 #define IPG_IE_RX_DMA_COMPLETE 0x0400
426 #define IPG_IE_RFD_LIST_END 0x0800
427 #define IPG_IE_RX_DMA_PRIORITY 0x1000
430 #define IPG_IS_RSVD_MASK 0x1FFF
431 #define IPG_IS_INTERRUPT_STATUS 0x0001
432 #define IPG_IS_HOST_ERROR 0x0002
433 #define IPG_IS_TX_COMPLETE 0x0004
434 #define IPG_IS_MAC_CTRL_FRAME 0x0008
435 #define IPG_IS_RX_COMPLETE 0x0010
436 #define IPG_IS_RX_EARLY 0x0020
437 #define IPG_IS_INT_REQUESTED 0x0040
438 #define IPG_IS_UPDATE_STATS 0x0080
439 #define IPG_IS_LINK_EVENT 0x0100
440 #define IPG_IS_TX_DMA_COMPLETE 0x0200
441 #define IPG_IS_RX_DMA_COMPLETE 0x0400
442 #define IPG_IS_RFD_LIST_END 0x0800
443 #define IPG_IS_RX_DMA_PRIORITY 0x1000
446 #define IPG_MC_RSVD_MASK 0x7FE33FA3
447 #define IPG_MC_IFS_SELECT 0x00000003
448 #define IPG_MC_IFS_4352BIT 0x00000003
449 #define IPG_MC_IFS_1792BIT 0x00000002
450 #define IPG_MC_IFS_1024BIT 0x00000001
451 #define IPG_MC_IFS_96BIT 0x00000000
452 #define IPG_MC_DUPLEX_SELECT 0x00000020
453 #define IPG_MC_DUPLEX_SELECT_FD 0x00000020
454 #define IPG_MC_DUPLEX_SELECT_HD 0x00000000
455 #define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080
456 #define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100
457 #define IPG_MC_RCV_FCS 0x00000200
458 #define IPG_MC_FIFO_LOOPBACK 0x00000400
459 #define IPG_MC_MAC_LOOPBACK 0x00000800
460 #define IPG_MC_AUTO_VLAN_TAGGING 0x00001000
461 #define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000
462 #define IPG_MC_COLLISION_DETECT 0x00010000
463 #define IPG_MC_CARRIER_SENSE 0x00020000
464 #define IPG_MC_STATISTICS_ENABLE 0x00200000
465 #define IPG_MC_STATISTICS_DISABLE 0x00400000
466 #define IPG_MC_STATISTICS_ENABLED 0x00800000
467 #define IPG_MC_TX_ENABLE 0x01000000
468 #define IPG_MC_TX_DISABLE 0x02000000
469 #define IPG_MC_TX_ENABLED 0x04000000
470 #define IPG_MC_RX_ENABLE 0x08000000
471 #define IPG_MC_RX_DISABLE 0x10000000
472 #define IPG_MC_RX_ENABLED 0x20000000
473 #define IPG_MC_PAUSED 0x40000000
479 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
480 #define IPG_APPEND_FCS_ON_TX 1
482 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
483 #define IPG_STRIP_FCS_ON_RX 1
485 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
488 #define IPG_DROP_ON_RX_ETH_ERRORS 1
490 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
493 #define IPG_INSERT_MANUAL_VLAN_TAG 0
495 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
496 #define IPG_ADD_IPCHECKSUM_ON_TX 0
498 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
499 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
501 #define IPG_ADD_TCPCHECKSUM_ON_TX 0
503 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
504 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
506 #define IPG_ADD_UDPCHECKSUM_ON_TX 0
508 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
509 * constants as desired.
511 #define IPG_MANUAL_VLAN_VID 0xABC
512 #define IPG_MANUAL_VLAN_CFI 0x1
513 #define IPG_MANUAL_VLAN_USERPRIORITY 0x5
515 #define IPG_IO_REG_RANGE 0xFF
516 #define IPG_MEM_REG_RANGE 0x154
517 #define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
518 #define IPG_NIC_PHY_ADDRESS 0x01
519 #define IPG_DMALIST_ALIGN_PAD 0x07
520 #define IPG_MULTICAST_HASHTABLE_SIZE 0x40
522 /* Number of miliseconds to wait after issuing a software reset.
523 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
525 #define IPG_AC_RESETWAIT 0x05
527 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
528 #define IPG_AC_RESET_TIMEOUT 0x0A
530 /* Minimum number of nanoseconds used to toggle MDC clock during
531 * MII/GMII register access.
533 #define IPG_PC_PHYCTRLWAIT_NS 200
535 #define IPG_TFDLIST_LENGTH 0x100
537 /* Number of frames between TxDMAComplete interrupt.
538 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
540 #define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
544 # ifdef JUMBO_FRAME_SIZE_2K
545 # define JUMBO_FRAME_SIZE 2048
546 # define __IPG_RXFRAG_SIZE 2048
548 # ifdef JUMBO_FRAME_SIZE_3K
549 # define JUMBO_FRAME_SIZE 3072
550 # define __IPG_RXFRAG_SIZE 3072
552 # ifdef JUMBO_FRAME_SIZE_4K
553 # define JUMBO_FRAME_SIZE 4096
554 # define __IPG_RXFRAG_SIZE 4088
556 # ifdef JUMBO_FRAME_SIZE_5K
557 # define JUMBO_FRAME_SIZE 5120
558 # define __IPG_RXFRAG_SIZE 4088
560 # ifdef JUMBO_FRAME_SIZE_6K
561 # define JUMBO_FRAME_SIZE 6144
562 # define __IPG_RXFRAG_SIZE 4088
564 # ifdef JUMBO_FRAME_SIZE_7K
565 # define JUMBO_FRAME_SIZE 7168
566 # define __IPG_RXFRAG_SIZE 4088
568 # ifdef JUMBO_FRAME_SIZE_8K
569 # define JUMBO_FRAME_SIZE 8192
570 # define __IPG_RXFRAG_SIZE 4088
572 # ifdef JUMBO_FRAME_SIZE_9K
573 # define JUMBO_FRAME_SIZE 9216
574 # define __IPG_RXFRAG_SIZE 4088
576 # ifdef JUMBO_FRAME_SIZE_10K
577 # define JUMBO_FRAME_SIZE 10240
578 # define __IPG_RXFRAG_SIZE 4088
580 # define JUMBO_FRAME_SIZE 4096
592 /* Size of allocated received buffers. Nominally 0x0600.
593 * Define larger if expecting jumbo frames.
596 //IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash
597 #define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
600 /* Size of allocated received buffers. Nominally 0x0600.
601 * Define larger if expecting jumbo frames.
605 #define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
606 #define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
608 #define IPG_RXFRAG_SIZE 0x0600
609 #define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
612 /* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
614 #define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
616 #define IPG_MAX_RXFRAME_SIZE 0x0600
619 #define IPG_RFDLIST_LENGTH 0x100
621 /* Maximum number of RFDs to process per interrupt.
622 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
624 #define IPG_MAXRFDPROCESS_COUNT 0x80
626 /* Minimum margin between last freed RFD, and current RFD.
627 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
629 #define IPG_MINUSEDRFDSTOFREE 0x80
631 /* specify the jumbo frame maximum size
632 * per unit is 0x600 (the RxBuffer size that one RFD can carry)
634 #define MAX_JUMBOSIZE 0x8 // max is 12K
636 /* Key register values loaded at driver start up. */
638 /* TXDMAPollPeriod is specified in 320ns increments.
641 * ---------------------
647 #define IPG_TXDMAPOLLPERIOD_VALUE 0x26
649 /* TxDMAUrgentThresh specifies the minimum amount of
650 * data in the transmit FIFO before asserting an
651 * urgent transmit DMA request.
653 * Value Min TxFIFO occupied space before urgent TX request
654 * ---------------------------------------------------------------
655 * 0x00-0x04 128 bytes (1024 bits)
656 * 0x27 1248 bytes (~10000 bits)
657 * 0x30 1536 bytes (12288 bits)
658 * 0xFF 8192 bytes (65535 bits)
660 #define IPG_TXDMAURGENTTHRESH_VALUE 0x04
662 /* TxDMABurstThresh specifies the minimum amount of
663 * free space in the transmit FIFO before asserting an
664 * transmit DMA request.
666 * Value Min TxFIFO free space before TX request
667 * ----------------------------------------------------
668 * 0x00-0x08 256 bytes
672 #define IPG_TXDMABURSTTHRESH_VALUE 0x30
674 /* RXDMAPollPeriod is specified in 320ns increments.
677 * ---------------------
683 #define IPG_RXDMAPOLLPERIOD_VALUE 0x01
685 /* RxDMAUrgentThresh specifies the minimum amount of
686 * free space within the receive FIFO before asserting
687 * a urgent receive DMA request.
689 * Value Min RxFIFO free space before urgent RX request
690 * ---------------------------------------------------------------
691 * 0x00-0x04 128 bytes (1024 bits)
692 * 0x27 1248 bytes (~10000 bits)
693 * 0x30 1536 bytes (12288 bits)
694 * 0xFF 8192 bytes (65535 bits)
696 #define IPG_RXDMAURGENTTHRESH_VALUE 0x30
698 /* RxDMABurstThresh specifies the minimum amount of
699 * occupied space within the receive FIFO before asserting
700 * a receive DMA request.
702 * Value Min TxFIFO free space before TX request
703 * ----------------------------------------------------
704 * 0x00-0x08 256 bytes
708 #define IPG_RXDMABURSTTHRESH_VALUE 0x30
710 /* FlowOnThresh specifies the maximum amount of occupied
711 * space in the receive FIFO before a PAUSE frame with
712 * maximum pause time transmitted.
714 * Value Max RxFIFO occupied space before PAUSE
715 * ---------------------------------------------------
717 * 0x0740 29,696 bytes
718 * 0x07FF 32,752 bytes
720 #define IPG_FLOWONTHRESH_VALUE 0x0740
722 /* FlowOffThresh specifies the minimum amount of occupied
723 * space in the receive FIFO before a PAUSE frame with
724 * zero pause time is transmitted.
726 * Value Max RxFIFO occupied space before PAUSE
727 * ---------------------------------------------------
730 * 0x07FF 32,752 bytes
732 #define IPG_FLOWOFFTHRESH_VALUE 0x00BF
735 * Miscellaneous macros.
738 /* Marco for printing debug statements.
739 # define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " ## args) */
741 # define IPG_DEBUG_MSG(args...)
742 # define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
743 # define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
744 # define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
746 # define IPG_DEBUG_MSG(args...)
747 # define IPG_DDEBUG_MSG(args...)
748 # define IPG_DUMPRFDLIST(args)
749 # define IPG_DUMPTFDLIST(args)
753 * End miscellaneous macros.
756 /* Transmit Frame Descriptor. The IPG supports 15 fragments,
757 * however Linux requires only a single fragment. Note, each
758 * TFD field is 64 bits wide.
766 /* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
779 /* Structure of IPG NIC specific data. */
780 struct ipg_nic_private {
781 void __iomem *ioaddr;
786 struct sk_buff *TxBuff[IPG_TFDLIST_LENGTH];
787 struct sk_buff *RxBuff[IPG_RFDLIST_LENGTH];
788 unsigned int tx_current;
789 unsigned int tx_dirty;
790 unsigned int rx_current;
791 unsigned int rx_dirty;
792 // Add by Grace 2005/05/19
796 unsigned int rx_buf_sz;
797 struct pci_dev *pdev;
798 struct net_device *dev;
799 struct net_device_stats stats;
803 /*Jesse20040128EEPROM_VALUE */
805 u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */
807 struct mutex mii_mutex;
808 struct mii_if_info mii_if;
812 int RFDListCheckedCount;
813 int EmptyRFDListCount;
815 struct delayed_work task;
818 #endif /* __LINUX_IPG_H */