git.oblomov.eu Git - linux-2.6/blob - drivers/crypto/hifn_795x.c

   1 /*
   2  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/slab.h>
  27 #include <linux/delay.h>
  28 #include <linux/mm.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/highmem.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/ktime.h>
  36
  37 #include <crypto/algapi.h>
  38 #include <crypto/des.h>
  39
  40 #include <asm/kmap_types.h>
  41
  42 #undef dprintk
  43
  44 #define HIFN_TEST
  45 //#define HIFN_DEBUG
  46
  47 #ifdef HIFN_DEBUG
  48 #define dprintk(f, a...)        printk(f, ##a)
  49 #else
  50 #define dprintk(f, a...)        do {} while (0)
  51 #endif
  52
  53 static char hifn_pll_ref[sizeof("extNNN")] = "ext";
  54 module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
  55 MODULE_PARM_DESC(hifn_pll_ref,
  56                  "PLL reference clock (pci[freq] or ext[freq], default ext)");
  57
  58 static atomic_t hifn_dev_number;
  59
  60 #define ACRYPTO_OP_DECRYPT      0
  61 #define ACRYPTO_OP_ENCRYPT      1
  62 #define ACRYPTO_OP_HMAC         2
  63 #define ACRYPTO_OP_RNG          3
  64
  65 #define ACRYPTO_MODE_ECB                0
  66 #define ACRYPTO_MODE_CBC                1
  67 #define ACRYPTO_MODE_CFB                2
  68 #define ACRYPTO_MODE_OFB                3
  69
  70 #define ACRYPTO_TYPE_AES_128    0
  71 #define ACRYPTO_TYPE_AES_192    1
  72 #define ACRYPTO_TYPE_AES_256    2
  73 #define ACRYPTO_TYPE_3DES       3
  74 #define ACRYPTO_TYPE_DES        4
  75
  76 #define PCI_VENDOR_ID_HIFN              0x13A3
  77 #define PCI_DEVICE_ID_HIFN_7955         0x0020
  78 #define PCI_DEVICE_ID_HIFN_7956         0x001d
  79
  80 /* I/O region sizes */
  81
  82 #define HIFN_BAR0_SIZE                  0x1000
  83 #define HIFN_BAR1_SIZE                  0x2000
  84 #define HIFN_BAR2_SIZE                  0x8000
  85
  86 /* DMA registres */
  87
  88 #define HIFN_DMA_CRA                    0x0C    /* DMA Command Ring Address */
  89 #define HIFN_DMA_SDRA                   0x1C    /* DMA Source Data Ring Address */
  90 #define HIFN_DMA_RRA                    0x2C    /* DMA Result Ring Address */
  91 #define HIFN_DMA_DDRA                   0x3C    /* DMA Destination Data Ring Address */
  92 #define HIFN_DMA_STCTL                  0x40    /* DMA Status and Control */
  93 #define HIFN_DMA_INTREN                 0x44    /* DMA Interrupt Enable */
  94 #define HIFN_DMA_CFG1                   0x48    /* DMA Configuration #1 */
  95 #define HIFN_DMA_CFG2                   0x6C    /* DMA Configuration #2 */
  96 #define HIFN_CHIP_ID                    0x98    /* Chip ID */
  97
  98 /*
  99  * Processing Unit Registers (offset from BASEREG0)
 100  */
 101 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
 102 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
 103 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
 104 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
 105 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
 106 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
 107 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
 108 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
 109 #define HIFN_0_SPACESIZE        0x20    /* Register space size */
 110
 111 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
 112 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
 113 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
 114 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
 115 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
 116 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
 117
 118 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
 119 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
 120 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
 121 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 122 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 123 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
 124 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
 125 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 126 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 127 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 128 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 129
 130 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 131 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 132 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 133 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 134 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 135 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 136 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 137 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 138 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 139 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 140 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 141 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 142 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 143 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 144 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 145 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 146 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 147 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 148 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 149 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 150 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 151 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 152 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 153 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 154
 155 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 156 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 157 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 158 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 159 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 160 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 161 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 162 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 163 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 164 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 165 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 166
 167 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 168 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 169 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 170 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 171 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 172 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 173 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 174 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 175 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 176 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 177 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 178 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 179 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 180 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 181 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 182 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 183 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 184 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 185
 186 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 187 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 188 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 189
 190 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 191 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as 1 */
 192
 193 /*
 194  * DMA Interface Registers (offset from BASEREG1)
 195  */
 196 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 197 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 198 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 199 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 200 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 201 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 202 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 203 #define HIFN_1_PLL              0x4c    /* 795x: PLL config */
 204 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 205 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 206 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 207 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 208 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 209 #define HIFN_1_REVID            0x98    /* Revision ID */
 210 #define HIFN_1_UNLOCK_SECRET1   0xf4
 211 #define HIFN_1_UNLOCK_SECRET2   0xfc
 212 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 213 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 214 #define HIFN_1_PUB_OPLEN        0x304   /* Public Operand Length */
 215 #define HIFN_1_PUB_OP           0x308   /* Public Operand */
 216 #define HIFN_1_PUB_STATUS       0x30c   /* Public Status */
 217 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 218 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 219 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 220 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 221 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 222
 223 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 224 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 225 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 226 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 227 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 228 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 229 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 230 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 231 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 232 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 233 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 234 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 235 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 236 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 237 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 238 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 239 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 240 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 241 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 242 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 243 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 244 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 245 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 246 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 247 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 248 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 249 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 250 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 251 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 252 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 253 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 254 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 255 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 256 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 257 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 258 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 259 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 260 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 261 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 262
 263 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 264 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 265 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 266 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 267 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 268 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 269 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 270 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 271 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 272 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 273 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 274 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 275 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 276 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 277 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 278 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 279 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 280 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 281 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 282 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 283 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 284 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 285 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 286
 287 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 288 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 289 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 290 #define HIFN_DMACNFG_UNLOCK     0x00000800
 291 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 292 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 293 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 294 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 295 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 296
 297 /* PLL configuration register */
 298 #define HIFN_PLL_REF_CLK_HBI    0x00000000      /* HBI reference clock */
 299 #define HIFN_PLL_REF_CLK_PLL    0x00000001      /* PLL reference clock */
 300 #define HIFN_PLL_BP             0x00000002      /* Reference clock bypass */
 301 #define HIFN_PLL_PK_CLK_HBI     0x00000000      /* PK engine HBI clock */
 302 #define HIFN_PLL_PK_CLK_PLL     0x00000008      /* PK engine PLL clock */
 303 #define HIFN_PLL_PE_CLK_HBI     0x00000000      /* PE engine HBI clock */
 304 #define HIFN_PLL_PE_CLK_PLL     0x00000010      /* PE engine PLL clock */
 305 #define HIFN_PLL_RESERVED_1     0x00000400      /* Reserved bit, must be 1 */
 306 #define HIFN_PLL_ND_SHIFT       11              /* Clock multiplier shift */
 307 #define HIFN_PLL_ND_MULT_2      0x00000000      /* PLL clock multiplier 2 */
 308 #define HIFN_PLL_ND_MULT_4      0x00000800      /* PLL clock multiplier 4 */
 309 #define HIFN_PLL_ND_MULT_6      0x00001000      /* PLL clock multiplier 6 */
 310 #define HIFN_PLL_ND_MULT_8      0x00001800      /* PLL clock multiplier 8 */
 311 #define HIFN_PLL_ND_MULT_10     0x00002000      /* PLL clock multiplier 10 */
 312 #define HIFN_PLL_ND_MULT_12     0x00002800      /* PLL clock multiplier 12 */
 313 #define HIFN_PLL_IS_1_8         0x00000000      /* charge pump (mult. 1-8) */
 314 #define HIFN_PLL_IS_9_12        0x00010000      /* charge pump (mult. 9-12) */
 315
 316 #define HIFN_PLL_FCK_MAX        266             /* Maximum PLL frequency */
 317
 318 /* Public key reset register (HIFN_1_PUB_RESET) */
 319 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 320
 321 /* Public base address register (HIFN_1_PUB_BASE) */
 322 #define HIFN_PUBBASE_ADDR       0x00003fff      /* base address */
 323
 324 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 325 #define HIFN_PUBOPLEN_MOD_M     0x0000007f      /* modulus length mask */
 326 #define HIFN_PUBOPLEN_MOD_S     0               /* modulus length shift */
 327 #define HIFN_PUBOPLEN_EXP_M     0x0003ff80      /* exponent length mask */
 328 #define HIFN_PUBOPLEN_EXP_S     7               /* exponent lenght shift */
 329 #define HIFN_PUBOPLEN_RED_M     0x003c0000      /* reducend length mask */
 330 #define HIFN_PUBOPLEN_RED_S     18              /* reducend length shift */
 331
 332 /* Public operation register (HIFN_1_PUB_OP) */
 333 #define HIFN_PUBOP_AOFFSET_M    0x0000007f      /* A offset mask */
 334 #define HIFN_PUBOP_AOFFSET_S    0               /* A offset shift */
 335 #define HIFN_PUBOP_BOFFSET_M    0x00000f80      /* B offset mask */
 336 #define HIFN_PUBOP_BOFFSET_S    7               /* B offset shift */
 337 #define HIFN_PUBOP_MOFFSET_M    0x0003f000      /* M offset mask */
 338 #define HIFN_PUBOP_MOFFSET_S    12              /* M offset shift */
 339 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 340 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 341 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 342 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 343 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 344 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 345 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 346 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 347 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 348 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 349 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 350 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 351 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular RED */
 352 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular EXP */
 353
 354 /* Public status register (HIFN_1_PUB_STATUS) */
 355 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 356 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 357
 358 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 359 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 360
 361 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 362 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 363
 364 #define HIFN_NAMESIZE                   32
 365 #define HIFN_MAX_RESULT_ORDER           5
 366
 367 #define HIFN_D_CMD_RSIZE                24*4
 368 #define HIFN_D_SRC_RSIZE                80*4
 369 #define HIFN_D_DST_RSIZE                80*4
 370 #define HIFN_D_RES_RSIZE                24*4
 371
 372 #define HIFN_D_DST_DALIGN               4
 373
 374 #define HIFN_QUEUE_LENGTH               HIFN_D_CMD_RSIZE-1
 375
 376 #define AES_MIN_KEY_SIZE                16
 377 #define AES_MAX_KEY_SIZE                32
 378
 379 #define HIFN_DES_KEY_LENGTH             8
 380 #define HIFN_3DES_KEY_LENGTH            24
 381 #define HIFN_MAX_CRYPT_KEY_LENGTH       AES_MAX_KEY_SIZE
 382 #define HIFN_IV_LENGTH                  8
 383 #define HIFN_AES_IV_LENGTH              16
 384 #define HIFN_MAX_IV_LENGTH              HIFN_AES_IV_LENGTH
 385
 386 #define HIFN_MAC_KEY_LENGTH             64
 387 #define HIFN_MD5_LENGTH                 16
 388 #define HIFN_SHA1_LENGTH                20
 389 #define HIFN_MAC_TRUNC_LENGTH           12
 390
 391 #define HIFN_MAX_COMMAND                (8 + 8 + 8 + 64 + 260)
 392 #define HIFN_MAX_RESULT                 (8 + 4 + 4 + 20 + 4)
 393 #define HIFN_USED_RESULT                12
 394
 395 struct hifn_desc
 396 {
 397         volatile __le32         l;
 398         volatile __le32         p;
 399 };
 400
 401 struct hifn_dma {
 402         struct hifn_desc        cmdr[HIFN_D_CMD_RSIZE+1];
 403         struct hifn_desc        srcr[HIFN_D_SRC_RSIZE+1];
 404         struct hifn_desc        dstr[HIFN_D_DST_RSIZE+1];
 405         struct hifn_desc        resr[HIFN_D_RES_RSIZE+1];
 406
 407         u8                      command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
 408         u8                      result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
 409
 410         u64                     test_src, test_dst;
 411
 412         /*
 413          *  Our current positions for insertion and removal from the descriptor
 414          *  rings.
 415          */
 416         volatile int            cmdi, srci, dsti, resi;
 417         volatile int            cmdu, srcu, dstu, resu;
 418         int                     cmdk, srck, dstk, resk;
 419 };
 420
 421 #define HIFN_FLAG_CMD_BUSY      (1<<0)
 422 #define HIFN_FLAG_SRC_BUSY      (1<<1)
 423 #define HIFN_FLAG_DST_BUSY      (1<<2)
 424 #define HIFN_FLAG_RES_BUSY      (1<<3)
 425 #define HIFN_FLAG_OLD_KEY       (1<<4)
 426
 427 #define HIFN_DEFAULT_ACTIVE_NUM 5
 428
 429 struct hifn_device
 430 {
 431         char                    name[HIFN_NAMESIZE];
 432
 433         int                     irq;
 434
 435         struct pci_dev          *pdev;
 436         void __iomem            *bar[3];
 437
 438         unsigned long           result_mem;
 439         dma_addr_t              dst;
 440
 441         void                    *desc_virt;
 442         dma_addr_t              desc_dma;
 443
 444         u32                     dmareg;
 445
 446         void                    *sa[HIFN_D_RES_RSIZE];
 447
 448         spinlock_t              lock;
 449
 450         void                    *priv;
 451
 452         u32                     flags;
 453         int                     active, started;
 454         struct delayed_work     work;
 455         unsigned long           reset;
 456         unsigned long           success;
 457         unsigned long           prev_success;
 458
 459         u8                      snum;
 460
 461         struct tasklet_struct   tasklet;
 462
 463         struct crypto_queue     queue;
 464         struct list_head        alg_list;
 465
 466         unsigned int            pk_clk_freq;
 467
 468 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 469         unsigned int            rng_wait_time;
 470         ktime_t                 rngtime;
 471         struct hwrng            rng;
 472 #endif
 473 };
 474
 475 #define HIFN_D_LENGTH                   0x0000ffff
 476 #define HIFN_D_NOINVALID                0x01000000
 477 #define HIFN_D_MASKDONEIRQ              0x02000000
 478 #define HIFN_D_DESTOVER                 0x04000000
 479 #define HIFN_D_OVER                     0x08000000
 480 #define HIFN_D_LAST                     0x20000000
 481 #define HIFN_D_JUMP                     0x40000000
 482 #define HIFN_D_VALID                    0x80000000
 483
 484 struct hifn_base_command
 485 {
 486         volatile __le16         masks;
 487         volatile __le16         session_num;
 488         volatile __le16         total_source_count;
 489         volatile __le16         total_dest_count;
 490 };
 491
 492 #define HIFN_BASE_CMD_COMP              0x0100  /* enable compression engine */
 493 #define HIFN_BASE_CMD_PAD               0x0200  /* enable padding engine */
 494 #define HIFN_BASE_CMD_MAC               0x0400  /* enable MAC engine */
 495 #define HIFN_BASE_CMD_CRYPT             0x0800  /* enable crypt engine */
 496 #define HIFN_BASE_CMD_DECODE            0x2000
 497 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 498 #define HIFN_BASE_CMD_SRCLEN_S          14
 499 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 500 #define HIFN_BASE_CMD_DSTLEN_S          12
 501 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 502 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 503
 504 /*
 505  * Structure to help build up the command data structure.
 506  */
 507 struct hifn_crypt_command
 508 {
 509         volatile __le16                 masks;
 510         volatile __le16                 header_skip;
 511         volatile __le16                 source_count;
 512         volatile __le16                 reserved;
 513 };
 514
 515 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 516 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 517 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 518 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 519 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 520 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 521 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 522 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 523 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 524 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 525 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 526 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 527 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*  128 bit */
 528 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*  192 bit */
 529 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*  256 bit */
 530 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 531 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 532 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 533 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 534
 535 /*
 536  * Structure to help build up the command data structure.
 537  */
 538 struct hifn_mac_command
 539 {
 540         volatile __le16         masks;
 541         volatile __le16         header_skip;
 542         volatile __le16         source_count;
 543         volatile __le16         reserved;
 544 };
 545
 546 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 547 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 548 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 549 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 550 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 551 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 552 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 553 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 554 #define HIFN_MAC_CMD_TRUNC              0x0010
 555 #define HIFN_MAC_CMD_RESULT             0x0020
 556 #define HIFN_MAC_CMD_APPEND             0x0040
 557 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 558 #define HIFN_MAC_CMD_SRCLEN_S           14
 559
 560 /*
 561  * MAC POS IPsec initiates authentication after encryption on encodes
 562  * and before decryption on decodes.
 563  */
 564 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 565 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 566
 567 struct hifn_comp_command
 568 {
 569         volatile __le16         masks;
 570         volatile __le16         header_skip;
 571         volatile __le16         source_count;
 572         volatile __le16         reserved;
 573 };
 574
 575 #define HIFN_COMP_CMD_SRCLEN_M          0xc000
 576 #define HIFN_COMP_CMD_SRCLEN_S          14
 577 #define HIFN_COMP_CMD_ONE               0x0100  /* must be one */
 578 #define HIFN_COMP_CMD_CLEARHIST         0x0010  /* clear history */
 579 #define HIFN_COMP_CMD_UPDATEHIST        0x0008  /* update history */
 580 #define HIFN_COMP_CMD_LZS_STRIP0        0x0004  /* LZS: strip zero */
 581 #define HIFN_COMP_CMD_MPPC_RESTART      0x0004  /* MPPC: restart */
 582 #define HIFN_COMP_CMD_ALG_MASK          0x0001  /* compression mode: */
 583 #define HIFN_COMP_CMD_ALG_MPPC          0x0001  /*   MPPC */
 584 #define HIFN_COMP_CMD_ALG_LZS           0x0000  /*   LZS */
 585
 586 struct hifn_base_result
 587 {
 588         volatile __le16         flags;
 589         volatile __le16         session;
 590         volatile __le16         src_cnt;                /* 15:0 of source count */
 591         volatile __le16         dst_cnt;                /* 15:0 of dest count */
 592 };
 593
 594 #define HIFN_BASE_RES_DSTOVERRUN        0x0200  /* destination overrun */
 595 #define HIFN_BASE_RES_SRCLEN_M          0xc000  /* 17:16 of source count */
 596 #define HIFN_BASE_RES_SRCLEN_S          14
 597 #define HIFN_BASE_RES_DSTLEN_M          0x3000  /* 17:16 of dest count */
 598 #define HIFN_BASE_RES_DSTLEN_S          12
 599
 600 struct hifn_comp_result
 601 {
 602         volatile __le16         flags;
 603         volatile __le16         crc;
 604 };
 605
 606 #define HIFN_COMP_RES_LCB_M             0xff00  /* longitudinal check byte */
 607 #define HIFN_COMP_RES_LCB_S             8
 608 #define HIFN_COMP_RES_RESTART           0x0004  /* MPPC: restart */
 609 #define HIFN_COMP_RES_ENDMARKER         0x0002  /* LZS: end marker seen */
 610 #define HIFN_COMP_RES_SRC_NOTZERO       0x0001  /* source expired */
 611
 612 struct hifn_mac_result
 613 {
 614         volatile __le16         flags;
 615         volatile __le16         reserved;
 616         /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
 617 };
 618
 619 #define HIFN_MAC_RES_MISCOMPARE         0x0002  /* compare failed */
 620 #define HIFN_MAC_RES_SRC_NOTZERO        0x0001  /* source expired */
 621
 622 struct hifn_crypt_result
 623 {
 624         volatile __le16         flags;
 625         volatile __le16         reserved;
 626 };
 627
 628 #define HIFN_CRYPT_RES_SRC_NOTZERO      0x0001  /* source expired */
 629
 630 #ifndef HIFN_POLL_FREQUENCY
 631 #define HIFN_POLL_FREQUENCY     0x1
 632 #endif
 633
 634 #ifndef HIFN_POLL_SCALAR
 635 #define HIFN_POLL_SCALAR        0x0
 636 #endif
 637
 638 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 639 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 640
 641 struct hifn_crypto_alg
 642 {
 643         struct list_head        entry;
 644         struct crypto_alg       alg;
 645         struct hifn_device      *dev;
 646 };
 647
 648 #define ASYNC_SCATTERLIST_CACHE 16
 649
 650 #define ASYNC_FLAGS_MISALIGNED  (1<<0)
 651
 652 struct ablkcipher_walk
 653 {
 654         struct scatterlist      cache[ASYNC_SCATTERLIST_CACHE];
 655         u32                     flags;
 656         int                     num;
 657 };
 658
 659 struct hifn_context
 660 {
 661         u8                      key[HIFN_MAX_CRYPT_KEY_LENGTH], *iv;
 662         struct hifn_device      *dev;
 663         unsigned int            keysize, ivsize;
 664         u8                      op, type, mode, unused;
 665         struct ablkcipher_walk  walk;
 666         atomic_t                sg_num;
 667 };
 668
 669 #define crypto_alg_to_hifn(a)   container_of(a, struct hifn_crypto_alg, alg)
 670
 671 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
 672 {
 673         u32 ret;
 674
 675         ret = readl(dev->bar[0] + reg);
 676
 677         return ret;
 678 }
 679
 680 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
 681 {
 682         u32 ret;
 683
 684         ret = readl(dev->bar[1] + reg);
 685
 686         return ret;
 687 }
 688
 689 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
 690 {
 691         writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
 692 }
 693
 694 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
 695 {
 696         writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
 697 }
 698
 699 static void hifn_wait_puc(struct hifn_device *dev)
 700 {
 701         int i;
 702         u32 ret;
 703
 704         for (i=10000; i > 0; --i) {
 705                 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
 706                 if (!(ret & HIFN_PUCTRL_RESET))
 707                         break;
 708
 709                 udelay(1);
 710         }
 711
 712         if (!i)
 713                 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
 714 }
 715
 716 static void hifn_reset_puc(struct hifn_device *dev)
 717 {
 718         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 719         hifn_wait_puc(dev);
 720 }
 721
 722 static void hifn_stop_device(struct hifn_device *dev)
 723 {
 724         hifn_write_1(dev, HIFN_1_DMA_CSR,
 725                 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 726                 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
 727         hifn_write_0(dev, HIFN_0_PUIER, 0);
 728         hifn_write_1(dev, HIFN_1_DMA_IER, 0);
 729 }
 730
 731 static void hifn_reset_dma(struct hifn_device *dev, int full)
 732 {
 733         hifn_stop_device(dev);
 734
 735         /*
 736          * Setting poll frequency and others to 0.
 737          */
 738         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 739                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 740         mdelay(1);
 741
 742         /*
 743          * Reset DMA.
 744          */
 745         if (full) {
 746                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 747                 mdelay(1);
 748         } else {
 749                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
 750                                 HIFN_DMACNFG_MSTRESET);
 751                 hifn_reset_puc(dev);
 752         }
 753
 754         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 755                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 756
 757         hifn_reset_puc(dev);
 758 }
 759
 760 static u32 hifn_next_signature(u_int32_t a, u_int cnt)
 761 {
 762         int i;
 763         u32 v;
 764
 765         for (i = 0; i < cnt; i++) {
 766
 767                 /* get the parity */
 768                 v = a & 0x80080125;
 769                 v ^= v >> 16;
 770                 v ^= v >> 8;
 771                 v ^= v >> 4;
 772                 v ^= v >> 2;
 773                 v ^= v >> 1;
 774
 775                 a = (v & 1) ^ (a << 1);
 776         }
 777
 778         return a;
 779 }
 780
 781 static struct pci2id {
 782         u_short         pci_vendor;
 783         u_short         pci_prod;
 784         char            card_id[13];
 785 } pci2id[] = {
 786         {
 787                 PCI_VENDOR_ID_HIFN,
 788                 PCI_DEVICE_ID_HIFN_7955,
 789                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 790                   0x00, 0x00, 0x00, 0x00, 0x00 }
 791         },
 792         {
 793                 PCI_VENDOR_ID_HIFN,
 794                 PCI_DEVICE_ID_HIFN_7956,
 795                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 796                   0x00, 0x00, 0x00, 0x00, 0x00 }
 797         }
 798 };
 799
 800 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 801 static int hifn_rng_data_present(struct hwrng *rng, int wait)
 802 {
 803         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 804         s64 nsec;
 805
 806         nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
 807         nsec -= dev->rng_wait_time;
 808         if (nsec <= 0)
 809                 return 1;
 810         if (!wait)
 811                 return 0;
 812         ndelay(nsec);
 813         return 1;
 814 }
 815
 816 static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
 817 {
 818         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 819
 820         *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
 821         dev->rngtime = ktime_get();
 822         return 4;
 823 }
 824
 825 static int hifn_register_rng(struct hifn_device *dev)
 826 {
 827         /*
 828          * We must wait at least 256 Pk_clk cycles between two reads of the rng.
 829          */
 830         dev->rng_wait_time      = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) *
 831                                   256;
 832
 833         dev->rng.name           = dev->name;
 834         dev->rng.data_present   = hifn_rng_data_present,
 835         dev->rng.data_read      = hifn_rng_data_read,
 836         dev->rng.priv           = (unsigned long)dev;
 837
 838         return hwrng_register(&dev->rng);
 839 }
 840
 841 static void hifn_unregister_rng(struct hifn_device *dev)
 842 {
 843         hwrng_unregister(&dev->rng);
 844 }
 845 #else
 846 #define hifn_register_rng(dev)          0
 847 #define hifn_unregister_rng(dev)
 848 #endif
 849
 850 static int hifn_init_pubrng(struct hifn_device *dev)
 851 {
 852         int i;
 853
 854         hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
 855                         HIFN_PUBRST_RESET);
 856
 857         for (i=100; i > 0; --i) {
 858                 mdelay(1);
 859
 860                 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
 861                         break;
 862         }
 863
 864         if (!i)
 865                 dprintk("Chip %s: Failed to initialise public key engine.\n",
 866                                 dev->name);
 867         else {
 868                 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 869                 dev->dmareg |= HIFN_DMAIER_PUBDONE;
 870                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 871
 872                 dprintk("Chip %s: Public key engine has been sucessfully "
 873                                 "initialised.\n", dev->name);
 874         }
 875
 876         /*
 877          * Enable RNG engine.
 878          */
 879
 880         hifn_write_1(dev, HIFN_1_RNG_CONFIG,
 881                         hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
 882         dprintk("Chip %s: RNG engine has been successfully initialised.\n",
 883                         dev->name);
 884
 885 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 886         /* First value must be discarded */
 887         hifn_read_1(dev, HIFN_1_RNG_DATA);
 888         dev->rngtime = ktime_get();
 889 #endif
 890         return 0;
 891 }
 892
 893 static int hifn_enable_crypto(struct hifn_device *dev)
 894 {
 895         u32 dmacfg, addr;
 896         char *offtbl = NULL;
 897         int i;
 898
 899         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
 900                 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
 901                                 pci2id[i].pci_prod == dev->pdev->device) {
 902                         offtbl = pci2id[i].card_id;
 903                         break;
 904                 }
 905         }
 906
 907         if (offtbl == NULL) {
 908                 dprintk("Chip %s: Unknown card!\n", dev->name);
 909                 return -ENODEV;
 910         }
 911
 912         dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
 913
 914         hifn_write_1(dev, HIFN_1_DMA_CNFG,
 915                         HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
 916                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 917         mdelay(1);
 918         addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
 919         mdelay(1);
 920         hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
 921         mdelay(1);
 922
 923         for (i=0; i<12; ++i) {
 924                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 925                 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
 926
 927                 mdelay(1);
 928         }
 929         hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
 930
 931         dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
 932
 933         return 0;
 934 }
 935
 936 static void hifn_init_dma(struct hifn_device *dev)
 937 {
 938         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
 939         u32 dptr = dev->desc_dma;
 940         int i;
 941
 942         for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
 943                 dma->cmdr[i].p = __cpu_to_le32(dptr +
 944                                 offsetof(struct hifn_dma, command_bufs[i][0]));
 945         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
 946                 dma->resr[i].p = __cpu_to_le32(dptr +
 947                                 offsetof(struct hifn_dma, result_bufs[i][0]));
 948
 949         /*
 950          * Setup LAST descriptors.
 951          */
 952         dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
 953                         offsetof(struct hifn_dma, cmdr[0]));
 954         dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
 955                         offsetof(struct hifn_dma, srcr[0]));
 956         dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
 957                         offsetof(struct hifn_dma, dstr[0]));
 958         dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
 959                         offsetof(struct hifn_dma, resr[0]));
 960
 961         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
 962         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
 963         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
 964 }
 965
 966 /*
 967  * Initialize the PLL. We need to know the frequency of the reference clock
 968  * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
 969  * allows us to operate without the risk of overclocking the chip. If it
 970  * actually uses 33MHz, the chip will operate at half the speed, this can be
 971  * overriden by specifying the frequency as module parameter (pci33).
 972  *
 973  * Unfortunately the PCI clock is not very suitable since the HIFN needs a
 974  * stable clock and the PCI clock frequency may vary, so the default is the
 975  * external clock. There is no way to find out its frequency, we default to
 976  * 66MHz since according to Mike Ham of HiFn, almost every board in existence
 977  * has an external crystal populated at 66MHz.
 978  */
 979 static void hifn_init_pll(struct hifn_device *dev)
 980 {
 981         unsigned int freq, m;
 982         u32 pllcfg;
 983
 984         pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
 985
 986         if (strncmp(hifn_pll_ref, "ext", 3) == 0)
 987                 pllcfg |= HIFN_PLL_REF_CLK_PLL;
 988         else
 989                 pllcfg |= HIFN_PLL_REF_CLK_HBI;
 990
 991         if (hifn_pll_ref[3] != '\0')
 992                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
 993         else {
 994                 freq = 66;
 995                 printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, "
 996                                  "override with hifn_pll_ref=%.3s<frequency>\n",
 997                        freq, hifn_pll_ref);
 998         }
 999
1000         m = HIFN_PLL_FCK_MAX / freq;
1001
1002         pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
1003         if (m <= 8)
1004                 pllcfg |= HIFN_PLL_IS_1_8;
1005         else
1006                 pllcfg |= HIFN_PLL_IS_9_12;
1007
1008         /* Select clock source and enable clock bypass */
1009         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1010                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
1011
1012         /* Let the chip lock to the input clock */
1013         mdelay(10);
1014
1015         /* Disable clock bypass */
1016         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1017                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
1018
1019         /* Switch the engines to the PLL */
1020         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1021                      HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
1022
1023         /*
1024          * The Fpk_clk runs at half the total speed. Its frequency is needed to
1025          * calculate the minimum time between two reads of the rng. Since 33MHz
1026          * is actually 33.333... we overestimate the frequency here, resulting
1027          * in slightly larger intervals.
1028          */
1029         dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
1030 }
1031
1032 static void hifn_init_registers(struct hifn_device *dev)
1033 {
1034         u32 dptr = dev->desc_dma;
1035
1036         /* Initialization magic... */
1037         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1038         hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1039         hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1040
1041         /* write all 4 ring address registers */
1042         hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
1043                                 offsetof(struct hifn_dma, cmdr[0]));
1044         hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
1045                                 offsetof(struct hifn_dma, srcr[0]));
1046         hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
1047                                 offsetof(struct hifn_dma, dstr[0]));
1048         hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
1049                                 offsetof(struct hifn_dma, resr[0]));
1050
1051         mdelay(2);
1052 #if 0
1053         hifn_write_1(dev, HIFN_1_DMA_CSR,
1054             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1055             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1056             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1057             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1058             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1059             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1060             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1061             HIFN_DMACSR_S_WAIT |
1062             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1063             HIFN_DMACSR_C_WAIT |
1064             HIFN_DMACSR_ENGINE |
1065             HIFN_DMACSR_PUBDONE);
1066 #else
1067         hifn_write_1(dev, HIFN_1_DMA_CSR,
1068             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1069             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1070             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1071             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1072             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1073             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1074             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1075             HIFN_DMACSR_S_WAIT |
1076             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1077             HIFN_DMACSR_C_WAIT |
1078             HIFN_DMACSR_ENGINE |
1079             HIFN_DMACSR_PUBDONE);
1080 #endif
1081         hifn_read_1(dev, HIFN_1_DMA_CSR);
1082
1083         dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1084             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1085             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1086             HIFN_DMAIER_ENGINE;
1087         dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1088
1089         hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1090         hifn_read_1(dev, HIFN_1_DMA_IER);
1091 #if 0
1092         hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1093                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1094                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1095                     HIFN_PUCNFG_DRAM);
1096 #else
1097         hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1098 #endif
1099         hifn_init_pll(dev);
1100
1101         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1102         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1103             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1104             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1105             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1106 }
1107
1108 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1109                 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1110 {
1111         struct hifn_base_command *base_cmd;
1112         u8 *buf_pos = buf;
1113
1114         base_cmd = (struct hifn_base_command *)buf_pos;
1115         base_cmd->masks = __cpu_to_le16(mask);
1116         base_cmd->total_source_count =
1117                 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1118         base_cmd->total_dest_count =
1119                 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1120
1121         dlen >>= 16;
1122         slen >>= 16;
1123         base_cmd->session_num = __cpu_to_le16(snum |
1124             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1125             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1126
1127         return sizeof(struct hifn_base_command);
1128 }
1129
1130 static int hifn_setup_crypto_command(struct hifn_device *dev,
1131                 u8 *buf, unsigned dlen, unsigned slen,
1132                 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1133 {
1134         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1135         struct hifn_crypt_command *cry_cmd;
1136         u8 *buf_pos = buf;
1137         u16 cmd_len;
1138
1139         cry_cmd = (struct hifn_crypt_command *)buf_pos;
1140
1141         cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1142         dlen >>= 16;
1143         cry_cmd->masks = __cpu_to_le16(mode |
1144                         ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1145                          HIFN_CRYPT_CMD_SRCLEN_M));
1146         cry_cmd->header_skip = 0;
1147         cry_cmd->reserved = 0;
1148
1149         buf_pos += sizeof(struct hifn_crypt_command);
1150
1151         dma->cmdu++;
1152         if (dma->cmdu > 1) {
1153                 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1154                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1155         }
1156
1157         if (keylen) {
1158                 memcpy(buf_pos, key, keylen);
1159                 buf_pos += keylen;
1160         }
1161         if (ivsize) {
1162                 memcpy(buf_pos, iv, ivsize);
1163                 buf_pos += ivsize;
1164         }
1165
1166         cmd_len = buf_pos - buf;
1167
1168         return cmd_len;
1169 }
1170
1171 static int hifn_setup_cmd_desc(struct hifn_device *dev,
1172                 struct hifn_context *ctx, void *priv, unsigned int nbytes)
1173 {
1174         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1175         int cmd_len, sa_idx;
1176         u8 *buf, *buf_pos;
1177         u16 mask;
1178
1179         sa_idx = dma->cmdi;
1180         buf_pos = buf = dma->command_bufs[dma->cmdi];
1181
1182         mask = 0;
1183         switch (ctx->op) {
1184                 case ACRYPTO_OP_DECRYPT:
1185                         mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1186                         break;
1187                 case ACRYPTO_OP_ENCRYPT:
1188                         mask = HIFN_BASE_CMD_CRYPT;
1189                         break;
1190                 case ACRYPTO_OP_HMAC:
1191                         mask = HIFN_BASE_CMD_MAC;
1192                         break;
1193                 default:
1194                         goto err_out;
1195         }
1196
1197         buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1198                         nbytes, mask, dev->snum);
1199
1200         if (ctx->op == ACRYPTO_OP_ENCRYPT || ctx->op == ACRYPTO_OP_DECRYPT) {
1201                 u16 md = 0;
1202
1203                 if (ctx->keysize)
1204                         md |= HIFN_CRYPT_CMD_NEW_KEY;
1205                 if (ctx->iv && ctx->mode != ACRYPTO_MODE_ECB)
1206                         md |= HIFN_CRYPT_CMD_NEW_IV;
1207
1208                 switch (ctx->mode) {
1209                         case ACRYPTO_MODE_ECB:
1210                                 md |= HIFN_CRYPT_CMD_MODE_ECB;
1211                                 break;
1212                         case ACRYPTO_MODE_CBC:
1213                                 md |= HIFN_CRYPT_CMD_MODE_CBC;
1214                                 break;
1215                         case ACRYPTO_MODE_CFB:
1216                                 md |= HIFN_CRYPT_CMD_MODE_CFB;
1217                                 break;
1218                         case ACRYPTO_MODE_OFB:
1219                                 md |= HIFN_CRYPT_CMD_MODE_OFB;
1220                                 break;
1221                         default:
1222                                 goto err_out;
1223                 }
1224
1225                 switch (ctx->type) {
1226                         case ACRYPTO_TYPE_AES_128:
1227                                 if (ctx->keysize != 16)
1228                                         goto err_out;
1229                                 md |= HIFN_CRYPT_CMD_KSZ_128 |
1230                                         HIFN_CRYPT_CMD_ALG_AES;
1231                                 break;
1232                         case ACRYPTO_TYPE_AES_192:
1233                                 if (ctx->keysize != 24)
1234                                         goto err_out;
1235                                 md |= HIFN_CRYPT_CMD_KSZ_192 |
1236                                         HIFN_CRYPT_CMD_ALG_AES;
1237                                 break;
1238                         case ACRYPTO_TYPE_AES_256:
1239                                 if (ctx->keysize != 32)
1240                                         goto err_out;
1241                                 md |= HIFN_CRYPT_CMD_KSZ_256 |
1242                                         HIFN_CRYPT_CMD_ALG_AES;
1243                                 break;
1244                         case ACRYPTO_TYPE_3DES:
1245                                 if (ctx->keysize != 24)
1246                                         goto err_out;
1247                                 md |= HIFN_CRYPT_CMD_ALG_3DES;
1248                                 break;
1249                         case ACRYPTO_TYPE_DES:
1250                                 if (ctx->keysize != 8)
1251                                         goto err_out;
1252                                 md |= HIFN_CRYPT_CMD_ALG_DES;
1253                                 break;
1254                         default:
1255                                 goto err_out;
1256                 }
1257
1258                 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1259                                 nbytes, nbytes, ctx->key, ctx->keysize,
1260                                 ctx->iv, ctx->ivsize, md);
1261         }
1262
1263         dev->sa[sa_idx] = priv;
1264
1265         cmd_len = buf_pos - buf;
1266         dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1267                         HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1268
1269         if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1270                 dma->cmdr[dma->cmdi].l = __cpu_to_le32(HIFN_MAX_COMMAND |
1271                         HIFN_D_VALID | HIFN_D_LAST |
1272                         HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1273                 dma->cmdi = 0;
1274         } else
1275                 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1276
1277         if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1278                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1279                 dev->flags |= HIFN_FLAG_CMD_BUSY;
1280         }
1281         return 0;
1282
1283 err_out:
1284         return -EINVAL;
1285 }
1286
1287 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1288                 unsigned int offset, unsigned int size)
1289 {
1290         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1291         int idx;
1292         dma_addr_t addr;
1293
1294         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1295
1296         idx = dma->srci;
1297
1298         dma->srcr[idx].p = __cpu_to_le32(addr);
1299         dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1300                         HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST);
1301
1302         if (++idx == HIFN_D_SRC_RSIZE) {
1303                 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1304                                 HIFN_D_JUMP |
1305                                 HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1306                 idx = 0;
1307         }
1308
1309         dma->srci = idx;
1310         dma->srcu++;
1311
1312         if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1313                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1314                 dev->flags |= HIFN_FLAG_SRC_BUSY;
1315         }
1316
1317         return size;
1318 }
1319
1320 static void hifn_setup_res_desc(struct hifn_device *dev)
1321 {
1322         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1323
1324         dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1325                         HIFN_D_VALID | HIFN_D_LAST);
1326         /*
1327          * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1328          *                                      HIFN_D_LAST | HIFN_D_NOINVALID);
1329          */
1330
1331         if (++dma->resi == HIFN_D_RES_RSIZE) {
1332                 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1333                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1334                 dma->resi = 0;
1335         }
1336
1337         dma->resu++;
1338
1339         if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1340                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1341                 dev->flags |= HIFN_FLAG_RES_BUSY;
1342         }
1343 }
1344
1345 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1346                 unsigned offset, unsigned size)
1347 {
1348         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1349         int idx;
1350         dma_addr_t addr;
1351
1352         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1353
1354         idx = dma->dsti;
1355         dma->dstr[idx].p = __cpu_to_le32(addr);
1356         dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1357                         HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST);
1358
1359         if (++idx == HIFN_D_DST_RSIZE) {
1360                 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1361                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1362                                 HIFN_D_LAST | HIFN_D_NOINVALID);
1363                 idx = 0;
1364         }
1365         dma->dsti = idx;
1366         dma->dstu++;
1367
1368         if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1369                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1370                 dev->flags |= HIFN_FLAG_DST_BUSY;
1371         }
1372 }
1373
1374 static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff,
1375                 struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv,
1376                 struct hifn_context *ctx)
1377 {
1378         dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n",
1379                         dev->name, spage, soff, dpage, doff, nbytes, priv, ctx);
1380
1381         hifn_setup_src_desc(dev, spage, soff, nbytes);
1382         hifn_setup_cmd_desc(dev, ctx, priv, nbytes);
1383         hifn_setup_dst_desc(dev, dpage, doff, nbytes);
1384         hifn_setup_res_desc(dev);
1385         return 0;
1386 }
1387
1388 static int ablkcipher_walk_init(struct ablkcipher_walk *w,
1389                 int num, gfp_t gfp_flags)
1390 {
1391         int i;
1392
1393         num = min(ASYNC_SCATTERLIST_CACHE, num);
1394         sg_init_table(w->cache, num);
1395
1396         w->num = 0;
1397         for (i=0; i<num; ++i) {
1398                 struct page *page = alloc_page(gfp_flags);
1399                 struct scatterlist *s;
1400
1401                 if (!page)
1402                         break;
1403
1404                 s = &w->cache[i];
1405
1406                 sg_set_page(s, page, PAGE_SIZE, 0);
1407                 w->num++;
1408         }
1409
1410         return i;
1411 }
1412
1413 static void ablkcipher_walk_exit(struct ablkcipher_walk *w)
1414 {
1415         int i;
1416
1417         for (i=0; i<w->num; ++i) {
1418                 struct scatterlist *s = &w->cache[i];
1419
1420                 __free_page(sg_page(s));
1421
1422                 s->length = 0;
1423         }
1424
1425         w->num = 0;
1426 }
1427
1428 static int ablkcipher_add(void *daddr, unsigned int *drestp, struct scatterlist *src,
1429                 unsigned int size, unsigned int *nbytesp)
1430 {
1431         unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1432         int idx = 0;
1433         void *saddr;
1434
1435         if (drest < size || size > nbytes)
1436                 return -EINVAL;
1437
1438         while (size) {
1439                 copy = min(drest, min(size, src->length));
1440
1441                 saddr = kmap_atomic(sg_page(src), KM_SOFTIRQ1);
1442                 memcpy(daddr, saddr + src->offset, copy);
1443                 kunmap_atomic(saddr, KM_SOFTIRQ1);
1444
1445                 size -= copy;
1446                 drest -= copy;
1447                 nbytes -= copy;
1448                 daddr += copy;
1449
1450                 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1451                                 __func__, copy, size, drest, nbytes);
1452
1453                 src++;
1454                 idx++;
1455         }
1456
1457         *nbytesp = nbytes;
1458         *drestp = drest;
1459
1460         return idx;
1461 }
1462
1463 static int ablkcipher_walk(struct ablkcipher_request *req,
1464                 struct ablkcipher_walk *w)
1465 {
1466         struct scatterlist *src, *dst, *t;
1467         void *daddr;
1468         unsigned int nbytes = req->nbytes, offset, copy, diff;
1469         int idx, tidx, err;
1470
1471         tidx = idx = 0;
1472         offset = 0;
1473         while (nbytes) {
1474                 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1475                         return -EINVAL;
1476
1477                 src = &req->src[idx];
1478                 dst = &req->dst[idx];
1479
1480                 dprintk("\n%s: slen: %u, dlen: %u, soff: %u, doff: %u, offset: %u, "
1481                                 "nbytes: %u.\n",
1482                                 __func__, src->length, dst->length, src->offset,
1483                                 dst->offset, offset, nbytes);
1484
1485                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1486                     !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1487                     offset) {
1488                         unsigned slen = min(src->length - offset, nbytes);
1489                         unsigned dlen = PAGE_SIZE;
1490
1491                         t = &w->cache[idx];
1492
1493                         daddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0);
1494                         err = ablkcipher_add(daddr, &dlen, src, slen, &nbytes);
1495                         if (err < 0)
1496                                 goto err_out_unmap;
1497
1498                         idx += err;
1499
1500                         copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1501                         diff = slen & (HIFN_D_DST_DALIGN - 1);
1502
1503                         if (dlen < nbytes) {
1504                                 /*
1505                                  * Destination page does not have enough space
1506                                  * to put there additional blocksized chunk,
1507                                  * so we mark that page as containing only
1508                                  * blocksize aligned chunks:
1509                                  *      t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
1510                                  * and increase number of bytes to be processed
1511                                  * in next chunk:
1512                                  *      nbytes += diff;
1513                                  */
1514                                 nbytes += diff;
1515
1516                                 /*
1517                                  * Temporary of course...
1518                                  * Kick author if you will catch this one.
1519                                  */
1520                                 printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
1521                                         "slen: %u, offset: %u.\n",
1522                                         __func__, dlen, nbytes, slen, offset);
1523                                 printk(KERN_ERR "%s: please contact author to fix this "
1524                                         "issue, generally you should not catch "
1525                                         "this path under any condition but who "
1526                                         "knows how did you use crypto code.\n"
1527                                         "Thank you.\n", __func__);
1528                                 BUG();
1529                         } else {
1530                                 copy += diff + nbytes;
1531
1532                                 src = &req->src[idx];
1533
1534                                 err = ablkcipher_add(daddr + slen, &dlen, src, nbytes, &nbytes);
1535                                 if (err < 0)
1536                                         goto err_out_unmap;
1537
1538                                 idx += err;
1539                         }
1540
1541                         t->length = copy;
1542                         t->offset = offset;
1543
1544                         kunmap_atomic(daddr, KM_SOFTIRQ0);
1545                 } else {
1546                         nbytes -= min(src->length, nbytes);
1547                         idx++;
1548                 }
1549
1550                 tidx++;
1551         }
1552
1553         return tidx;
1554
1555 err_out_unmap:
1556         kunmap_atomic(daddr, KM_SOFTIRQ0);
1557         return err;
1558 }
1559
1560 static int hifn_setup_session(struct ablkcipher_request *req)
1561 {
1562         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1563         struct hifn_device *dev = ctx->dev;
1564         struct page *spage, *dpage;
1565         unsigned long soff, doff, dlen, flags;
1566         unsigned int nbytes = req->nbytes, idx = 0, len;
1567         int err = -EINVAL, sg_num;
1568         struct scatterlist *src, *dst, *t;
1569
1570         if (ctx->iv && !ctx->ivsize && ctx->mode != ACRYPTO_MODE_ECB)
1571                 goto err_out_exit;
1572
1573         ctx->walk.flags = 0;
1574
1575         while (nbytes) {
1576                 dst = &req->dst[idx];
1577                 dlen = min(dst->length, nbytes);
1578
1579                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1580                     !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
1581                         ctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1582
1583                 nbytes -= dlen;
1584                 idx++;
1585         }
1586
1587         if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1588                 err = ablkcipher_walk_init(&ctx->walk, idx, GFP_ATOMIC);
1589                 if (err < 0)
1590                         return err;
1591         }
1592
1593         nbytes = req->nbytes;
1594         idx = 0;
1595
1596         sg_num = ablkcipher_walk(req, &ctx->walk);
1597         if (sg_num < 0) {
1598                 err = sg_num;
1599                 goto err_out_exit;
1600         }
1601         atomic_set(&ctx->sg_num, sg_num);
1602
1603         spin_lock_irqsave(&dev->lock, flags);
1604         if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1605                 err = -EAGAIN;
1606                 goto err_out;
1607         }
1608
1609         dev->snum++;
1610         dev->started += sg_num;
1611
1612         while (nbytes) {
1613                 src = &req->src[idx];
1614                 dst = &req->dst[idx];
1615                 t = &ctx->walk.cache[idx];
1616
1617                 if (t->length) {
1618                         spage = dpage = sg_page(t);
1619                         soff = doff = 0;
1620                         len = t->length;
1621                 } else {
1622                         spage = sg_page(src);
1623                         soff = src->offset;
1624
1625                         dpage = sg_page(dst);
1626                         doff = dst->offset;
1627
1628                         len = dst->length;
1629                 }
1630
1631                 idx++;
1632
1633                 err = hifn_setup_dma(dev, spage, soff, dpage, doff, nbytes,
1634                                 req, ctx);
1635                 if (err)
1636                         goto err_out;
1637
1638                 nbytes -= min(len, nbytes);
1639         }
1640
1641         dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1642         spin_unlock_irqrestore(&dev->lock, flags);
1643
1644         return 0;
1645
1646 err_out:
1647         spin_unlock_irqrestore(&dev->lock, flags);
1648 err_out_exit:
1649         if (err)
1650                 dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1651                                 "type: %u, err: %d.\n",
1652                         dev->name, ctx->iv, ctx->ivsize,
1653                         ctx->key, ctx->keysize,
1654                         ctx->mode, ctx->op, ctx->type, err);
1655
1656         return err;
1657 }
1658
1659 static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
1660 {
1661         int n, err;
1662         u8 src[16];
1663         struct hifn_context ctx;
1664         u8 fips_aes_ecb_from_zero[16] = {
1665                 0x66, 0xE9, 0x4B, 0xD4,
1666                 0xEF, 0x8A, 0x2C, 0x3B,
1667                 0x88, 0x4C, 0xFA, 0x59,
1668                 0xCA, 0x34, 0x2B, 0x2E};
1669
1670         memset(src, 0, sizeof(src));
1671         memset(ctx.key, 0, sizeof(ctx.key));
1672
1673         ctx.dev = dev;
1674         ctx.keysize = 16;
1675         ctx.ivsize = 0;
1676         ctx.iv = NULL;
1677         ctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
1678         ctx.mode = ACRYPTO_MODE_ECB;
1679         ctx.type = ACRYPTO_TYPE_AES_128;
1680         atomic_set(&ctx.sg_num, 1);
1681
1682         err = hifn_setup_dma(dev,
1683                         virt_to_page(src), offset_in_page(src),
1684                         virt_to_page(src), offset_in_page(src),
1685                         sizeof(src), NULL, &ctx);
1686         if (err)
1687                 goto err_out;
1688
1689         msleep(200);
1690
1691         dprintk("%s: decoded: ", dev->name);
1692         for (n=0; n<sizeof(src); ++n)
1693                 dprintk("%02x ", src[n]);
1694         dprintk("\n");
1695         dprintk("%s: FIPS   : ", dev->name);
1696         for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
1697                 dprintk("%02x ", fips_aes_ecb_from_zero[n]);
1698         dprintk("\n");
1699
1700         if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
1701                 printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
1702                                 "passed.\n", dev->name);
1703                 return 0;
1704         }
1705
1706 err_out:
1707         printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
1708         return -1;
1709 }
1710
1711 static int hifn_start_device(struct hifn_device *dev)
1712 {
1713         int err;
1714
1715         hifn_reset_dma(dev, 1);
1716
1717         err = hifn_enable_crypto(dev);
1718         if (err)
1719                 return err;
1720
1721         hifn_reset_puc(dev);
1722
1723         hifn_init_dma(dev);
1724
1725         hifn_init_registers(dev);
1726
1727         hifn_init_pubrng(dev);
1728
1729         return 0;
1730 }
1731
1732 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1733                 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1734 {
1735         unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1736         void *daddr;
1737         int idx = 0;
1738
1739         if (srest < size || size > nbytes)
1740                 return -EINVAL;
1741
1742         while (size) {
1743                 copy = min(srest, min(dst->length, size));
1744
1745                 daddr = kmap_atomic(sg_page(dst), KM_IRQ0);
1746                 memcpy(daddr + dst->offset + offset, saddr, copy);
1747                 kunmap_atomic(daddr, KM_IRQ0);
1748
1749                 nbytes -= copy;
1750                 size -= copy;
1751                 srest -= copy;
1752                 saddr += copy;
1753                 offset = 0;
1754
1755                 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1756                                 __func__, copy, size, srest, nbytes);
1757
1758                 dst++;
1759                 idx++;
1760         }
1761
1762         *nbytesp = nbytes;
1763         *srestp = srest;
1764
1765         return idx;
1766 }
1767
1768 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1769 {
1770         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1771         struct hifn_device *dev;
1772
1773         dprintk("%s: req: %p, ctx: %p.\n", __func__, req, ctx);
1774
1775         dev = ctx->dev;
1776         dprintk("%s: req: %p, started: %d, sg_num: %d.\n",
1777                 __func__, req, dev->started, atomic_read(&ctx->sg_num));
1778
1779         if (--dev->started < 0)
1780                 BUG();
1781
1782         if (atomic_dec_and_test(&ctx->sg_num)) {
1783                 unsigned int nbytes = req->nbytes;
1784                 int idx = 0, err;
1785                 struct scatterlist *dst, *t;
1786                 void *saddr;
1787
1788                 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1789                         while (nbytes) {
1790                                 t = &ctx->walk.cache[idx];
1791                                 dst = &req->dst[idx];
1792
1793                                 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1794                                         "sg_page(dst): %p, dst->length: %u, "
1795                                         "nbytes: %u.\n",
1796                                         __func__, sg_page(t), t->length,
1797                                         sg_page(dst), dst->length, nbytes);
1798
1799                                 if (!t->length) {
1800                                         nbytes -= min(dst->length, nbytes);
1801                                         idx++;
1802                                         continue;
1803                                 }
1804
1805                                 saddr = kmap_atomic(sg_page(t), KM_IRQ1);
1806
1807                                 err = ablkcipher_get(saddr, &t->length, t->offset,
1808                                                 dst, nbytes, &nbytes);
1809                                 if (err < 0) {
1810                                         kunmap_atomic(saddr, KM_IRQ1);
1811                                         break;
1812                                 }
1813
1814                                 idx += err;
1815                                 kunmap_atomic(saddr, KM_IRQ1);
1816                         }
1817
1818                         ablkcipher_walk_exit(&ctx->walk);
1819                 }
1820
1821                 req->base.complete(&req->base, error);
1822         }
1823 }
1824
1825 static void hifn_check_for_completion(struct hifn_device *dev, int error)
1826 {
1827         int i;
1828         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1829
1830         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1831                 struct hifn_desc *d = &dma->resr[i];
1832
1833                 if (!(d->l & __cpu_to_le32(HIFN_D_VALID)) && dev->sa[i]) {
1834                         dev->success++;
1835                         dev->reset = 0;
1836                         hifn_process_ready(dev->sa[i], error);
1837                         dev->sa[i] = NULL;
1838                 }
1839
1840                 if (d->l & __cpu_to_le32(HIFN_D_DESTOVER | HIFN_D_OVER))
1841                         if (printk_ratelimit())
1842                                 printk("%s: overflow detected [d: %u, o: %u] "
1843                                                 "at %d resr: l: %08x, p: %08x.\n",
1844                                         dev->name,
1845                                         !!(d->l & __cpu_to_le32(HIFN_D_DESTOVER)),
1846                                         !!(d->l & __cpu_to_le32(HIFN_D_OVER)),
1847                                         i, d->l, d->p);
1848         }
1849 }
1850
1851 static void hifn_clear_rings(struct hifn_device *dev)
1852 {
1853         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1854         int i, u;
1855
1856         dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1857                         "k: %d.%d.%d.%d.\n",
1858                         dev->name,
1859                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1860                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1861                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1862
1863         i = dma->resk; u = dma->resu;
1864         while (u != 0) {
1865                 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1866                         break;
1867
1868                 if (i != HIFN_D_RES_RSIZE)
1869                         u--;
1870
1871                 if (++i == (HIFN_D_RES_RSIZE + 1))
1872                         i = 0;
1873         }
1874         dma->resk = i; dma->resu = u;
1875
1876         i = dma->srck; u = dma->srcu;
1877         while (u != 0) {
1878                 if (i == HIFN_D_SRC_RSIZE)
1879                         i = 0;
1880                 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1881                         break;
1882                 i++, u--;
1883         }
1884         dma->srck = i; dma->srcu = u;
1885
1886         i = dma->cmdk; u = dma->cmdu;
1887         while (u != 0) {
1888                 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1889                         break;
1890                 if (i != HIFN_D_CMD_RSIZE)
1891                         u--;
1892                 if (++i == (HIFN_D_CMD_RSIZE + 1))
1893                         i = 0;
1894         }
1895         dma->cmdk = i; dma->cmdu = u;
1896
1897         i = dma->dstk; u = dma->dstu;
1898         while (u != 0) {
1899                 if (i == HIFN_D_DST_RSIZE)
1900                         i = 0;
1901                 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1902                         break;
1903                 i++, u--;
1904         }
1905         dma->dstk = i; dma->dstu = u;
1906
1907         dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1908                         "k: %d.%d.%d.%d.\n",
1909                         dev->name,
1910                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1911                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1912                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1913 }
1914
1915 static void hifn_work(struct work_struct *work)
1916 {
1917         struct delayed_work *dw = container_of(work, struct delayed_work, work);
1918         struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1919         unsigned long flags;
1920         int reset = 0;
1921         u32 r = 0;
1922
1923         spin_lock_irqsave(&dev->lock, flags);
1924         if (dev->active == 0) {
1925                 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1926
1927                 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1928                         dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1929                         r |= HIFN_DMACSR_C_CTRL_DIS;
1930                 }
1931                 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1932                         dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1933                         r |= HIFN_DMACSR_S_CTRL_DIS;
1934                 }
1935                 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1936                         dev->flags &= ~HIFN_FLAG_DST_BUSY;
1937                         r |= HIFN_DMACSR_D_CTRL_DIS;
1938                 }
1939                 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1940                         dev->flags &= ~HIFN_FLAG_RES_BUSY;
1941                         r |= HIFN_DMACSR_R_CTRL_DIS;
1942                 }
1943                 if (r)
1944                         hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1945         } else
1946                 dev->active--;
1947
1948         if (dev->prev_success == dev->success && dev->started)
1949                 reset = 1;
1950         dev->prev_success = dev->success;
1951         spin_unlock_irqrestore(&dev->lock, flags);
1952
1953         if (reset) {
1954                 dprintk("%s: r: %08x, active: %d, started: %d, "
1955                                 "success: %lu: reset: %d.\n",
1956                         dev->name, r, dev->active, dev->started,
1957                         dev->success, reset);
1958
1959                 if (++dev->reset >= 5) {
1960                         dprintk("%s: really hard reset.\n", dev->name);
1961                         hifn_reset_dma(dev, 1);
1962                         hifn_stop_device(dev);
1963                         hifn_start_device(dev);
1964                         dev->reset = 0;
1965                 }
1966
1967                 spin_lock_irqsave(&dev->lock, flags);
1968                 hifn_check_for_completion(dev, -EBUSY);
1969                 hifn_clear_rings(dev);
1970                 dev->started = 0;
1971                 spin_unlock_irqrestore(&dev->lock, flags);
1972         }
1973
1974         schedule_delayed_work(&dev->work, HZ);
1975 }
1976
1977 static irqreturn_t hifn_interrupt(int irq, void *data)
1978 {
1979         struct hifn_device *dev = (struct hifn_device *)data;
1980         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1981         u32 dmacsr, restart;
1982
1983         dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1984
1985         dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1986                         "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1987                 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1988                 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1989                 dma->cmdi, dma->srci, dma->dsti, dma->resi);
1990
1991         if ((dmacsr & dev->dmareg) == 0)
1992                 return IRQ_NONE;
1993
1994         hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1995
1996         if (dmacsr & HIFN_DMACSR_ENGINE)
1997                 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1998         if (dmacsr & HIFN_DMACSR_PUBDONE)
1999                 hifn_write_1(dev, HIFN_1_PUB_STATUS,
2000                         hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2001
2002         restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
2003         if (restart) {
2004                 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
2005
2006                 if (printk_ratelimit())
2007                         printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
2008                                 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
2009                                 !!(dmacsr & HIFN_DMACSR_D_OVER),
2010                                 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
2011                 if (!!(puisr & HIFN_PUISR_DSTOVER))
2012                         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
2013                 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
2014                                         HIFN_DMACSR_D_OVER));
2015         }
2016
2017         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2018                         HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2019         if (restart) {
2020                 if (printk_ratelimit())
2021                         printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
2022                                 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
2023                                 !!(dmacsr & HIFN_DMACSR_S_ABORT),
2024                                 !!(dmacsr & HIFN_DMACSR_D_ABORT),
2025                                 !!(dmacsr & HIFN_DMACSR_R_ABORT));
2026                 hifn_reset_dma(dev, 1);
2027                 hifn_init_dma(dev);
2028                 hifn_init_registers(dev);
2029         }
2030
2031         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2032                 dprintk("%s: wait on command.\n", dev->name);
2033                 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
2034                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
2035         }
2036
2037         tasklet_schedule(&dev->tasklet);
2038         hifn_clear_rings(dev);
2039
2040         return IRQ_HANDLED;
2041 }
2042
2043 static void hifn_flush(struct hifn_device *dev)
2044 {
2045         unsigned long flags;
2046         struct crypto_async_request *async_req;
2047         struct hifn_context *ctx;
2048         struct ablkcipher_request *req;
2049         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
2050         int i;
2051
2052         spin_lock_irqsave(&dev->lock, flags);
2053         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
2054                 struct hifn_desc *d = &dma->resr[i];
2055
2056                 if (dev->sa[i]) {
2057                         hifn_process_ready(dev->sa[i],
2058                                 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
2059                 }
2060         }
2061
2062         while ((async_req = crypto_dequeue_request(&dev->queue))) {
2063                 ctx = crypto_tfm_ctx(async_req->tfm);
2064                 req = container_of(async_req, struct ablkcipher_request, base);
2065
2066                 hifn_process_ready(req, -ENODEV);
2067         }
2068         spin_unlock_irqrestore(&dev->lock, flags);
2069 }
2070
2071 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
2072                 unsigned int len)
2073 {
2074         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
2075         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2076         struct hifn_device *dev = ctx->dev;
2077
2078         if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
2079                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
2080                 return -1;
2081         }
2082
2083         if (len == HIFN_DES_KEY_LENGTH) {
2084                 u32 tmp[DES_EXPKEY_WORDS];
2085                 int ret = des_ekey(tmp, key);
2086
2087                 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
2088                         tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
2089                         return -EINVAL;
2090                 }
2091         }
2092
2093         dev->flags &= ~HIFN_FLAG_OLD_KEY;
2094
2095         memcpy(ctx->key, key, len);
2096         ctx->keysize = len;
2097
2098         return 0;
2099 }
2100
2101 static int hifn_handle_req(struct ablkcipher_request *req)
2102 {
2103         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2104         struct hifn_device *dev = ctx->dev;
2105         int err = -EAGAIN;
2106
2107         if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
2108                 err = hifn_setup_session(req);
2109
2110         if (err == -EAGAIN) {
2111                 unsigned long flags;
2112
2113                 spin_lock_irqsave(&dev->lock, flags);
2114                 err = ablkcipher_enqueue_request(&dev->queue, req);
2115                 spin_unlock_irqrestore(&dev->lock, flags);
2116         }
2117
2118         return err;
2119 }
2120
2121 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
2122                 u8 type, u8 mode)
2123 {
2124         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2125         unsigned ivsize;
2126
2127         ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
2128
2129         if (req->info && mode != ACRYPTO_MODE_ECB) {
2130                 if (type == ACRYPTO_TYPE_AES_128)
2131                         ivsize = HIFN_AES_IV_LENGTH;
2132                 else if (type == ACRYPTO_TYPE_DES)
2133                         ivsize = HIFN_DES_KEY_LENGTH;
2134                 else if (type == ACRYPTO_TYPE_3DES)
2135                         ivsize = HIFN_3DES_KEY_LENGTH;
2136         }
2137
2138         if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2139                 if (ctx->keysize == 24)
2140                         type = ACRYPTO_TYPE_AES_192;
2141                 else if (ctx->keysize == 32)
2142                         type = ACRYPTO_TYPE_AES_256;
2143         }
2144
2145         ctx->op = op;
2146         ctx->mode = mode;
2147         ctx->type = type;
2148         ctx->iv = req->info;
2149         ctx->ivsize = ivsize;
2150
2151         /*
2152          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2153          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2154          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2155          */
2156
2157         return hifn_handle_req(req);
2158 }
2159
2160 static int hifn_process_queue(struct hifn_device *dev)
2161 {
2162         struct crypto_async_request *async_req;
2163         struct hifn_context *ctx;
2164         struct ablkcipher_request *req;
2165         unsigned long flags;
2166         int err = 0;
2167
2168         while (dev->started < HIFN_QUEUE_LENGTH) {
2169                 spin_lock_irqsave(&dev->lock, flags);
2170                 async_req = crypto_dequeue_request(&dev->queue);
2171                 spin_unlock_irqrestore(&dev->lock, flags);
2172
2173                 if (!async_req)
2174                         break;
2175
2176                 ctx = crypto_tfm_ctx(async_req->tfm);
2177                 req = container_of(async_req, struct ablkcipher_request, base);
2178
2179                 err = hifn_handle_req(req);
2180                 if (err)
2181                         break;
2182         }
2183
2184         return err;
2185 }
2186
2187 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2188                 u8 type, u8 mode)
2189 {
2190         int err;
2191         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2192         struct hifn_device *dev = ctx->dev;
2193
2194         err = hifn_setup_crypto_req(req, op, type, mode);
2195         if (err)
2196                 return err;
2197
2198         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2199                 hifn_process_queue(dev);
2200
2201         return -EINPROGRESS;
2202 }
2203
2204 /*
2205  * AES ecryption functions.
2206  */
2207 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2208 {
2209         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2210                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2211 }
2212 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2213 {
2214         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2215                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2216 }
2217 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2218 {
2219         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2220                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2221 }
2222 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2223 {
2224         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2225                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2226 }
2227
2228 /*
2229  * AES decryption functions.
2230  */
2231 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2232 {
2233         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2234                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2235 }
2236 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2237 {
2238         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2239                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2240 }
2241 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2242 {
2243         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2244                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2245 }
2246 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2247 {
2248         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2249                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2250 }
2251
2252 /*
2253  * DES ecryption functions.
2254  */
2255 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2256 {
2257         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2258                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2259 }
2260 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2261 {
2262         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2263                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2264 }
2265 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2266 {
2267         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2268                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2269 }
2270 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2271 {
2272         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2273                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2274 }
2275
2276 /*
2277  * DES decryption functions.
2278  */
2279 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2280 {
2281         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2282                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2283 }
2284 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2285 {
2286         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2287                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2288 }
2289 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2290 {
2291         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2292                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2293 }
2294 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2295 {
2296         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2297                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2298 }
2299
2300 /*
2301  * 3DES ecryption functions.
2302  */
2303 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2304 {
2305         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2306                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2307 }
2308 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2309 {
2310         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2311                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2312 }
2313 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2314 {
2315         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2316                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2317 }
2318 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2319 {
2320         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2321                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2322 }
2323
2324 /*
2325  * 3DES decryption functions.
2326  */
2327 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2328 {
2329         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2330                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2331 }
2332 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2333 {
2334         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2335                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2336 }
2337 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2338 {
2339         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2340                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2341 }
2342 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2343 {
2344         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2345                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2346 }
2347
2348 struct hifn_alg_template
2349 {
2350         char name[CRYPTO_MAX_ALG_NAME];
2351         char drv_name[CRYPTO_MAX_ALG_NAME];
2352         unsigned int bsize;
2353         struct ablkcipher_alg ablkcipher;
2354 };
2355
2356 static struct hifn_alg_template hifn_alg_templates[] = {
2357         /*
2358          * 3DES ECB, CBC, CFB and OFB modes.
2359          */
2360         {
2361                 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
2362                 .ablkcipher = {
2363                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2364                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2365                         .setkey         =       hifn_setkey,
2366                         .encrypt        =       hifn_encrypt_3des_cfb,
2367                         .decrypt        =       hifn_decrypt_3des_cfb,
2368                 },
2369         },
2370         {
2371                 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
2372                 .ablkcipher = {
2373                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2374                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2375                         .setkey         =       hifn_setkey,
2376                         .encrypt        =       hifn_encrypt_3des_ofb,
2377                         .decrypt        =       hifn_decrypt_3des_ofb,
2378                 },
2379         },
2380         {
2381                 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
2382                 .ablkcipher = {
2383                         .ivsize         =       HIFN_IV_LENGTH,
2384                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2385                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2386                         .setkey         =       hifn_setkey,
2387                         .encrypt        =       hifn_encrypt_3des_cbc,
2388                         .decrypt        =       hifn_decrypt_3des_cbc,
2389                 },
2390         },
2391         {
2392                 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
2393                 .ablkcipher = {
2394                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2395                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2396                         .setkey         =       hifn_setkey,
2397                         .encrypt        =       hifn_encrypt_3des_ecb,
2398                         .decrypt        =       hifn_decrypt_3des_ecb,
2399                 },
2400         },
2401
2402         /*
2403          * DES ECB, CBC, CFB and OFB modes.
2404          */
2405         {
2406                 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
2407                 .ablkcipher = {
2408                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2409                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2410                         .setkey         =       hifn_setkey,
2411                         .encrypt        =       hifn_encrypt_des_cfb,
2412                         .decrypt        =       hifn_decrypt_des_cfb,
2413                 },
2414         },
2415         {
2416                 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
2417                 .ablkcipher = {
2418                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2419                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2420                         .setkey         =       hifn_setkey,
2421                         .encrypt        =       hifn_encrypt_des_ofb,
2422                         .decrypt        =       hifn_decrypt_des_ofb,
2423                 },
2424         },
2425         {
2426                 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
2427                 .ablkcipher = {
2428                         .ivsize         =       HIFN_IV_LENGTH,
2429                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2430                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2431                         .setkey         =       hifn_setkey,
2432                         .encrypt        =       hifn_encrypt_des_cbc,
2433                         .decrypt        =       hifn_decrypt_des_cbc,
2434                 },
2435         },
2436         {
2437                 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
2438                 .ablkcipher = {
2439                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2440                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2441                         .setkey         =       hifn_setkey,
2442                         .encrypt        =       hifn_encrypt_des_ecb,
2443                         .decrypt        =       hifn_decrypt_des_ecb,
2444                 },
2445         },
2446
2447         /*
2448          * AES ECB, CBC, CFB and OFB modes.
2449          */
2450         {
2451                 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
2452                 .ablkcipher = {
2453                         .min_keysize    =       AES_MIN_KEY_SIZE,
2454                         .max_keysize    =       AES_MAX_KEY_SIZE,
2455                         .setkey         =       hifn_setkey,
2456                         .encrypt        =       hifn_encrypt_aes_ecb,
2457                         .decrypt        =       hifn_decrypt_aes_ecb,
2458                 },
2459         },
2460         {
2461                 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
2462                 .ablkcipher = {
2463                         .ivsize         =       HIFN_AES_IV_LENGTH,
2464                         .min_keysize    =       AES_MIN_KEY_SIZE,
2465                         .max_keysize    =       AES_MAX_KEY_SIZE,
2466                         .setkey         =       hifn_setkey,
2467                         .encrypt        =       hifn_encrypt_aes_cbc,
2468                         .decrypt        =       hifn_decrypt_aes_cbc,
2469                 },
2470         },
2471         {
2472                 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
2473                 .ablkcipher = {
2474                         .min_keysize    =       AES_MIN_KEY_SIZE,
2475                         .max_keysize    =       AES_MAX_KEY_SIZE,
2476                         .setkey         =       hifn_setkey,
2477                         .encrypt        =       hifn_encrypt_aes_cfb,
2478                         .decrypt        =       hifn_decrypt_aes_cfb,
2479                 },
2480         },
2481         {
2482                 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
2483                 .ablkcipher = {
2484                         .min_keysize    =       AES_MIN_KEY_SIZE,
2485                         .max_keysize    =       AES_MAX_KEY_SIZE,
2486                         .setkey         =       hifn_setkey,
2487                         .encrypt        =       hifn_encrypt_aes_ofb,
2488                         .decrypt        =       hifn_decrypt_aes_ofb,
2489                 },
2490         },
2491 };
2492
2493 static int hifn_cra_init(struct crypto_tfm *tfm)
2494 {
2495         struct crypto_alg *alg = tfm->__crt_alg;
2496         struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2497         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2498
2499         ctx->dev = ha->dev;
2500
2501         return 0;
2502 }
2503
2504 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2505 {
2506         struct hifn_crypto_alg *alg;
2507         int err;
2508
2509         alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2510         if (!alg)
2511                 return -ENOMEM;
2512
2513         snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2514         snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2515                  t->drv_name, dev->name);
2516
2517         alg->alg.cra_priority = 300;
2518         alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC;
2519         alg->alg.cra_blocksize = t->bsize;
2520         alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2521         alg->alg.cra_alignmask = 0;
2522         alg->alg.cra_type = &crypto_ablkcipher_type;
2523         alg->alg.cra_module = THIS_MODULE;
2524         alg->alg.cra_u.ablkcipher = t->ablkcipher;
2525         alg->alg.cra_init = hifn_cra_init;
2526
2527         alg->dev = dev;
2528
2529         list_add_tail(&alg->entry, &dev->alg_list);
2530
2531         err = crypto_register_alg(&alg->alg);
2532         if (err) {
2533                 list_del(&alg->entry);
2534                 kfree(alg);
2535         }
2536
2537         return err;
2538 }
2539
2540 static void hifn_unregister_alg(struct hifn_device *dev)
2541 {
2542         struct hifn_crypto_alg *a, *n;
2543
2544         list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2545                 list_del(&a->entry);
2546                 crypto_unregister_alg(&a->alg);
2547                 kfree(a);
2548         }
2549 }
2550
2551 static int hifn_register_alg(struct hifn_device *dev)
2552 {
2553         int i, err;
2554
2555         for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2556                 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2557                 if (err)
2558                         goto err_out_exit;
2559         }
2560
2561         return 0;
2562
2563 err_out_exit:
2564         hifn_unregister_alg(dev);
2565         return err;
2566 }
2567
2568 static void hifn_tasklet_callback(unsigned long data)
2569 {
2570         struct hifn_device *dev = (struct hifn_device *)data;
2571
2572         /*
2573          * This is ok to call this without lock being held,
2574          * althogh it modifies some parameters used in parallel,
2575          * (like dev->success), but they are used in process
2576          * context or update is atomic (like setting dev->sa[i] to NULL).
2577          */
2578         hifn_check_for_completion(dev, 0);
2579 }
2580
2581 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2582 {
2583         int err, i;
2584         struct hifn_device *dev;
2585         char name[8];
2586
2587         err = pci_enable_device(pdev);
2588         if (err)
2589                 return err;
2590         pci_set_master(pdev);
2591
2592         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2593         if (err)
2594                 goto err_out_disable_pci_device;
2595
2596         snprintf(name, sizeof(name), "hifn%d",
2597                         atomic_inc_return(&hifn_dev_number)-1);
2598
2599         err = pci_request_regions(pdev, name);
2600         if (err)
2601                 goto err_out_disable_pci_device;
2602
2603         if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2604             pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2605             pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2606                 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2607                                 pci_name(pdev));
2608                 err = -ENODEV;
2609                 goto err_out_free_regions;
2610         }
2611
2612         dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2613                         GFP_KERNEL);
2614         if (!dev) {
2615                 err = -ENOMEM;
2616                 goto err_out_free_regions;
2617         }
2618
2619         INIT_LIST_HEAD(&dev->alg_list);
2620
2621         snprintf(dev->name, sizeof(dev->name), "%s", name);
2622         spin_lock_init(&dev->lock);
2623
2624         for (i=0; i<3; ++i) {
2625                 unsigned long addr, size;
2626
2627                 addr = pci_resource_start(pdev, i);
2628                 size = pci_resource_len(pdev, i);
2629
2630                 dev->bar[i] = ioremap_nocache(addr, size);
2631                 if (!dev->bar[i])
2632                         goto err_out_unmap_bars;
2633         }
2634
2635         dev->result_mem = __get_free_pages(GFP_KERNEL, HIFN_MAX_RESULT_ORDER);
2636         if (!dev->result_mem) {
2637                 dprintk("Failed to allocate %d pages for result_mem.\n",
2638                                 HIFN_MAX_RESULT_ORDER);
2639                 goto err_out_unmap_bars;
2640         }
2641         memset((void *)dev->result_mem, 0, PAGE_SIZE*(1<<HIFN_MAX_RESULT_ORDER));
2642
2643         dev->dst = pci_map_single(pdev, (void *)dev->result_mem,
2644                         PAGE_SIZE << HIFN_MAX_RESULT_ORDER, PCI_DMA_FROMDEVICE);
2645
2646         dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma),
2647                         &dev->desc_dma);
2648         if (!dev->desc_virt) {
2649                 dprintk("Failed to allocate descriptor rings.\n");
2650                 goto err_out_free_result_pages;
2651         }
2652         memset(dev->desc_virt, 0, sizeof(struct hifn_dma));
2653
2654         dev->pdev = pdev;
2655         dev->irq = pdev->irq;
2656
2657         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2658                 dev->sa[i] = NULL;
2659
2660         pci_set_drvdata(pdev, dev);
2661
2662         tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2663
2664         crypto_init_queue(&dev->queue, 1);
2665
2666         err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2667         if (err) {
2668                 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
2669                 dev->irq = 0;
2670                 goto err_out_free_desc;
2671         }
2672
2673         err = hifn_start_device(dev);
2674         if (err)
2675                 goto err_out_free_irq;
2676
2677         err = hifn_test(dev, 1, 0);
2678         if (err)
2679                 goto err_out_stop_device;
2680
2681         err = hifn_register_rng(dev);
2682         if (err)
2683                 goto err_out_stop_device;
2684
2685         err = hifn_register_alg(dev);
2686         if (err)
2687                 goto err_out_unregister_rng;
2688
2689         INIT_DELAYED_WORK(&dev->work, hifn_work);
2690         schedule_delayed_work(&dev->work, HZ);
2691
2692         dprintk("HIFN crypto accelerator card at %s has been "
2693                         "successfully registered as %s.\n",
2694                         pci_name(pdev), dev->name);
2695
2696         return 0;
2697
2698 err_out_unregister_rng:
2699         hifn_unregister_rng(dev);
2700 err_out_stop_device:
2701         hifn_reset_dma(dev, 1);
2702         hifn_stop_device(dev);
2703 err_out_free_irq:
2704         free_irq(dev->irq, dev->name);
2705         tasklet_kill(&dev->tasklet);
2706 err_out_free_desc:
2707         pci_free_consistent(pdev, sizeof(struct hifn_dma),
2708                         dev->desc_virt, dev->desc_dma);
2709
2710 err_out_free_result_pages:
2711         pci_unmap_single(pdev, dev->dst, PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2712                         PCI_DMA_FROMDEVICE);
2713         free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2714
2715 err_out_unmap_bars:
2716         for (i=0; i<3; ++i)
2717                 if (dev->bar[i])
2718                         iounmap(dev->bar[i]);
2719
2720 err_out_free_regions:
2721         pci_release_regions(pdev);
2722
2723 err_out_disable_pci_device:
2724         pci_disable_device(pdev);
2725
2726         return err;
2727 }
2728
2729 static void hifn_remove(struct pci_dev *pdev)
2730 {
2731         int i;
2732         struct hifn_device *dev;
2733
2734         dev = pci_get_drvdata(pdev);
2735
2736         if (dev) {
2737                 cancel_delayed_work(&dev->work);
2738                 flush_scheduled_work();
2739
2740                 hifn_unregister_rng(dev);
2741                 hifn_unregister_alg(dev);
2742                 hifn_reset_dma(dev, 1);
2743                 hifn_stop_device(dev);
2744
2745                 free_irq(dev->irq, dev->name);
2746                 tasklet_kill(&dev->tasklet);
2747
2748                 hifn_flush(dev);
2749
2750                 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2751                                 dev->desc_virt, dev->desc_dma);
2752                 pci_unmap_single(pdev, dev->dst,
2753                                 PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2754                                 PCI_DMA_FROMDEVICE);
2755                 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2756                 for (i=0; i<3; ++i)
2757                         if (dev->bar[i])
2758                                 iounmap(dev->bar[i]);
2759
2760                 kfree(dev);
2761         }
2762
2763         pci_release_regions(pdev);
2764         pci_disable_device(pdev);
2765 }
2766
2767 static struct pci_device_id hifn_pci_tbl[] = {
2768         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2769         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2770         { 0 }
2771 };
2772 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2773
2774 static struct pci_driver hifn_pci_driver = {
2775         .name     = "hifn795x",
2776         .id_table = hifn_pci_tbl,
2777         .probe    = hifn_probe,
2778         .remove   = __devexit_p(hifn_remove),
2779 };
2780
2781 static int __devinit hifn_init(void)
2782 {
2783         unsigned int freq;
2784         int err;
2785
2786         if (strncmp(hifn_pll_ref, "ext", 3) &&
2787             strncmp(hifn_pll_ref, "pci", 3)) {
2788                 printk(KERN_ERR "hifn795x: invalid hifn_pll_ref clock, "
2789                                 "must be pci or ext");
2790                 return -EINVAL;
2791         }
2792
2793         /*
2794          * For the 7955/7956 the reference clock frequency must be in the
2795          * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2796          * but this chip is currently not supported.
2797          */
2798         if (hifn_pll_ref[3] != '\0') {
2799                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2800                 if (freq < 20 || freq > 100) {
2801                         printk(KERN_ERR "hifn795x: invalid hifn_pll_ref "
2802                                         "frequency, must be in the range "
2803                                         "of 20-100");
2804                         return -EINVAL;
2805                 }
2806         }
2807
2808         err = pci_register_driver(&hifn_pci_driver);
2809         if (err < 0) {
2810                 dprintk("Failed to register PCI driver for %s device.\n",
2811                                 hifn_pci_driver.name);
2812                 return -ENODEV;
2813         }
2814
2815         printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2816                         "has been successfully registered.\n");
2817
2818         return 0;
2819 }
2820
2821 static void __devexit hifn_fini(void)
2822 {
2823         pci_unregister_driver(&hifn_pci_driver);
2824
2825         printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2826                         "has been successfully unregistered.\n");
2827 }
2828
2829 module_init(hifn_init);
2830 module_exit(hifn_fini);
2831
2832 MODULE_LICENSE("GPL");
2833 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2834 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");