git.oblomov.eu Git - linux-2.6/blob - drivers/media/dvb/frontends/stb0899_algo.c

   1 /*
   2         STB0899 Multistandard Frontend driver
   3         Copyright (C) Manu Abraham (abraham.manu@gmail.com)
   4
   5         Copyright (C) ST Microelectronics
   6
   7         This program is free software; you can redistribute it and/or modify
   8         it under the terms of the GNU General Public License as published by
   9         the Free Software Foundation; either version 2 of the License, or
  10         (at your option) any later version.
  11
  12         This program is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17         You should have received a copy of the GNU General Public License
  18         along with this program; if not, write to the Free Software
  19         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include "stb0899_drv.h"
  23 #include "stb0899_priv.h"
  24 #include "stb0899_reg.h"
  25
  26 inline u32 stb0899_do_div(u64 n, u32 d)
  27 {
  28         /* wrap do_div() for ease of use */
  29
  30         do_div(n, d);
  31         return n;
  32 }
  33
  34 /*
  35  * stb0899_calc_srate
  36  * Compute symbol rate
  37  */
  38 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
  39 {
  40         u64 tmp;
  41
  42         /* srate = (SFR * master_clk) >> 20 */
  43
  44         /* sfr is of size 20 bit, stored with an offset of 4 bit */
  45         tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
  46         tmp &= ~0xf;
  47         tmp *= master_clk;
  48         tmp >>= 24;
  49
  50         return tmp;
  51 }
  52
  53 /*
  54  * stb0899_get_srate
  55  * Get the current symbol rate
  56  */
  57 u32 stb0899_get_srate(struct stb0899_state *state)
  58 {
  59         struct stb0899_internal *internal = &state->internal;
  60         u8 sfr[3];
  61
  62         stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
  63
  64         return stb0899_calc_srate(internal->master_clk, sfr);
  65 }
  66
  67 /*
  68  * stb0899_set_srate
  69  * Set symbol frequency
  70  * MasterClock: master clock frequency (hz)
  71  * SymbolRate: symbol rate (bauds)
  72  * return symbol frequency
  73  */
  74 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
  75 {
  76         u32 tmp, tmp_up, srate_up;
  77         u8 sfr_up[3], sfr[3];
  78
  79 //      srate_up = srate;
  80         dprintk(state->verbose, FE_DEBUG, 1, "-->");
  81         /*
  82          * in order to have the maximum precision, the symbol rate entered into
  83          * the chip is computed as the closest value of the "true value".
  84          * In this purpose, the symbol rate value is rounded (1 is added on the bit
  85          * below the LSB )
  86          */
  87 //      srate_up += (srate_up * 3) / 100;
  88
  89         /*
  90          * srate = (SFR * master_clk) >> 20
  91          *      <=>
  92          *   SFR = srate << 20 / master_clk
  93          *
  94          * rounded:
  95          *   SFR = (srate << 21 + master_clk) / (2 * master_clk)
  96          *
  97          * stored as 20 bit number with an offset of 4 bit:
  98          *   sfr = SFR << 4;
  99          */
 100 //      tmp_up = stb0899_do_div((((u64)srate_up) << 21) + master_clk, 2 * master_clk);
 101 //      tmp_up <<= 4;
 102
 103         tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
 104         tmp <<= 4;
 105
 106 //      sfr_up[0] = tmp_up >> 16;
 107 //      sfr_up[1] = tmp_up >>  8;
 108 //      sfr_up[2] = tmp_up;
 109
 110         sfr[0] = tmp >> 16;
 111         sfr[1] = tmp >>  8;
 112         sfr[2] = tmp;
 113
 114 //      stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
 115         stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
 116
 117         return srate;
 118 }
 119
 120 /*
 121  * stb0899_calc_loop_time
 122  * Compute the amount of time needed by the timing loop to lock
 123  * SymbolRate: Symbol rate
 124  * return: timing loop time constant (ms)
 125  */
 126 static long stb0899_calc_loop_time(long srate)
 127 {
 128         if (srate > 0)
 129                 return (100000 / (srate / 1000));
 130         else
 131                 return 0;
 132 }
 133
 134 /*
 135  * stb0899_calc_derot_time
 136  * Compute the amount of time needed by the derotator to lock
 137  * SymbolRate: Symbol rate
 138  * return: derotator time constant (ms)
 139  */
 140 static long stb0899_calc_derot_time(long srate)
 141 {
 142         if (srate > 0)
 143                 return (100000 / (srate / 1000));
 144         else
 145                 return 0;
 146 }
 147
 148 /*
 149  * stb0899_carr_width
 150  * Compute the width of the carrier
 151  * return: width of carrier (kHz or Mhz)
 152  */
 153 long stb0899_carr_width(struct stb0899_state *state)
 154 {
 155         struct stb0899_internal *internal = &state->internal;
 156
 157         return (internal->srate + (internal->srate * internal->rolloff) / 100);
 158 }
 159
 160 /*
 161  * stb0899_first_subrange
 162  * Compute the first subrange of the search
 163  */
 164 static void stb0899_first_subrange(struct stb0899_state *state)
 165 {
 166         struct stb0899_internal *internal       = &state->internal;
 167         struct stb0899_params *params           = &state->params;
 168         struct stb0899_config *config           =  state->config;
 169
 170         int range = 0;
 171         u32 bandwidth = 0;
 172
 173         if (config->tuner_get_bandwidth) {
 174                 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 175                 range = bandwidth - stb0899_carr_width(state) / 2;
 176         }
 177
 178         if (range > 0)
 179                 internal->sub_range = MIN(internal->srch_range, range);
 180         else
 181                 internal->sub_range = 0;
 182
 183         internal->freq = params->freq;
 184         internal->tuner_offst = 0L;
 185         internal->sub_dir = 1;
 186 }
 187
 188 /*
 189  * stb0899_check_tmg
 190  * check for timing lock
 191  * internal.Ttiming: time to wait for loop lock
 192  */
 193 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
 194 {
 195         struct stb0899_internal *internal = &state->internal;
 196         int lock;
 197         u8 reg;
 198         s8 timing;
 199
 200         msleep(internal->t_timing);
 201
 202         stb0899_write_reg(state, STB0899_RTF, 0xf2);
 203         reg = stb0899_read_reg(state, STB0899_TLIR);
 204         lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
 205         timing = stb0899_read_reg(state, STB0899_RTF);
 206
 207         if (lock >= 42) {
 208                 if ((lock > 48) && (ABS(timing) >= 110)) {
 209                         internal->status = ANALOGCARRIER;
 210                         dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
 211                 } else {
 212                         internal->status = TIMINGOK;
 213                         dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
 214                 }
 215         } else {
 216                 internal->status = NOTIMING;
 217                 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
 218         }
 219         return internal->status;
 220 }
 221
 222 /*
 223  * stb0899_search_tmg
 224  * perform a fs/2 zig-zag to find timing
 225  */
 226 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
 227 {
 228         struct stb0899_internal *internal = &state->internal;
 229         struct stb0899_params *params = &state->params;
 230
 231         short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
 232         int index = 0;
 233         u8 cfr[2];
 234
 235         internal->status = NOTIMING;
 236
 237         /* timing loop computation & symbol rate optimisation   */
 238         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 239         derot_step = (params->srate / 2L) / internal->mclk;
 240
 241         while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
 242                 index++;
 243                 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position  */
 244
 245                 if (ABS(derot_freq) > derot_limit)
 246                         next_loop--;
 247
 248                 if (next_loop) {
 249                         STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 250                         STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 251                         stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency         */
 252                 }
 253                 internal->direction = -internal->direction;     /* Change zigzag direction              */
 254         }
 255
 256         if (internal->status == TIMINGOK) {
 257                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency              */
 258                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 259                 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
 260         }
 261
 262         return internal->status;
 263 }
 264
 265 /*
 266  * stb0899_check_carrier
 267  * Check for carrier found
 268  */
 269 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
 270 {
 271         struct stb0899_internal *internal = &state->internal;
 272         u8 reg;
 273
 274         msleep(internal->t_derot); /* wait for derotator ok     */
 275
 276         reg = stb0899_read_reg(state, STB0899_CFD);
 277         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 278         stb0899_write_reg(state, STB0899_CFD, reg);
 279
 280         reg = stb0899_read_reg(state, STB0899_DSTATUS);
 281         dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
 282         if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
 283                 internal->status = CARRIEROK;
 284                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
 285         } else {
 286                 internal->status = NOCARRIER;
 287                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
 288         }
 289
 290         return internal->status;
 291 }
 292
 293 /*
 294  * stb0899_search_carrier
 295  * Search for a QPSK carrier with the derotator
 296  */
 297 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
 298 {
 299         struct stb0899_internal *internal = &state->internal;
 300
 301         short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
 302         int index = 0;
 303         u8 cfr[2];
 304         u8 reg;
 305
 306         internal->status = NOCARRIER;
 307         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 308         derot_freq = internal->derot_freq;
 309
 310         reg = stb0899_read_reg(state, STB0899_CFD);
 311         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 312         stb0899_write_reg(state, STB0899_CFD, reg);
 313
 314         do {
 315                 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
 316                 if (stb0899_check_carrier(state) == NOCARRIER) {
 317                         index++;
 318                         last_derot_freq = derot_freq;
 319                         derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position    */
 320
 321                         if(ABS(derot_freq) > derot_limit)
 322                                 next_loop--;
 323
 324                         if (next_loop) {
 325                                 reg = stb0899_read_reg(state, STB0899_CFD);
 326                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 327                                 stb0899_write_reg(state, STB0899_CFD, reg);
 328
 329                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 330                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 331                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 332                         }
 333                 }
 334
 335                 internal->direction = -internal->direction; /* Change zigzag direction  */
 336         } while ((internal->status != CARRIEROK) && next_loop);
 337
 338         if (internal->status == CARRIEROK) {
 339                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 340                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 341                 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
 342         } else {
 343                 internal->derot_freq = last_derot_freq;
 344         }
 345
 346         return internal->status;
 347 }
 348
 349 /*
 350  * stb0899_check_data
 351  * Check for data found
 352  */
 353 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
 354 {
 355         struct stb0899_internal *internal = &state->internal;
 356         struct stb0899_params *params = &state->params;
 357
 358         int lock = 0, index = 0, dataTime = 500, loop;
 359         u8 reg;
 360
 361         internal->status = NODATA;
 362
 363         /* RESET FEC    */
 364         reg = stb0899_read_reg(state, STB0899_TSTRES);
 365         STB0899_SETFIELD_VAL(FRESACS, reg, 1);
 366         stb0899_write_reg(state, STB0899_TSTRES, reg);
 367         msleep(1);
 368         reg = stb0899_read_reg(state, STB0899_TSTRES);
 369         STB0899_SETFIELD_VAL(FRESACS, reg, 0);
 370         stb0899_write_reg(state, STB0899_TSTRES, reg);
 371
 372         if (params->srate <= 2000000)
 373                 dataTime = 2000;
 374         else if (params->srate <= 5000000)
 375                 dataTime = 1500;
 376         else if (params->srate <= 15000000)
 377                 dataTime = 1000;
 378         else
 379                 dataTime = 500;
 380
 381         stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop  */
 382         while (1) {
 383                 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP    */
 384                 reg = stb0899_read_reg(state, STB0899_VSTATUS);
 385                 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
 386                 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
 387
 388                 if (lock || loop || (index > dataTime))
 389                         break;
 390                 index++;
 391         }
 392
 393         if (lock) {     /* DATA LOCK indicator  */
 394                 internal->status = DATAOK;
 395                 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
 396         }
 397
 398         return internal->status;
 399 }
 400
 401 /*
 402  * stb0899_search_data
 403  * Search for a QPSK carrier with the derotator
 404  */
 405 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
 406 {
 407         short int derot_freq, derot_step, derot_limit, next_loop = 3;
 408         u8 cfr[2];
 409         u8 reg;
 410         int index = 1;
 411
 412         struct stb0899_internal *internal = &state->internal;
 413         struct stb0899_params *params = &state->params;
 414
 415         derot_step = (params->srate / 4L) / internal->mclk;
 416         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 417         derot_freq = internal->derot_freq;
 418
 419         do {
 420                 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
 421
 422                         derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position      */
 423                         if (ABS(derot_freq) > derot_limit)
 424                                 next_loop--;
 425
 426                         if (next_loop) {
 427                                 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
 428                                 reg = stb0899_read_reg(state, STB0899_CFD);
 429                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 430                                 stb0899_write_reg(state, STB0899_CFD, reg);
 431
 432                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 433                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 434                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 435
 436                                 stb0899_check_carrier(state);
 437                                 index++;
 438                         }
 439                 }
 440                 internal->direction = -internal->direction; /* change zig zag direction         */
 441         } while ((internal->status != DATAOK) && next_loop);
 442
 443         if (internal->status == DATAOK) {
 444                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 445                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 446                 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
 447         }
 448
 449         return internal->status;
 450 }
 451
 452 /*
 453  * stb0899_check_range
 454  * check if the found frequency is in the correct range
 455  */
 456 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
 457 {
 458         struct stb0899_internal *internal = &state->internal;
 459         struct stb0899_params *params = &state->params;
 460
 461         int range_offst, tp_freq;
 462
 463         range_offst = internal->srch_range / 2000;
 464         tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
 465
 466         if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
 467                 internal->status = RANGEOK;
 468                 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
 469         } else {
 470                 internal->status = OUTOFRANGE;
 471                 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
 472         }
 473
 474         return internal->status;
 475 }
 476
 477 /*
 478  * NextSubRange
 479  * Compute the next subrange of the search
 480  */
 481 static void next_sub_range(struct stb0899_state *state)
 482 {
 483         struct stb0899_internal *internal = &state->internal;
 484         struct stb0899_params *params = &state->params;
 485
 486         long old_sub_range;
 487
 488         if (internal->sub_dir > 0) {
 489                 old_sub_range = internal->sub_range;
 490                 internal->sub_range = MIN((internal->srch_range / 2) -
 491                                           (internal->tuner_offst + internal->sub_range / 2),
 492                                            internal->sub_range);
 493
 494                 if (internal->sub_range < 0)
 495                         internal->sub_range = 0;
 496
 497                 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
 498         }
 499
 500         internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
 501         internal->sub_dir = -internal->sub_dir;
 502 }
 503
 504 /*
 505  * stb0899_dvbs_algo
 506  * Search for a signal, timing, carrier and data for a
 507  * given frequency in a given range
 508  */
 509 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
 510 {
 511         struct stb0899_params *params           = &state->params;
 512         struct stb0899_internal *internal       = &state->internal;
 513         struct stb0899_config *config           = state->config;
 514
 515         u8 bclc, reg;
 516         u8 cfr[2];
 517         u8 eq_const[10];
 518         s32 clnI = 3;
 519         u32 bandwidth = 0;
 520
 521         /* BETA values rated @ 99MHz    */
 522         s32 betaTab[5][4] = {
 523                /*  5   10   20   30MBps */
 524                 { 37,  34,  32,  31 }, /* QPSK 1/2      */
 525                 { 37,  35,  33,  31 }, /* QPSK 2/3      */
 526                 { 37,  35,  33,  31 }, /* QPSK 3/4      */
 527                 { 37,  36,  33,  32 }, /* QPSK 5/6      */
 528                 { 37,  36,  33,  32 }  /* QPSK 7/8      */
 529         };
 530
 531         internal->direction = 1;
 532
 533         stb0899_set_srate(state, internal->master_clk, params->srate);
 534         /* Carrier loop optimization versus symbol rate for acquisition*/
 535         if (params->srate <= 5000000) {
 536                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 537                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 538                 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
 539                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 540                 clnI = 0;
 541         } else if (params->srate <= 15000000) {
 542                 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
 543                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 544                 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
 545                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 546                 clnI = 1;
 547         } else if(params->srate <= 25000000) {
 548                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 549                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 550                 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
 551                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 552                 clnI = 2;
 553         } else {
 554                 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
 555                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 556                 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
 557                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 558                 clnI = 3;
 559         }
 560
 561         dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
 562         /* Set the timing loop to acquisition   */
 563         stb0899_write_reg(state, STB0899_RTC, 0x46);
 564         stb0899_write_reg(state, STB0899_CFD, 0xee);
 565
 566         /* !! WARNING !!
 567          * Do not read any status variables while acquisition,
 568          * If any needed, read before the acquisition starts
 569          * querying status while acquiring causes the
 570          * acquisition to go bad and hence no locks.
 571          */
 572         dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
 573                 internal->derot_percent, params->srate, internal->mclk);
 574
 575         /* Initial calculations */
 576         internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol  */
 577         internal->t_timing = stb0899_calc_loop_time(params->srate);
 578         internal->t_derot = stb0899_calc_derot_time(params->srate);
 579         internal->t_data = 500;
 580
 581         dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
 582         /* RESET Stream merger  */
 583         reg = stb0899_read_reg(state, STB0899_TSTRES);
 584         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
 585         stb0899_write_reg(state, STB0899_TSTRES, reg);
 586
 587         /*
 588          * Set KDIVIDER to an intermediate value between
 589          * 1/2 and 7/8 for acquisition
 590          */
 591         reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
 592         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
 593         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 594
 595         stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring  */
 596         stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
 597
 598         stb0899_first_subrange(state);
 599         do {
 600                 /* Initialisations      */
 601                 cfr[0] = cfr[1] = 0;
 602                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency   */
 603
 604                 stb0899_write_reg(state, STB0899_RTF, 0);
 605                 reg = stb0899_read_reg(state, STB0899_CFD);
 606                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 607                 stb0899_write_reg(state, STB0899_CFD, reg);
 608
 609                 internal->derot_freq = 0;
 610                 internal->status = NOAGC1;
 611
 612                 /* Move tuner to frequency      */
 613                 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
 614                 if (state->config->tuner_set_frequency)
 615                         state->config->tuner_set_frequency(&state->frontend, internal->freq);
 616
 617                 if (state->config->tuner_get_frequency)
 618                         state->config->tuner_get_frequency(&state->frontend, &internal->freq);
 619
 620                 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
 621                 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
 622                 internal->status = AGC1OK;
 623
 624                 /* There is signal in the band  */
 625                 if (config->tuner_get_bandwidth)
 626                         config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 627                 if (params->srate <= bandwidth / 2)
 628                         stb0899_search_tmg(state); /* For low rates (SCPC)      */
 629                 else
 630                         stb0899_check_tmg(state); /* For high rates (MCPC)      */
 631
 632                 if (internal->status == TIMINGOK) {
 633                         dprintk(state->verbose, FE_DEBUG, 1,
 634                                 "TIMING OK ! Derot freq=%d, mclk=%d",
 635                                 internal->derot_freq, internal->mclk);
 636
 637                         if (stb0899_search_carrier(state) == CARRIEROK) {       /* Search for carrier   */
 638                                 dprintk(state->verbose, FE_DEBUG, 1,
 639                                         "CARRIER OK ! Derot freq=%d, mclk=%d",
 640                                         internal->derot_freq, internal->mclk);
 641
 642                                 if (stb0899_search_data(state) == DATAOK) {     /* Check for data       */
 643                                         dprintk(state->verbose, FE_DEBUG, 1,
 644                                                 "DATA OK ! Derot freq=%d, mclk=%d",
 645                                                 internal->derot_freq, internal->mclk);
 646
 647                                         if (stb0899_check_range(state) == RANGEOK) {
 648                                                 dprintk(state->verbose, FE_DEBUG, 1,
 649                                                         "RANGE OK ! derot freq=%d, mclk=%d",
 650                                                         internal->derot_freq, internal->mclk);
 651
 652                                                 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
 653                                                 reg = stb0899_read_reg(state, STB0899_PLPARM);
 654                                                 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
 655                                                 dprintk(state->verbose, FE_DEBUG, 1,
 656                                                         "freq=%d, internal resultant freq=%d",
 657                                                         params->freq, internal->freq);
 658
 659                                                 dprintk(state->verbose, FE_DEBUG, 1,
 660                                                         "internal puncture rate=%d",
 661                                                         internal->fecrate);
 662                                         }
 663                                 }
 664                         }
 665                 }
 666                 if (internal->status != RANGEOK)
 667                         next_sub_range(state);
 668
 669         } while (internal->sub_range && internal->status != RANGEOK);
 670
 671         /* Set the timing loop to tracking      */
 672         stb0899_write_reg(state, STB0899_RTC, 0x33);
 673         stb0899_write_reg(state, STB0899_CFD, 0xf7);
 674         /* if locked and range ok, set Kdiv     */
 675         if (internal->status == RANGEOK) {
 676                 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
 677                 stb0899_write_reg(state, STB0899_EQON, 0x41);           /* Equalizer OFF while acquiring        */
 678                 stb0899_write_reg(state, STB0899_VITSYNC, 0x39);        /* SN to b'11 for acquisition           */
 679
 680                 /*
 681                  * Carrier loop optimization versus
 682                  * symbol Rate/Puncture Rate for Tracking
 683                  */
 684                 reg = stb0899_read_reg(state, STB0899_BCLC);
 685                 switch (internal->fecrate) {
 686                 case STB0899_FEC_1_2:           /* 13   */
 687                         stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
 688                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
 689                         stb0899_write_reg(state, STB0899_BCLC, reg);
 690                         break;
 691                 case STB0899_FEC_2_3:           /* 18   */
 692                         stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
 693                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
 694                         stb0899_write_reg(state, STB0899_BCLC, reg);
 695                         break;
 696                 case STB0899_FEC_3_4:           /* 21   */
 697                         stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
 698                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
 699                         stb0899_write_reg(state, STB0899_BCLC, reg);
 700                         break;
 701                 case STB0899_FEC_5_6:           /* 24   */
 702                         stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
 703                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
 704                         stb0899_write_reg(state, STB0899_BCLC, reg);
 705                         break;
 706                 case STB0899_FEC_6_7:           /* 25   */
 707                         stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
 708                         stb0899_write_reg(state, STB0899_ACLC, 0x88);
 709                         stb0899_write_reg(state, STB0899_BCLC, 0x9a);
 710                         break;
 711                 case STB0899_FEC_7_8:           /* 26   */
 712                         stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
 713                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
 714                         stb0899_write_reg(state, STB0899_BCLC, reg);
 715                         break;
 716                 default:
 717                         dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
 718                         break;
 719                 }
 720                 /* release stream merger RESET  */
 721                 reg = stb0899_read_reg(state, STB0899_TSTRES);
 722                 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
 723                 stb0899_write_reg(state, STB0899_TSTRES, reg);
 724
 725                 /* disable carrier detector     */
 726                 reg = stb0899_read_reg(state, STB0899_CFD);
 727                 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
 728                 stb0899_write_reg(state, STB0899_CFD, reg);
 729
 730                 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
 731         }
 732
 733         return internal->status;
 734 }
 735
 736 /*
 737  * stb0899_dvbs2_config_uwp
 738  * Configure UWP state machine
 739  */
 740 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
 741 {
 742         struct stb0899_internal *internal = &state->internal;
 743         struct stb0899_config *config = state->config;
 744         u32 uwp1, uwp2, uwp3, reg;
 745
 746         uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
 747         uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
 748         uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
 749
 750         STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
 751         STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
 752         STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
 753
 754         STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
 755         STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
 756         STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
 757
 758         STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
 759         STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
 760
 761         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
 762         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
 763         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
 764
 765         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
 766         STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
 767         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
 768 }
 769
 770 /*
 771  * stb0899_dvbs2_config_csm_auto
 772  * Set CSM to AUTO mode
 773  */
 774 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
 775 {
 776         u32 reg;
 777
 778         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
 779         STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
 780         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
 781 }
 782
 783 long Log2Int(int number)
 784 {
 785         int i;
 786
 787         i = 0;
 788         while ((1 << i) <= ABS(number))
 789                 i++;
 790
 791         if (number == 0)
 792                 i = 1;
 793
 794         return i - 1;
 795 }
 796
 797 /*
 798  * stb0899_dvbs2_calc_srate
 799  * compute BTR_NOM_FREQ for the symbol rate
 800  */
 801 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
 802 {
 803         struct stb0899_internal *internal       = &state->internal;
 804         struct stb0899_config *config           = state->config;
 805
 806         u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
 807         u32 master_clk, srate;
 808
 809         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 810         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 811         dec_rate = Log2Int(dec_ratio);
 812         decim = 1 << dec_rate;
 813         master_clk = internal->master_clk / 1000;
 814         srate = internal->srate / 1000;
 815
 816         if (decim <= 4) {
 817                 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
 818                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 819         } else {
 820                 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
 821                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 822         }
 823         btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
 824
 825         return btr_nom_freq;
 826 }
 827
 828 /*
 829  * stb0899_dvbs2_calc_dev
 830  * compute the correction to be applied to symbol rate
 831  */
 832 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
 833 {
 834         struct stb0899_internal *internal = &state->internal;
 835         u32 dec_ratio, correction, master_clk, srate;
 836
 837         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 838         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 839
 840         master_clk = internal->master_clk / 1000;       /* for integer Caculation*/
 841         srate = internal->srate / 1000; /* for integer Caculation*/
 842         correction = (512 * master_clk) / (2 * dec_ratio * srate);
 843
 844         return  correction;
 845 }
 846
 847 /*
 848  * stb0899_dvbs2_set_srate
 849  * Set DVBS2 symbol rate
 850  */
 851 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
 852 {
 853         struct stb0899_internal *internal = &state->internal;
 854
 855         u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
 856         u32 correction, freq_adj, band_lim, decim_cntrl, reg;
 857         u8 anti_alias;
 858
 859         /*set decimation to 1*/
 860         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 861         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 862         dec_rate = Log2Int(dec_ratio);
 863
 864         win_sel = 0;
 865         if (dec_rate >= 5)
 866                 win_sel = dec_rate - 4;
 867
 868         decim = (1 << dec_rate);
 869         /* (FSamp/Fsymbol *100) for integer Caculation */
 870         f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
 871
 872         if (f_sym <= 2250)      /* don't band limit signal going into btr block*/
 873                 band_lim = 1;
 874         else
 875                 band_lim = 0;   /* band limit signal going into btr block*/
 876
 877         decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
 878         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
 879
 880         if (f_sym <= 3450)
 881                 anti_alias = 0;
 882         else if (f_sym <= 4250)
 883                 anti_alias = 1;
 884         else
 885                 anti_alias = 2;
 886
 887         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
 888         btr_nom_freq = stb0899_dvbs2_calc_srate(state);
 889         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
 890
 891         correction = stb0899_dvbs2_calc_dev(state);
 892         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
 893         STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
 894         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
 895
 896         /* scale UWP+CSM frequency to sample rate*/
 897         freq_adj =  internal->srate / (internal->master_clk / 4096);
 898         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
 899 }
 900
 901 /*
 902  * stb0899_dvbs2_set_btr_loopbw
 903  * set bit timing loop bandwidth as a percentage of the symbol rate
 904  */
 905 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
 906 {
 907         struct stb0899_internal *internal       = &state->internal;
 908         struct stb0899_config *config           = state->config;
 909
 910         u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
 911         s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
 912         s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
 913         u32 decim, K, wn, k_direct, k_indirect;
 914         u32 reg;
 915
 916         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 917         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 918         dec_rate = Log2Int(dec_ratio);
 919         decim = (1 << dec_rate);
 920
 921         sym_peak *= 576000;
 922         K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
 923         K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
 924
 925         if (K != 0) {
 926                 K = sym_peak / K;
 927                 wn = (4 * zeta * zeta) + 1000000;
 928                 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/
 929
 930                 k_indirect = (wn * wn) / K;
 931                 k_indirect = k_indirect;          /*kindirect = kindirect 10^-6*/
 932                 k_direct   = (2 * wn * zeta) / K;       /*kDirect = kDirect 10^-2*/
 933                 k_direct  *= 100;
 934
 935                 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
 936                 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
 937                 k_btr1 = k_direct / (1 << k_direct_shift);
 938                 k_btr1 /= 10000;
 939
 940                 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
 941                 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
 942                 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
 943                 k_btr0 /= 1000000;
 944
 945                 k_btr2_rshft = 0;
 946                 if (k_btr0_rshft > 15) {
 947                         k_btr2_rshft = k_btr0_rshft - 15;
 948                         k_btr0_rshft = 15;
 949                 }
 950                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
 951                 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
 952                 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
 953                 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
 954                 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
 955                 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
 956                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
 957         } else
 958                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
 959 }
 960
 961 /*
 962  * stb0899_dvbs2_set_carr_freq
 963  * set nominal frequency for carrier search
 964  */
 965 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
 966 {
 967         struct stb0899_config *config = state->config;
 968         s32 crl_nom_freq;
 969         u32 reg;
 970
 971         crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
 972         crl_nom_freq *= carr_freq;
 973         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
 974         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
 975         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
 976 }
 977
 978 /*
 979  * stb0899_dvbs2_init_calc
 980  * Initialize DVBS2 UWP, CSM, carrier and timing loops
 981  */
 982 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
 983 {
 984         struct stb0899_internal *internal = &state->internal;
 985         s32 steps, step_size;
 986         u32 range, reg;
 987
 988         /* config uwp and csm */
 989         stb0899_dvbs2_config_uwp(state);
 990         stb0899_dvbs2_config_csm_auto(state);
 991
 992         /* initialize BTR       */
 993         stb0899_dvbs2_set_srate(state);
 994         stb0899_dvbs2_set_btr_loopbw(state);
 995
 996         if (internal->srate / 1000000 >= 15)
 997                 step_size = (1 << 17) / 5;
 998         else if (internal->srate / 1000000 >= 10)
 999                 step_size = (1 << 17) / 7;
1000         else if (internal->srate / 1000000 >= 5)
1001                 step_size = (1 << 17) / 10;
1002         else
1003                 step_size = (1 << 17) / 4;
1004
1005         range = internal->srch_range / 1000000;
1006         steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1007         steps = (steps + 6) / 10;
1008         steps = (steps == 0) ? 1 : steps;
1009         if (steps % 2 == 0)
1010                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1011                                            (internal->step_size * (internal->srate / 20000000)),
1012                                            (internal->master_clk) / 1000000);
1013         else
1014                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1015
1016         /*Set Carrier Search params (zigzag, num steps and freq step size*/
1017         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1018         STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1019         STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1020         STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1021         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1022 }
1023
1024 /*
1025  * stb0899_dvbs2_btr_init
1026  * initialize the timing loop
1027  */
1028 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1029 {
1030         u32 reg;
1031
1032         /* set enable BTR loopback      */
1033         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1034         STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1035         STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1036         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1037
1038         /* fix btr freq accum at 0      */
1039         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1040         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1041
1042         /* fix btr freq accum at 0      */
1043         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1044         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1045 }
1046
1047 /*
1048  * stb0899_dvbs2_reacquire
1049  * trigger a DVB-S2 acquisition
1050  */
1051 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1052 {
1053         u32 reg = 0;
1054
1055         /* demod soft reset     */
1056         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1057         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1058
1059         /*Reset Timing Loop     */
1060         stb0899_dvbs2_btr_init(state);
1061
1062         /* reset Carrier loop   */
1063         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1064         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1065         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1066         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1067         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1068
1069         /*release demod soft reset      */
1070         reg = 0;
1071         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1072         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1073
1074         /* start acquisition process    */
1075         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1076         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1077
1078         /* equalizer Init       */
1079         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1080
1081         /*Start equilizer       */
1082         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1083
1084         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1085         STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1086         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1087         STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1088         STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1089         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1090
1091         /* RESET Packet delineator      */
1092         stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1093 }
1094
1095 /*
1096  * stb0899_dvbs2_get_dmd_status
1097  * get DVB-S2 Demod LOCK status
1098  */
1099 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1100 {
1101         int time = -10, lock = 0, uwp, csm;
1102         u32 reg;
1103
1104         do {
1105                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1106                 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1107                 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1108                         dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1109                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1110                 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1111                 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1112                 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1113                 if (uwp && csm)
1114                         lock = 1;
1115
1116                 time += 10;
1117                 msleep(10);
1118
1119         } while ((!lock) && (time <= timeout));
1120
1121         if (lock) {
1122                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1123                 return DVBS2_DEMOD_LOCK;
1124         } else {
1125                 return DVBS2_DEMOD_NOLOCK;
1126         }
1127 }
1128
1129 /*
1130  * stb0899_dvbs2_get_data_lock
1131  * get FEC status
1132  */
1133 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1134 {
1135         int time = 0, lock = 0;
1136         u8 reg;
1137
1138         while ((!lock) && (time < timeout)) {
1139                 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1140                 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1141                 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1142                 time++;
1143         }
1144
1145         return lock;
1146 }
1147
1148 /*
1149  * stb0899_dvbs2_get_fec_status
1150  * get DVB-S2 FEC LOCK status
1151  */
1152 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1153 {
1154         int time = 0, Locked;
1155
1156         do {
1157                 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1158                 time++;
1159                 msleep(1);
1160
1161         } while ((!Locked) && (time < timeout));
1162
1163         if (Locked) {
1164                 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1165                 return DVBS2_FEC_LOCK;
1166         } else {
1167                 return DVBS2_FEC_NOLOCK;
1168         }
1169 }
1170
1171
1172 /*
1173  * stb0899_dvbs2_init_csm
1174  * set parameters for manual mode
1175  */
1176 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1177 {
1178         struct stb0899_internal *internal = &state->internal;
1179
1180         s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1181         s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1182         u32 csm1, csm2, csm3, csm4;
1183
1184         if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1185                 switch (modcod) {
1186                 case STB0899_QPSK_12:
1187                         gamma_acq               = 25;
1188                         gamma_rho_acq           = 2700;
1189                         gamma_trk               = 12;
1190                         gamma_rho_trk           = 180;
1191                         lock_count_thr          = 8;
1192                         break;
1193                 case STB0899_QPSK_35:
1194                         gamma_acq               = 38;
1195                         gamma_rho_acq           = 7182;
1196                         gamma_trk               = 14;
1197                         gamma_rho_trk           = 308;
1198                         lock_count_thr          = 8;
1199                         break;
1200                 case STB0899_QPSK_23:
1201                         gamma_acq               = 42;
1202                         gamma_rho_acq           = 9408;
1203                         gamma_trk               = 17;
1204                         gamma_rho_trk           = 476;
1205                         lock_count_thr          = 8;
1206                         break;
1207                 case STB0899_QPSK_34:
1208                         gamma_acq               = 53;
1209                         gamma_rho_acq           = 16642;
1210                         gamma_trk               = 19;
1211                         gamma_rho_trk           = 646;
1212                         lock_count_thr          = 8;
1213                         break;
1214                 case STB0899_QPSK_45:
1215                         gamma_acq               = 53;
1216                         gamma_rho_acq           = 17119;
1217                         gamma_trk               = 22;
1218                         gamma_rho_trk           = 880;
1219                         lock_count_thr          = 8;
1220                         break;
1221                 case STB0899_QPSK_56:
1222                         gamma_acq               = 55;
1223                         gamma_rho_acq           = 19250;
1224                         gamma_trk               = 23;
1225                         gamma_rho_trk           = 989;
1226                         lock_count_thr          = 8;
1227                         break;
1228                 case STB0899_QPSK_89:
1229                         gamma_acq               = 60;
1230                         gamma_rho_acq           = 24240;
1231                         gamma_trk               = 24;
1232                         gamma_rho_trk           = 1176;
1233                         lock_count_thr          = 8;
1234                         break;
1235                 case STB0899_QPSK_910:
1236                         gamma_acq               = 66;
1237                         gamma_rho_acq           = 29634;
1238                         gamma_trk               = 24;
1239                         gamma_rho_trk           = 1176;
1240                         lock_count_thr          = 8;
1241                         break;
1242                 default:
1243                         gamma_acq               = 66;
1244                         gamma_rho_acq           = 29634;
1245                         gamma_trk               = 24;
1246                         gamma_rho_trk           = 1176;
1247                         lock_count_thr          = 8;
1248                         break;
1249                 }
1250
1251                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1252                 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1253                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1254
1255                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1256                 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1257                 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1258                 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1259
1260                 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1261                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1262                 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1263                 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1264                 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1265                 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1266                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1267                 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1268                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1269                 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1270                 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1271
1272                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1273                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1274                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1275                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1276         }
1277 }
1278
1279 /*
1280  * stb0899_dvbs2_get_srate
1281  * get DVB-S2 Symbol Rate
1282  */
1283 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1284 {
1285         struct stb0899_internal *internal = &state->internal;
1286         struct stb0899_config *config = state->config;
1287
1288         u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1289         int div1, div2, rem1, rem2;
1290
1291         div1 = config->btr_nco_bits / 2;
1292         div2 = config->btr_nco_bits - div1 - 1;
1293
1294         bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1295
1296         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1297         decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1298         decimRate = (1 << decimRate);
1299
1300         intval1 = internal->master_clk / (1 << div1);
1301         intval2 = bTrNomFreq / (1 << div2);
1302
1303         rem1 = internal->master_clk % (1 << div1);
1304         rem2 = bTrNomFreq % (1 << div2);
1305         /* only for integer calculation */
1306         srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1307         srate /= decimRate;     /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1308
1309         return  srate;
1310 }
1311
1312 /*
1313  * stb0899_dvbs2_algo
1314  * Search for signal, timing, carrier and data for a given
1315  * frequency in a given range
1316  */
1317 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1318 {
1319         struct stb0899_internal *internal = &state->internal;
1320         enum stb0899_modcod modcod;
1321
1322         s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1323         int i = 0;
1324         u32 reg, csm1;
1325
1326         if (internal->srate <= 2000000) {
1327                 searchTime      = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs           */
1328                 FecLockTime     = 350;  /* 350  ms max time to lock FEC, SYMB <= 2Mbs                   */
1329         } else if (internal->srate <= 5000000) {
1330                 searchTime      = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs    */
1331                 FecLockTime     = 170;  /* 170  ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs             */
1332         } else if (internal->srate <= 10000000) {
1333                 searchTime      = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs    */
1334                 FecLockTime     = 80;   /* 80  ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs             */
1335         } else if (internal->srate <= 15000000) {
1336                 searchTime      = 500;  /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs    */
1337                 FecLockTime     = 50;   /* 50  ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs            */
1338         } else if (internal->srate <= 20000000) {
1339                 searchTime      = 300;  /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs   */
1340                 FecLockTime     = 30;   /* 50  ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs            */
1341         } else if (internal->srate <= 25000000) {
1342                 searchTime      = 250;  /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs  */
1343                 FecLockTime     = 25;   /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1344         } else {
1345                 searchTime      = 150;  /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs            */
1346                 FecLockTime     = 20;   /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1347         }
1348
1349         /* Maintain Stream Merger in reset during acquisition   */
1350         reg = stb0899_read_reg(state, STB0899_TSTRES);
1351         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1352         stb0899_write_reg(state, STB0899_TSTRES, reg);
1353
1354         /* Move tuner to frequency      */
1355         if (state->config->tuner_set_frequency)
1356                 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1357         if (state->config->tuner_get_frequency)
1358                 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1359
1360         /* Set IF AGC to acquisition    */
1361         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1362         STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1363         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1364         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1365
1366         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1367         STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1368         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1369
1370         /* Initialisation       */
1371         stb0899_dvbs2_init_calc(state);
1372
1373         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1374         switch (internal->inversion) {
1375         case IQ_SWAP_OFF:
1376                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1377                 break;
1378         case IQ_SWAP_ON:
1379                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1380                 break;
1381         case IQ_SWAP_AUTO:      /* use last successful search first     */
1382                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1383                 break;
1384         }
1385         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1386         stb0899_dvbs2_reacquire(state);
1387
1388         /* Wait for demod lock (UWP and CSM)    */
1389         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1390
1391         if (internal->status == DVBS2_DEMOD_LOCK) {
1392                 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1393                 i = 0;
1394                 /* Demod Locked, check FEC status       */
1395                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1396
1397                 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1398                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1399                         /*      Read the frequency offset*/
1400                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1401
1402                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1403                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1404                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1405                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1406                         stb0899_dvbs2_reacquire(state);
1407                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1408                         i++;
1409                 }
1410         }
1411
1412         if (internal->status != DVBS2_FEC_LOCK) {
1413                 if (internal->inversion == IQ_SWAP_AUTO) {
1414                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1415                         iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1416                         /* IQ Spectrum Inversion        */
1417                         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1418                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1419                         /* start acquistion process     */
1420                         stb0899_dvbs2_reacquire(state);
1421
1422                         /* Wait for demod lock (UWP and CSM)    */
1423                         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1424                         if (internal->status == DVBS2_DEMOD_LOCK) {
1425                                 i = 0;
1426                                 /* Demod Locked, check FEC      */
1427                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1428                                 /*try thrice for false locks, (UWP and CSM Locked but no FEC)   */
1429                                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1430                                         /*      Read the frequency offset*/
1431                                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1432
1433                                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1434                                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1435                                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1436                                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1437
1438                                         stb0899_dvbs2_reacquire(state);
1439                                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1440                                         i++;
1441                                 }
1442                         }
1443 /*
1444                         if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1445                                 pParams->IQLocked = !iqSpectrum;
1446 */
1447                 }
1448         }
1449         if (internal->status == DVBS2_FEC_LOCK) {
1450                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1451                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1452                 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1453                 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1454
1455                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1456                       (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1457                       (pilots == 1)) {
1458
1459                         stb0899_dvbs2_init_csm(state, pilots, modcod);
1460                         /* Wait for UWP,CSM and data LOCK 20ms max      */
1461                         internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1462
1463                         i = 0;
1464                         while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1465                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1466                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1467                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1468                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1469                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1470                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1471
1472                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1473                                 i++;
1474                         }
1475                 }
1476
1477                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1478                       (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1479                       (pilots == 1)) {
1480
1481                         /* Equalizer Disable update      */
1482                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1483                         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1484                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1485                 }
1486
1487                 /* slow down the Equalizer once locked  */
1488                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1489                 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1490                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1491
1492                 /* Store signal parameters      */
1493                 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1494
1495                 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1496                 offsetfreq *= (internal->master_clk / 1000000);
1497                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1498                 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1499                         offsetfreq *= -1;
1500
1501                 internal->freq = internal->freq - offsetfreq;
1502                 internal->srate = stb0899_dvbs2_get_srate(state);
1503
1504                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1505                 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1506                 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1507                 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1508
1509                  /* Set IF AGC to tracking      */
1510                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1511                 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1512
1513                 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1514                 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1515                         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1516
1517                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1518
1519                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1520                 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1521                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1522         }
1523
1524         /* Release Stream Merger Reset          */
1525         reg = stb0899_read_reg(state, STB0899_TSTRES);
1526         STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1527         stb0899_write_reg(state, STB0899_TSTRES, reg);
1528
1529         return internal->status;
1530 }