2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
30 VERSION 1.2 <2002/11/30>
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
37 VERSION 1.6LK <2004/04/14>
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
45 VERSION 2.2LK <2005/01/25>
47 - RX csum, TX csum/SG, TSO
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
72 #ifdef CONFIG_R8169_NAPI
73 #define NAPI_SUFFIX "-NAPI"
75 #define NAPI_SUFFIX ""
78 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
79 #define MODULENAME "r8169"
80 #define PFX MODULENAME ": "
83 #define assert(expr) \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
88 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
90 #define assert(expr) do {} while (0)
91 #define dprintk(fmt, args...) do {} while (0)
92 #endif /* RTL8169_DEBUG */
94 #define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
97 #define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
100 #ifdef CONFIG_R8169_NAPI
101 #define rtl8169_rx_skb netif_receive_skb
102 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
103 #define rtl8169_rx_quota(count, quota) min(count, quota)
105 #define rtl8169_rx_skb netif_rx
106 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
107 #define rtl8169_rx_quota(count, quota) count
112 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113 static int num_media = 0;
115 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116 static const int max_interrupt_work = 20;
118 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120 static const int multicast_filter_limit = 32;
122 /* MAC address length */
123 #define MAC_ADDR_LEN 6
125 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
133 #define R8169_REGS_SIZE 256
134 #define R8169_NAPI_WEIGHT 64
135 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
138 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
141 #define RTL8169_TX_TIMEOUT (6*HZ)
142 #define RTL8169_PHY_TIMEOUT (10*HZ)
144 /* write/read MMIO register */
145 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148 #define RTL_R8(reg) readb (ioaddr + (reg))
149 #define RTL_R16(reg) readw (ioaddr + (reg))
150 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
170 #define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
173 static const struct {
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177 } rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
185 static struct pci_device_id rtl8169_pci_tbl[] = {
186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), },
188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
189 { PCI_DEVICE(0x16ec, 0x0116), },
190 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
194 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
196 static int rx_copybreak = 200;
202 enum RTL8169_registers {
203 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
236 RxDescAddrLow = 0xE4,
237 RxDescAddrHigh = 0xE8,
240 FuncEventMask = 0xF4,
241 FuncPresetState = 0xF8,
242 FuncForceEvent = 0xFC,
245 enum RTL8169_register_content {
246 /* InterruptStatusBits */
250 TxDescUnavail = 0x80,
273 Cfg9346_Unlock = 0xC0,
278 AcceptBroadcast = 0x08,
279 AcceptMulticast = 0x04,
281 AcceptAllPhys = 0x01,
288 TxInterFrameGapShift = 24,
289 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
291 /* Config1 register p.24 */
292 PMEnable = (1 << 0), /* Power Management Enable */
294 /* Config3 register p.25 */
295 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
296 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
298 /* Config5 register p.27 */
299 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
300 MWF = (1 << 5), /* Accept Multicast wakeup frame */
301 UWF = (1 << 4), /* Accept Unicast wakeup frame */
302 LanWake = (1 << 1), /* LanWake enable/disable */
303 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
306 TBIReset = 0x80000000,
307 TBILoopback = 0x40000000,
308 TBINwEnable = 0x20000000,
309 TBINwRestart = 0x10000000,
310 TBILinkOk = 0x02000000,
311 TBINwComplete = 0x01000000,
319 /* rtl8169_PHYstatus */
329 /* GIGABIT_PHY_registers */
332 PHY_AUTO_NEGO_REG = 4,
333 PHY_1000_CTRL_REG = 9,
335 /* GIGABIT_PHY_REG_BIT */
336 PHY_Restart_Auto_Nego = 0x0200,
337 PHY_Enable_Auto_Nego = 0x1000,
339 /* PHY_STAT_REG = 1 */
340 PHY_Auto_Neco_Comp = 0x0020,
342 /* PHY_AUTO_NEGO_REG = 4 */
343 PHY_Cap_10_Half = 0x0020,
344 PHY_Cap_10_Full = 0x0040,
345 PHY_Cap_100_Half = 0x0080,
346 PHY_Cap_100_Full = 0x0100,
348 /* PHY_1000_CTRL_REG = 9 */
349 PHY_Cap_1000_Full = 0x0200,
361 TBILinkOK = 0x02000000,
363 /* DumpCounterCommand */
367 enum _DescStatusBit {
368 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
369 RingEnd = (1 << 30), /* End of descriptor ring */
370 FirstFrag = (1 << 29), /* First segment of a packet */
371 LastFrag = (1 << 28), /* Final segment of a packet */
374 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
375 MSSShift = 16, /* MSS value position */
376 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
377 IPCS = (1 << 18), /* Calculate IP checksum */
378 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
379 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
380 TxVlanTag = (1 << 17), /* Add VLAN tag */
383 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
384 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
386 #define RxProtoUDP (PID1)
387 #define RxProtoTCP (PID0)
388 #define RxProtoIP (PID1 | PID0)
389 #define RxProtoMask RxProtoIP
391 IPFail = (1 << 16), /* IP checksum failed */
392 UDPFail = (1 << 15), /* UDP/IP checksum failed */
393 TCPFail = (1 << 14), /* TCP/IP checksum failed */
394 RxVlanTag = (1 << 16), /* VLAN tag available */
397 #define RsvdMask 0x3fffc000
414 u8 __pad[sizeof(void *) - sizeof(u32)];
417 struct rtl8169_private {
418 void __iomem *mmio_addr; /* memory map physical address */
419 struct pci_dev *pci_dev; /* Index of PCI device */
420 struct net_device_stats stats; /* statistics of net device */
421 spinlock_t lock; /* spin lock flag */
426 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
427 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
430 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
431 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
432 dma_addr_t TxPhyAddr;
433 dma_addr_t RxPhyAddr;
434 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
435 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
437 struct timer_list timer;
440 int phy_auto_nego_reg;
441 int phy_1000_ctrl_reg;
442 #ifdef CONFIG_R8169_VLAN
443 struct vlan_group *vlgrp;
445 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
446 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
447 void (*phy_reset_enable)(void __iomem *);
448 unsigned int (*phy_reset_pending)(void __iomem *);
449 unsigned int (*link_ok)(void __iomem *);
450 struct work_struct task;
451 unsigned wol_enabled : 1;
454 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
455 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
456 module_param_array(media, int, &num_media, 0);
457 MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
458 module_param(rx_copybreak, int, 0);
459 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
460 module_param(use_dac, int, 0);
461 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
462 module_param_named(debug, debug.msg_enable, int, 0);
463 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
464 MODULE_LICENSE("GPL");
465 MODULE_VERSION(RTL8169_VERSION);
467 static int rtl8169_open(struct net_device *dev);
468 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
469 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
470 struct pt_regs *regs);
471 static int rtl8169_init_ring(struct net_device *dev);
472 static void rtl8169_hw_start(struct net_device *dev);
473 static int rtl8169_close(struct net_device *dev);
474 static void rtl8169_set_rx_mode(struct net_device *dev);
475 static void rtl8169_tx_timeout(struct net_device *dev);
476 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
477 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
479 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
480 static void rtl8169_down(struct net_device *dev);
482 #ifdef CONFIG_R8169_NAPI
483 static int rtl8169_poll(struct net_device *dev, int *budget);
486 static const u16 rtl8169_intr_mask =
487 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
488 static const u16 rtl8169_napi_event =
489 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
490 static const unsigned int rtl8169_rx_config =
491 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
493 #define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
494 #define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
495 #define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
496 #define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
498 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
502 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
504 for (i = 20; i > 0; i--) {
505 /* Check if the RTL8169 has completed writing to the specified MII register */
506 if (!(RTL_R32(PHYAR) & 0x80000000))
512 static int mdio_read(void __iomem *ioaddr, int RegAddr)
516 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
518 for (i = 20; i > 0; i--) {
519 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
520 if (RTL_R32(PHYAR) & 0x80000000) {
521 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
529 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
531 RTL_W16(IntrMask, 0x0000);
533 RTL_W16(IntrStatus, 0xffff);
536 static void rtl8169_asic_down(void __iomem *ioaddr)
538 RTL_W8(ChipCmd, 0x00);
539 rtl8169_irq_mask_and_ack(ioaddr);
543 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
545 return RTL_R32(TBICSR) & TBIReset;
548 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
550 return mdio_read(ioaddr, 0) & 0x8000;
553 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
555 return RTL_R32(TBICSR) & TBILinkOk;
558 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
560 return RTL_R8(PHYstatus) & LinkStatus;
563 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
565 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
568 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
572 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
573 mdio_write(ioaddr, PHY_CTRL_REG, val);
576 static void rtl8169_check_link_status(struct net_device *dev,
577 struct rtl8169_private *tp, void __iomem *ioaddr)
581 spin_lock_irqsave(&tp->lock, flags);
582 if (tp->link_ok(ioaddr)) {
583 netif_carrier_on(dev);
584 if (netif_msg_ifup(tp))
585 printk(KERN_INFO PFX "%s: link up\n", dev->name);
587 if (netif_msg_ifdown(tp))
588 printk(KERN_INFO PFX "%s: link down\n", dev->name);
589 netif_carrier_off(dev);
591 spin_unlock_irqrestore(&tp->lock, flags);
594 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
601 } link_settings[] = {
602 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
603 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
604 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
605 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
606 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
608 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
610 unsigned char option;
612 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
614 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
615 printk(KERN_WARNING PFX "media option is deprecated.\n");
617 for (p = link_settings; p->media != 0xff; p++) {
618 if (p->media == option)
621 *autoneg = p->autoneg;
626 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
628 struct rtl8169_private *tp = netdev_priv(dev);
629 void __iomem *ioaddr = tp->mmio_addr;
634 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
635 wol->supported = WAKE_ANY;
637 spin_lock_irq(&tp->lock);
639 options = RTL_R8(Config1);
640 if (!(options & PMEnable))
643 options = RTL_R8(Config3);
644 if (options & LinkUp)
645 wol->wolopts |= WAKE_PHY;
646 if (options & MagicPacket)
647 wol->wolopts |= WAKE_MAGIC;
649 options = RTL_R8(Config5);
651 wol->wolopts |= WAKE_UCAST;
653 wol->wolopts |= WAKE_BCAST;
655 wol->wolopts |= WAKE_MCAST;
658 spin_unlock_irq(&tp->lock);
661 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
671 { WAKE_ANY, Config1, PMEnable },
672 { WAKE_PHY, Config3, LinkUp },
673 { WAKE_MAGIC, Config3, MagicPacket },
674 { WAKE_UCAST, Config5, UWF },
675 { WAKE_BCAST, Config5, BWF },
676 { WAKE_MCAST, Config5, MWF },
677 { WAKE_ANY, Config5, LanWake }
680 spin_lock_irq(&tp->lock);
682 RTL_W8(Cfg9346, Cfg9346_Unlock);
684 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
685 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
686 if (wol->wolopts & cfg[i].opt)
687 options |= cfg[i].mask;
688 RTL_W8(cfg[i].reg, options);
691 RTL_W8(Cfg9346, Cfg9346_Lock);
693 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
695 spin_unlock_irq(&tp->lock);
700 static void rtl8169_get_drvinfo(struct net_device *dev,
701 struct ethtool_drvinfo *info)
703 struct rtl8169_private *tp = netdev_priv(dev);
705 strcpy(info->driver, MODULENAME);
706 strcpy(info->version, RTL8169_VERSION);
707 strcpy(info->bus_info, pci_name(tp->pci_dev));
710 static int rtl8169_get_regs_len(struct net_device *dev)
712 return R8169_REGS_SIZE;
715 static int rtl8169_set_speed_tbi(struct net_device *dev,
716 u8 autoneg, u16 speed, u8 duplex)
718 struct rtl8169_private *tp = netdev_priv(dev);
719 void __iomem *ioaddr = tp->mmio_addr;
723 reg = RTL_R32(TBICSR);
724 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
725 (duplex == DUPLEX_FULL)) {
726 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
727 } else if (autoneg == AUTONEG_ENABLE)
728 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
730 if (netif_msg_link(tp)) {
731 printk(KERN_WARNING "%s: "
732 "incorrect speed setting refused in TBI mode\n",
741 static int rtl8169_set_speed_xmii(struct net_device *dev,
742 u8 autoneg, u16 speed, u8 duplex)
744 struct rtl8169_private *tp = netdev_priv(dev);
745 void __iomem *ioaddr = tp->mmio_addr;
746 int auto_nego, giga_ctrl;
748 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
749 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
750 PHY_Cap_100_Half | PHY_Cap_100_Full);
751 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
752 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
754 if (autoneg == AUTONEG_ENABLE) {
755 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
756 PHY_Cap_100_Half | PHY_Cap_100_Full);
757 giga_ctrl |= PHY_Cap_1000_Full;
759 if (speed == SPEED_10)
760 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
761 else if (speed == SPEED_100)
762 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
763 else if (speed == SPEED_1000)
764 giga_ctrl |= PHY_Cap_1000_Full;
766 if (duplex == DUPLEX_HALF)
767 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
769 if (duplex == DUPLEX_FULL)
770 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
773 tp->phy_auto_nego_reg = auto_nego;
774 tp->phy_1000_ctrl_reg = giga_ctrl;
776 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
777 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
778 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
779 PHY_Restart_Auto_Nego);
783 static int rtl8169_set_speed(struct net_device *dev,
784 u8 autoneg, u16 speed, u8 duplex)
786 struct rtl8169_private *tp = netdev_priv(dev);
789 ret = tp->set_speed(dev, autoneg, speed, duplex);
791 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
792 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
797 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
799 struct rtl8169_private *tp = netdev_priv(dev);
803 spin_lock_irqsave(&tp->lock, flags);
804 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
805 spin_unlock_irqrestore(&tp->lock, flags);
810 static u32 rtl8169_get_rx_csum(struct net_device *dev)
812 struct rtl8169_private *tp = netdev_priv(dev);
814 return tp->cp_cmd & RxChkSum;
817 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
823 spin_lock_irqsave(&tp->lock, flags);
826 tp->cp_cmd |= RxChkSum;
828 tp->cp_cmd &= ~RxChkSum;
830 RTL_W16(CPlusCmd, tp->cp_cmd);
833 spin_unlock_irqrestore(&tp->lock, flags);
838 #ifdef CONFIG_R8169_VLAN
840 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
843 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
844 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
847 static void rtl8169_vlan_rx_register(struct net_device *dev,
848 struct vlan_group *grp)
850 struct rtl8169_private *tp = netdev_priv(dev);
851 void __iomem *ioaddr = tp->mmio_addr;
854 spin_lock_irqsave(&tp->lock, flags);
857 tp->cp_cmd |= RxVlan;
859 tp->cp_cmd &= ~RxVlan;
860 RTL_W16(CPlusCmd, tp->cp_cmd);
862 spin_unlock_irqrestore(&tp->lock, flags);
865 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
867 struct rtl8169_private *tp = netdev_priv(dev);
870 spin_lock_irqsave(&tp->lock, flags);
872 tp->vlgrp->vlan_devices[vid] = NULL;
873 spin_unlock_irqrestore(&tp->lock, flags);
876 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
879 u32 opts2 = le32_to_cpu(desc->opts2);
882 if (tp->vlgrp && (opts2 & RxVlanTag)) {
883 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
884 swab16(opts2 & 0xffff));
892 #else /* !CONFIG_R8169_VLAN */
894 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
900 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
908 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
910 struct rtl8169_private *tp = netdev_priv(dev);
911 void __iomem *ioaddr = tp->mmio_addr;
915 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
916 cmd->port = PORT_FIBRE;
917 cmd->transceiver = XCVR_INTERNAL;
919 status = RTL_R32(TBICSR);
920 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
921 cmd->autoneg = !!(status & TBINwEnable);
923 cmd->speed = SPEED_1000;
924 cmd->duplex = DUPLEX_FULL; /* Always set */
927 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
929 struct rtl8169_private *tp = netdev_priv(dev);
930 void __iomem *ioaddr = tp->mmio_addr;
933 cmd->supported = SUPPORTED_10baseT_Half |
934 SUPPORTED_10baseT_Full |
935 SUPPORTED_100baseT_Half |
936 SUPPORTED_100baseT_Full |
937 SUPPORTED_1000baseT_Full |
942 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
944 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
945 cmd->advertising |= ADVERTISED_10baseT_Half;
946 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
947 cmd->advertising |= ADVERTISED_10baseT_Full;
948 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
949 cmd->advertising |= ADVERTISED_100baseT_Half;
950 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
951 cmd->advertising |= ADVERTISED_100baseT_Full;
952 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
953 cmd->advertising |= ADVERTISED_1000baseT_Full;
955 status = RTL_R8(PHYstatus);
957 if (status & _1000bpsF)
958 cmd->speed = SPEED_1000;
959 else if (status & _100bps)
960 cmd->speed = SPEED_100;
961 else if (status & _10bps)
962 cmd->speed = SPEED_10;
964 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
965 DUPLEX_FULL : DUPLEX_HALF;
968 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
970 struct rtl8169_private *tp = netdev_priv(dev);
973 spin_lock_irqsave(&tp->lock, flags);
975 tp->get_settings(dev, cmd);
977 spin_unlock_irqrestore(&tp->lock, flags);
981 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
984 struct rtl8169_private *tp = netdev_priv(dev);
987 if (regs->len > R8169_REGS_SIZE)
988 regs->len = R8169_REGS_SIZE;
990 spin_lock_irqsave(&tp->lock, flags);
991 memcpy_fromio(p, tp->mmio_addr, regs->len);
992 spin_unlock_irqrestore(&tp->lock, flags);
995 static u32 rtl8169_get_msglevel(struct net_device *dev)
997 struct rtl8169_private *tp = netdev_priv(dev);
999 return tp->msg_enable;
1002 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1004 struct rtl8169_private *tp = netdev_priv(dev);
1006 tp->msg_enable = value;
1009 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1016 "tx_single_collisions",
1017 "tx_multi_collisions",
1025 struct rtl8169_counters {
1032 u32 tx_one_collision;
1033 u32 tx_multi_collision;
1041 static int rtl8169_get_stats_count(struct net_device *dev)
1043 return ARRAY_SIZE(rtl8169_gstrings);
1046 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1047 struct ethtool_stats *stats, u64 *data)
1049 struct rtl8169_private *tp = netdev_priv(dev);
1050 void __iomem *ioaddr = tp->mmio_addr;
1051 struct rtl8169_counters *counters;
1057 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1061 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1062 cmd = (u64)paddr & DMA_32BIT_MASK;
1063 RTL_W32(CounterAddrLow, cmd);
1064 RTL_W32(CounterAddrLow, cmd | CounterDump);
1066 while (RTL_R32(CounterAddrLow) & CounterDump) {
1067 if (msleep_interruptible(1))
1071 RTL_W32(CounterAddrLow, 0);
1072 RTL_W32(CounterAddrHigh, 0);
1074 data[0] = le64_to_cpu(counters->tx_packets);
1075 data[1] = le64_to_cpu(counters->rx_packets);
1076 data[2] = le64_to_cpu(counters->tx_errors);
1077 data[3] = le32_to_cpu(counters->rx_errors);
1078 data[4] = le16_to_cpu(counters->rx_missed);
1079 data[5] = le16_to_cpu(counters->align_errors);
1080 data[6] = le32_to_cpu(counters->tx_one_collision);
1081 data[7] = le32_to_cpu(counters->tx_multi_collision);
1082 data[8] = le64_to_cpu(counters->rx_unicast);
1083 data[9] = le64_to_cpu(counters->rx_broadcast);
1084 data[10] = le32_to_cpu(counters->rx_multicast);
1085 data[11] = le16_to_cpu(counters->tx_aborted);
1086 data[12] = le16_to_cpu(counters->tx_underun);
1088 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1091 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1095 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1101 static struct ethtool_ops rtl8169_ethtool_ops = {
1102 .get_drvinfo = rtl8169_get_drvinfo,
1103 .get_regs_len = rtl8169_get_regs_len,
1104 .get_link = ethtool_op_get_link,
1105 .get_settings = rtl8169_get_settings,
1106 .set_settings = rtl8169_set_settings,
1107 .get_msglevel = rtl8169_get_msglevel,
1108 .set_msglevel = rtl8169_set_msglevel,
1109 .get_rx_csum = rtl8169_get_rx_csum,
1110 .set_rx_csum = rtl8169_set_rx_csum,
1111 .get_tx_csum = ethtool_op_get_tx_csum,
1112 .set_tx_csum = ethtool_op_set_tx_csum,
1113 .get_sg = ethtool_op_get_sg,
1114 .set_sg = ethtool_op_set_sg,
1115 .get_tso = ethtool_op_get_tso,
1116 .set_tso = ethtool_op_set_tso,
1117 .get_regs = rtl8169_get_regs,
1118 .get_wol = rtl8169_get_wol,
1119 .set_wol = rtl8169_set_wol,
1120 .get_strings = rtl8169_get_strings,
1121 .get_stats_count = rtl8169_get_stats_count,
1122 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1123 .get_perm_addr = ethtool_op_get_perm_addr,
1126 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1131 val = mdio_read(ioaddr, reg);
1132 val = (bitval == 1) ?
1133 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1134 mdio_write(ioaddr, reg, val & 0xffff);
1137 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1143 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1144 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1145 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1146 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1150 reg = RTL_R32(TxConfig) & 0x7c800000;
1151 while ((reg & p->mask) != p->mask)
1153 tp->mac_version = p->mac_version;
1156 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1162 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1163 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1164 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1168 for (p = mac_print; p->msg; p++) {
1169 if (tp->mac_version == p->version) {
1170 dprintk("mac_version == %s (%04d)\n", p->msg,
1175 dprintk("mac_version == Unknown\n");
1178 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1185 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1186 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1187 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1188 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1192 reg = mdio_read(ioaddr, 3) & 0xffff;
1193 while ((reg & p->mask) != p->set)
1195 tp->phy_version = p->phy_version;
1198 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1205 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1206 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1207 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1208 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1212 for (p = phy_print; p->msg; p++) {
1213 if (tp->phy_version == p->version) {
1214 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1218 dprintk("phy_version == Unknown\n");
1221 static void rtl8169_hw_phy_config(struct net_device *dev)
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224 void __iomem *ioaddr = tp->mmio_addr;
1226 u16 regs[5]; /* Beware of bit-sign propagation */
1227 } phy_magic[5] = { {
1228 { 0x0000, //w 4 15 12 0
1229 0x00a1, //w 3 15 0 00a1
1230 0x0008, //w 2 15 0 0008
1231 0x1020, //w 1 15 0 1020
1232 0x1000 } },{ //w 0 15 0 1000
1233 { 0x7000, //w 4 15 12 7
1234 0xff41, //w 3 15 0 ff41
1235 0xde60, //w 2 15 0 de60
1236 0x0140, //w 1 15 0 0140
1237 0x0077 } },{ //w 0 15 0 0077
1238 { 0xa000, //w 4 15 12 a
1239 0xdf01, //w 3 15 0 df01
1240 0xdf20, //w 2 15 0 df20
1241 0xff95, //w 1 15 0 ff95
1242 0xfa00 } },{ //w 0 15 0 fa00
1243 { 0xb000, //w 4 15 12 b
1244 0xff41, //w 3 15 0 ff41
1245 0xde20, //w 2 15 0 de20
1246 0x0140, //w 1 15 0 0140
1247 0x00bb } },{ //w 0 15 0 00bb
1248 { 0xf000, //w 4 15 12 f
1249 0xdf01, //w 3 15 0 df01
1250 0xdf20, //w 2 15 0 df20
1251 0xff95, //w 1 15 0 ff95
1252 0xbf00 } //w 0 15 0 bf00
1257 rtl8169_print_mac_version(tp);
1258 rtl8169_print_phy_version(tp);
1260 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1262 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1265 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1266 dprintk("Do final_reg2.cfg\n");
1270 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1271 mdio_write(ioaddr, 31, 0x0001);
1272 mdio_write(ioaddr, 9, 0x273a);
1273 mdio_write(ioaddr, 14, 0x7bfb);
1274 mdio_write(ioaddr, 27, 0x841e);
1276 mdio_write(ioaddr, 31, 0x0002);
1277 mdio_write(ioaddr, 1, 0x90d0);
1278 mdio_write(ioaddr, 31, 0x0000);
1282 /* phy config for RTL8169s mac_version C chip */
1283 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1284 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1285 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1286 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1288 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1291 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1292 mdio_write(ioaddr, pos, val);
1294 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1295 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1296 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1298 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1301 static void rtl8169_phy_timer(unsigned long __opaque)
1303 struct net_device *dev = (struct net_device *)__opaque;
1304 struct rtl8169_private *tp = netdev_priv(dev);
1305 struct timer_list *timer = &tp->timer;
1306 void __iomem *ioaddr = tp->mmio_addr;
1307 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1309 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1310 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1312 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1315 spin_lock_irq(&tp->lock);
1317 if (tp->phy_reset_pending(ioaddr)) {
1319 * A busy loop could burn quite a few cycles on nowadays CPU.
1320 * Let's delay the execution of the timer for a few ticks.
1326 if (tp->link_ok(ioaddr))
1329 if (netif_msg_link(tp))
1330 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1332 tp->phy_reset_enable(ioaddr);
1335 mod_timer(timer, jiffies + timeout);
1337 spin_unlock_irq(&tp->lock);
1340 static inline void rtl8169_delete_timer(struct net_device *dev)
1342 struct rtl8169_private *tp = netdev_priv(dev);
1343 struct timer_list *timer = &tp->timer;
1345 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1346 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1349 del_timer_sync(timer);
1352 static inline void rtl8169_request_timer(struct net_device *dev)
1354 struct rtl8169_private *tp = netdev_priv(dev);
1355 struct timer_list *timer = &tp->timer;
1357 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1358 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1363 timer->data = (unsigned long)(dev);
1364 timer->function = rtl8169_phy_timer;
1368 #ifdef CONFIG_NET_POLL_CONTROLLER
1370 * Polling 'interrupt' - used by things like netconsole to send skbs
1371 * without having to re-enable interrupts. It's not called while
1372 * the interrupt routine is executing.
1374 static void rtl8169_netpoll(struct net_device *dev)
1376 struct rtl8169_private *tp = netdev_priv(dev);
1377 struct pci_dev *pdev = tp->pci_dev;
1379 disable_irq(pdev->irq);
1380 rtl8169_interrupt(pdev->irq, dev, NULL);
1381 enable_irq(pdev->irq);
1385 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1386 void __iomem *ioaddr)
1389 pci_release_regions(pdev);
1390 pci_disable_device(pdev);
1394 static int __devinit
1395 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1396 void __iomem **ioaddr_out)
1398 void __iomem *ioaddr;
1399 struct net_device *dev;
1400 struct rtl8169_private *tp;
1401 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1403 assert(ioaddr_out != NULL);
1405 /* dev zeroed in alloc_etherdev */
1406 dev = alloc_etherdev(sizeof (*tp));
1408 if (netif_msg_drv(&debug))
1409 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1413 SET_MODULE_OWNER(dev);
1414 SET_NETDEV_DEV(dev, &pdev->dev);
1415 tp = netdev_priv(dev);
1416 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1418 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1419 rc = pci_enable_device(pdev);
1421 if (netif_msg_probe(tp)) {
1422 printk(KERN_ERR PFX "%s: enable failure\n",
1425 goto err_out_free_dev;
1428 rc = pci_set_mwi(pdev);
1430 goto err_out_disable;
1432 /* save power state before pci_enable_device overwrites it */
1433 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1437 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1438 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1440 if (netif_msg_probe(tp)) {
1442 "PowerManagement capability not found.\n");
1446 /* make sure PCI base addr 1 is MMIO */
1447 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1448 if (netif_msg_probe(tp)) {
1450 "region #1 not an MMIO resource, aborting\n");
1455 /* check for weird/broken PCI region reporting */
1456 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1457 if (netif_msg_probe(tp)) {
1459 "Invalid PCI region size(s), aborting\n");
1465 rc = pci_request_regions(pdev, MODULENAME);
1467 if (netif_msg_probe(tp)) {
1468 printk(KERN_ERR PFX "%s: could not request regions.\n",
1474 tp->cp_cmd = PCIMulRW | RxChkSum;
1476 if ((sizeof(dma_addr_t) > 4) &&
1477 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1478 tp->cp_cmd |= PCIDAC;
1479 dev->features |= NETIF_F_HIGHDMA;
1481 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1483 if (netif_msg_probe(tp)) {
1485 "DMA configuration failed.\n");
1487 goto err_out_free_res;
1491 pci_set_master(pdev);
1493 /* ioremap MMIO region */
1494 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1495 if (ioaddr == NULL) {
1496 if (netif_msg_probe(tp))
1497 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1499 goto err_out_free_res;
1502 /* Unneeded ? Don't mess with Mrs. Murphy. */
1503 rtl8169_irq_mask_and_ack(ioaddr);
1505 /* Soft reset the chip. */
1506 RTL_W8(ChipCmd, CmdReset);
1508 /* Check that the chip has finished the reset. */
1509 for (i = 1000; i > 0; i--) {
1510 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1515 /* Identify chip attached to board */
1516 rtl8169_get_mac_version(tp, ioaddr);
1517 rtl8169_get_phy_version(tp, ioaddr);
1519 rtl8169_print_mac_version(tp);
1520 rtl8169_print_phy_version(tp);
1522 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1523 if (tp->mac_version == rtl_chip_info[i].mac_version)
1527 /* Unknown chip: assume array element #0, original RTL-8169 */
1528 if (netif_msg_probe(tp)) {
1529 printk(KERN_DEBUG PFX "PCI device %s: "
1530 "unknown chip version, assuming %s\n",
1531 pci_name(pdev), rtl_chip_info[0].name);
1537 RTL_W8(Cfg9346, Cfg9346_Unlock);
1538 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1539 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1540 RTL_W8(Cfg9346, Cfg9346_Lock);
1542 *ioaddr_out = ioaddr;
1548 pci_release_regions(pdev);
1551 pci_clear_mwi(pdev);
1554 pci_disable_device(pdev);
1564 static int __devinit
1565 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1567 struct net_device *dev = NULL;
1568 struct rtl8169_private *tp;
1569 void __iomem *ioaddr = NULL;
1570 static int board_idx = -1;
1575 assert(pdev != NULL);
1576 assert(ent != NULL);
1580 if (netif_msg_drv(&debug)) {
1581 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1582 MODULENAME, RTL8169_VERSION);
1585 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1589 tp = netdev_priv(dev);
1590 assert(ioaddr != NULL);
1592 if (RTL_R8(PHYstatus) & TBI_Enable) {
1593 tp->set_speed = rtl8169_set_speed_tbi;
1594 tp->get_settings = rtl8169_gset_tbi;
1595 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1596 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1597 tp->link_ok = rtl8169_tbi_link_ok;
1599 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1601 tp->set_speed = rtl8169_set_speed_xmii;
1602 tp->get_settings = rtl8169_gset_xmii;
1603 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1604 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1605 tp->link_ok = rtl8169_xmii_link_ok;
1608 /* Get MAC address. FIXME: read EEPROM */
1609 for (i = 0; i < MAC_ADDR_LEN; i++)
1610 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1611 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1613 dev->open = rtl8169_open;
1614 dev->hard_start_xmit = rtl8169_start_xmit;
1615 dev->get_stats = rtl8169_get_stats;
1616 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1617 dev->stop = rtl8169_close;
1618 dev->tx_timeout = rtl8169_tx_timeout;
1619 dev->set_multicast_list = rtl8169_set_rx_mode;
1620 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1621 dev->irq = pdev->irq;
1622 dev->base_addr = (unsigned long) ioaddr;
1623 dev->change_mtu = rtl8169_change_mtu;
1625 #ifdef CONFIG_R8169_NAPI
1626 dev->poll = rtl8169_poll;
1627 dev->weight = R8169_NAPI_WEIGHT;
1630 #ifdef CONFIG_R8169_VLAN
1631 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1632 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1633 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1636 #ifdef CONFIG_NET_POLL_CONTROLLER
1637 dev->poll_controller = rtl8169_netpoll;
1640 tp->intr_mask = 0xffff;
1642 tp->mmio_addr = ioaddr;
1644 spin_lock_init(&tp->lock);
1646 rc = register_netdev(dev);
1648 rtl8169_release_board(pdev, dev, ioaddr);
1652 if (netif_msg_probe(tp)) {
1653 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1654 dev->name, rtl_chip_info[tp->chipset].name);
1657 pci_set_drvdata(pdev, dev);
1659 if (netif_msg_probe(tp)) {
1660 printk(KERN_INFO "%s: %s at 0x%lx, "
1661 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1664 rtl_chip_info[ent->driver_data].name,
1666 dev->dev_addr[0], dev->dev_addr[1],
1667 dev->dev_addr[2], dev->dev_addr[3],
1668 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1671 rtl8169_hw_phy_config(dev);
1673 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1676 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1677 dprintk("Set PCI Latency=0x40\n");
1678 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1681 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1682 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1684 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1685 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1688 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1690 rtl8169_set_speed(dev, autoneg, speed, duplex);
1692 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1693 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1698 static void __devexit
1699 rtl8169_remove_one(struct pci_dev *pdev)
1701 struct net_device *dev = pci_get_drvdata(pdev);
1702 struct rtl8169_private *tp = netdev_priv(dev);
1704 assert(dev != NULL);
1707 unregister_netdev(dev);
1708 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1709 pci_set_drvdata(pdev, NULL);
1712 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1713 struct net_device *dev)
1715 unsigned int mtu = dev->mtu;
1717 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1720 static int rtl8169_open(struct net_device *dev)
1722 struct rtl8169_private *tp = netdev_priv(dev);
1723 struct pci_dev *pdev = tp->pci_dev;
1726 rtl8169_set_rxbufsize(tp, dev);
1729 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1736 * Rx and Tx desscriptors needs 256 bytes alignment.
1737 * pci_alloc_consistent provides more.
1739 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1741 if (!tp->TxDescArray)
1744 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1746 if (!tp->RxDescArray)
1749 retval = rtl8169_init_ring(dev);
1753 INIT_WORK(&tp->task, NULL, dev);
1755 rtl8169_hw_start(dev);
1757 rtl8169_request_timer(dev);
1759 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1764 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1767 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1770 free_irq(dev->irq, dev);
1774 static void rtl8169_hw_reset(void __iomem *ioaddr)
1776 /* Disable interrupts */
1777 rtl8169_irq_mask_and_ack(ioaddr);
1779 /* Reset the chipset */
1780 RTL_W8(ChipCmd, CmdReset);
1787 rtl8169_hw_start(struct net_device *dev)
1789 struct rtl8169_private *tp = netdev_priv(dev);
1790 void __iomem *ioaddr = tp->mmio_addr;
1793 /* Soft reset the chip. */
1794 RTL_W8(ChipCmd, CmdReset);
1796 /* Check that the chip has finished the reset. */
1797 for (i = 1000; i > 0; i--) {
1798 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1803 RTL_W8(Cfg9346, Cfg9346_Unlock);
1804 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1805 RTL_W8(EarlyTxThres, EarlyTxThld);
1807 /* Low hurts. Let's disable the filtering. */
1808 RTL_W16(RxMaxSize, 16383);
1810 /* Set Rx Config register */
1811 i = rtl8169_rx_config |
1812 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1813 RTL_W32(RxConfig, i);
1815 /* Set DMA burst size and Interframe Gap Time */
1817 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1818 TxInterFrameGapShift));
1819 tp->cp_cmd |= RTL_R16(CPlusCmd);
1820 RTL_W16(CPlusCmd, tp->cp_cmd);
1822 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1823 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1824 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1825 "Bit-3 and bit-14 MUST be 1\n");
1826 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1827 RTL_W16(CPlusCmd, tp->cp_cmd);
1831 * Undocumented corner. Supposedly:
1832 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1834 RTL_W16(IntrMitigate, 0x0000);
1836 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1837 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1838 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1839 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1840 RTL_W8(Cfg9346, Cfg9346_Lock);
1843 RTL_W32(RxMissed, 0);
1845 rtl8169_set_rx_mode(dev);
1847 /* no early-rx interrupts */
1848 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1850 /* Enable all known interrupts by setting the interrupt mask. */
1851 RTL_W16(IntrMask, rtl8169_intr_mask);
1853 netif_start_queue(dev);
1856 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1858 struct rtl8169_private *tp = netdev_priv(dev);
1861 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1866 if (!netif_running(dev))
1871 rtl8169_set_rxbufsize(tp, dev);
1873 ret = rtl8169_init_ring(dev);
1877 netif_poll_enable(dev);
1879 rtl8169_hw_start(dev);
1881 rtl8169_request_timer(dev);
1887 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1889 desc->addr = 0x0badbadbadbadbadull;
1890 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1893 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1894 struct sk_buff **sk_buff, struct RxDesc *desc)
1896 struct pci_dev *pdev = tp->pci_dev;
1898 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1899 PCI_DMA_FROMDEVICE);
1900 dev_kfree_skb(*sk_buff);
1902 rtl8169_make_unusable_by_asic(desc);
1905 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1907 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1909 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1912 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1915 desc->addr = cpu_to_le64(mapping);
1917 rtl8169_mark_to_asic(desc, rx_buf_sz);
1920 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1921 struct RxDesc *desc, int rx_buf_sz)
1923 struct sk_buff *skb;
1927 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1931 skb_reserve(skb, NET_IP_ALIGN);
1934 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1935 PCI_DMA_FROMDEVICE);
1937 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1944 rtl8169_make_unusable_by_asic(desc);
1948 static void rtl8169_rx_clear(struct rtl8169_private *tp)
1952 for (i = 0; i < NUM_RX_DESC; i++) {
1953 if (tp->Rx_skbuff[i]) {
1954 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1955 tp->RxDescArray + i);
1960 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1965 for (cur = start; end - cur > 0; cur++) {
1966 int ret, i = cur % NUM_RX_DESC;
1968 if (tp->Rx_skbuff[i])
1971 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1972 tp->RxDescArray + i, tp->rx_buf_sz);
1979 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1981 desc->opts1 |= cpu_to_le32(RingEnd);
1984 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1986 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1989 static int rtl8169_init_ring(struct net_device *dev)
1991 struct rtl8169_private *tp = netdev_priv(dev);
1993 rtl8169_init_ring_indexes(tp);
1995 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1996 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1998 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2001 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2006 rtl8169_rx_clear(tp);
2010 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2011 struct TxDesc *desc)
2013 unsigned int len = tx_skb->len;
2015 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2022 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2026 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2027 unsigned int entry = i % NUM_TX_DESC;
2028 struct ring_info *tx_skb = tp->tx_skb + entry;
2029 unsigned int len = tx_skb->len;
2032 struct sk_buff *skb = tx_skb->skb;
2034 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2035 tp->TxDescArray + entry);
2040 tp->stats.tx_dropped++;
2043 tp->cur_tx = tp->dirty_tx = 0;
2046 static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2048 struct rtl8169_private *tp = netdev_priv(dev);
2050 PREPARE_WORK(&tp->task, task, dev);
2051 schedule_delayed_work(&tp->task, 4);
2054 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2056 struct rtl8169_private *tp = netdev_priv(dev);
2057 void __iomem *ioaddr = tp->mmio_addr;
2059 synchronize_irq(dev->irq);
2061 /* Wait for any pending NAPI task to complete */
2062 netif_poll_disable(dev);
2064 rtl8169_irq_mask_and_ack(ioaddr);
2066 netif_poll_enable(dev);
2069 static void rtl8169_reinit_task(void *_data)
2071 struct net_device *dev = _data;
2074 if (netif_running(dev)) {
2075 rtl8169_wait_for_quiescence(dev);
2079 ret = rtl8169_open(dev);
2080 if (unlikely(ret < 0)) {
2081 if (net_ratelimit()) {
2082 struct rtl8169_private *tp = netdev_priv(dev);
2084 if (netif_msg_drv(tp)) {
2086 "%s: reinit failure (status = %d)."
2087 " Rescheduling.\n", dev->name, ret);
2090 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2094 static void rtl8169_reset_task(void *_data)
2096 struct net_device *dev = _data;
2097 struct rtl8169_private *tp = netdev_priv(dev);
2099 if (!netif_running(dev))
2102 rtl8169_wait_for_quiescence(dev);
2104 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2105 rtl8169_tx_clear(tp);
2107 if (tp->dirty_rx == tp->cur_rx) {
2108 rtl8169_init_ring_indexes(tp);
2109 rtl8169_hw_start(dev);
2110 netif_wake_queue(dev);
2112 if (net_ratelimit()) {
2113 struct rtl8169_private *tp = netdev_priv(dev);
2115 if (netif_msg_intr(tp)) {
2116 printk(PFX KERN_EMERG
2117 "%s: Rx buffers shortage\n", dev->name);
2120 rtl8169_schedule_work(dev, rtl8169_reset_task);
2124 static void rtl8169_tx_timeout(struct net_device *dev)
2126 struct rtl8169_private *tp = netdev_priv(dev);
2128 rtl8169_hw_reset(tp->mmio_addr);
2130 /* Let's wait a bit while any (async) irq lands on */
2131 rtl8169_schedule_work(dev, rtl8169_reset_task);
2134 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2137 struct skb_shared_info *info = skb_shinfo(skb);
2138 unsigned int cur_frag, entry;
2142 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2143 skb_frag_t *frag = info->frags + cur_frag;
2148 entry = (entry + 1) % NUM_TX_DESC;
2150 txd = tp->TxDescArray + entry;
2152 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2153 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2155 /* anti gcc 2.95.3 bugware (sic) */
2156 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2158 txd->opts1 = cpu_to_le32(status);
2159 txd->addr = cpu_to_le64(mapping);
2161 tp->tx_skb[entry].len = len;
2165 tp->tx_skb[entry].skb = skb;
2166 txd->opts1 |= cpu_to_le32(LastFrag);
2172 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2174 if (dev->features & NETIF_F_TSO) {
2175 u32 mss = skb_shinfo(skb)->tso_size;
2178 return LargeSend | ((mss & MSSMask) << MSSShift);
2180 if (skb->ip_summed == CHECKSUM_HW) {
2181 const struct iphdr *ip = skb->nh.iph;
2183 if (ip->protocol == IPPROTO_TCP)
2184 return IPCS | TCPCS;
2185 else if (ip->protocol == IPPROTO_UDP)
2186 return IPCS | UDPCS;
2187 WARN_ON(1); /* we need a WARN() */
2192 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2194 struct rtl8169_private *tp = netdev_priv(dev);
2195 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2196 struct TxDesc *txd = tp->TxDescArray + entry;
2197 void __iomem *ioaddr = tp->mmio_addr;
2203 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2204 if (netif_msg_drv(tp)) {
2206 "%s: BUG! Tx Ring full when queue awake!\n",
2212 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2215 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2217 frags = rtl8169_xmit_frags(tp, skb, opts1);
2219 len = skb_headlen(skb);
2224 if (unlikely(len < ETH_ZLEN)) {
2225 skb = skb_padto(skb, ETH_ZLEN);
2227 goto err_update_stats;
2231 opts1 |= FirstFrag | LastFrag;
2232 tp->tx_skb[entry].skb = skb;
2235 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2237 tp->tx_skb[entry].len = len;
2238 txd->addr = cpu_to_le64(mapping);
2239 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2243 /* anti gcc 2.95.3 bugware (sic) */
2244 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2245 txd->opts1 = cpu_to_le32(status);
2247 dev->trans_start = jiffies;
2249 tp->cur_tx += frags + 1;
2253 RTL_W8(TxPoll, 0x40); /* set polling bit */
2255 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2256 netif_stop_queue(dev);
2258 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2259 netif_wake_queue(dev);
2266 netif_stop_queue(dev);
2269 tp->stats.tx_dropped++;
2273 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2275 struct rtl8169_private *tp = netdev_priv(dev);
2276 struct pci_dev *pdev = tp->pci_dev;
2277 void __iomem *ioaddr = tp->mmio_addr;
2278 u16 pci_status, pci_cmd;
2280 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2281 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2283 if (netif_msg_intr(tp)) {
2285 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2286 dev->name, pci_cmd, pci_status);
2290 * The recovery sequence below admits a very elaborated explanation:
2291 * - it seems to work;
2292 * - I did not see what else could be done.
2294 * Feel free to adjust to your needs.
2296 pci_write_config_word(pdev, PCI_COMMAND,
2297 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2299 pci_write_config_word(pdev, PCI_STATUS,
2300 pci_status & (PCI_STATUS_DETECTED_PARITY |
2301 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2302 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2304 /* The infamous DAC f*ckup only happens at boot time */
2305 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2306 if (netif_msg_intr(tp))
2307 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2308 tp->cp_cmd &= ~PCIDAC;
2309 RTL_W16(CPlusCmd, tp->cp_cmd);
2310 dev->features &= ~NETIF_F_HIGHDMA;
2311 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2314 rtl8169_hw_reset(ioaddr);
2318 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2319 void __iomem *ioaddr)
2321 unsigned int dirty_tx, tx_left;
2323 assert(dev != NULL);
2325 assert(ioaddr != NULL);
2327 dirty_tx = tp->dirty_tx;
2329 tx_left = tp->cur_tx - dirty_tx;
2331 while (tx_left > 0) {
2332 unsigned int entry = dirty_tx % NUM_TX_DESC;
2333 struct ring_info *tx_skb = tp->tx_skb + entry;
2334 u32 len = tx_skb->len;
2338 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2339 if (status & DescOwn)
2342 tp->stats.tx_bytes += len;
2343 tp->stats.tx_packets++;
2345 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2347 if (status & LastFrag) {
2348 dev_kfree_skb_irq(tx_skb->skb);
2355 if (tp->dirty_tx != dirty_tx) {
2356 tp->dirty_tx = dirty_tx;
2358 if (netif_queue_stopped(dev) &&
2359 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2360 netif_wake_queue(dev);
2365 static inline int rtl8169_fragmented_frame(u32 status)
2367 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2370 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2372 u32 opts1 = le32_to_cpu(desc->opts1);
2373 u32 status = opts1 & RxProtoMask;
2375 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2376 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2377 ((status == RxProtoIP) && !(opts1 & IPFail)))
2378 skb->ip_summed = CHECKSUM_UNNECESSARY;
2380 skb->ip_summed = CHECKSUM_NONE;
2383 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2384 struct RxDesc *desc, int rx_buf_sz)
2388 if (pkt_size < rx_copybreak) {
2389 struct sk_buff *skb;
2391 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2393 skb_reserve(skb, NET_IP_ALIGN);
2394 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
2396 rtl8169_mark_to_asic(desc, rx_buf_sz);
2404 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2405 void __iomem *ioaddr)
2407 unsigned int cur_rx, rx_left;
2408 unsigned int delta, count;
2410 assert(dev != NULL);
2412 assert(ioaddr != NULL);
2414 cur_rx = tp->cur_rx;
2415 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2416 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2418 for (; rx_left > 0; rx_left--, cur_rx++) {
2419 unsigned int entry = cur_rx % NUM_RX_DESC;
2420 struct RxDesc *desc = tp->RxDescArray + entry;
2424 status = le32_to_cpu(desc->opts1);
2426 if (status & DescOwn)
2428 if (unlikely(status & RxRES)) {
2429 if (netif_msg_rx_err(tp)) {
2431 "%s: Rx ERROR. status = %08x\n",
2434 tp->stats.rx_errors++;
2435 if (status & (RxRWT | RxRUNT))
2436 tp->stats.rx_length_errors++;
2438 tp->stats.rx_crc_errors++;
2439 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2441 struct sk_buff *skb = tp->Rx_skbuff[entry];
2442 int pkt_size = (status & 0x00001FFF) - 4;
2443 void (*pci_action)(struct pci_dev *, dma_addr_t,
2444 size_t, int) = pci_dma_sync_single_for_device;
2447 * The driver does not support incoming fragmented
2448 * frames. They are seen as a symptom of over-mtu
2451 if (unlikely(rtl8169_fragmented_frame(status))) {
2452 tp->stats.rx_dropped++;
2453 tp->stats.rx_length_errors++;
2454 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2458 rtl8169_rx_csum(skb, desc);
2460 pci_dma_sync_single_for_cpu(tp->pci_dev,
2461 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2462 PCI_DMA_FROMDEVICE);
2464 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2466 pci_action = pci_unmap_single;
2467 tp->Rx_skbuff[entry] = NULL;
2470 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2471 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2474 skb_put(skb, pkt_size);
2475 skb->protocol = eth_type_trans(skb, dev);
2477 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2478 rtl8169_rx_skb(skb);
2480 dev->last_rx = jiffies;
2481 tp->stats.rx_bytes += pkt_size;
2482 tp->stats.rx_packets++;
2486 count = cur_rx - tp->cur_rx;
2487 tp->cur_rx = cur_rx;
2489 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2490 if (!delta && count && netif_msg_intr(tp))
2491 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2492 tp->dirty_rx += delta;
2495 * FIXME: until there is periodic timer to try and refill the ring,
2496 * a temporary shortage may definitely kill the Rx process.
2497 * - disable the asic to try and avoid an overflow and kick it again
2499 * - how do others driver handle this condition (Uh oh...).
2501 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2502 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2507 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2509 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2511 struct net_device *dev = (struct net_device *) dev_instance;
2512 struct rtl8169_private *tp = netdev_priv(dev);
2513 int boguscnt = max_interrupt_work;
2514 void __iomem *ioaddr = tp->mmio_addr;
2519 status = RTL_R16(IntrStatus);
2521 /* hotplug/major error/no more work/shared irq */
2522 if ((status == 0xFFFF) || !status)
2527 if (unlikely(!netif_running(dev))) {
2528 rtl8169_asic_down(ioaddr);
2532 status &= tp->intr_mask;
2534 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2536 if (!(status & rtl8169_intr_mask))
2539 if (unlikely(status & SYSErr)) {
2540 rtl8169_pcierr_interrupt(dev);
2544 if (status & LinkChg)
2545 rtl8169_check_link_status(dev, tp, ioaddr);
2547 #ifdef CONFIG_R8169_NAPI
2548 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2549 tp->intr_mask = ~rtl8169_napi_event;
2551 if (likely(netif_rx_schedule_prep(dev)))
2552 __netif_rx_schedule(dev);
2553 else if (netif_msg_intr(tp)) {
2554 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2560 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2561 rtl8169_rx_interrupt(dev, tp, ioaddr);
2564 if (status & (TxOK | TxErr))
2565 rtl8169_tx_interrupt(dev, tp, ioaddr);
2569 } while (boguscnt > 0);
2571 if (boguscnt <= 0) {
2572 if (netif_msg_intr(tp) && net_ratelimit() ) {
2574 "%s: Too much work at interrupt!\n", dev->name);
2576 /* Clear all interrupt sources. */
2577 RTL_W16(IntrStatus, 0xffff);
2580 return IRQ_RETVAL(handled);
2583 #ifdef CONFIG_R8169_NAPI
2584 static int rtl8169_poll(struct net_device *dev, int *budget)
2586 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2587 struct rtl8169_private *tp = netdev_priv(dev);
2588 void __iomem *ioaddr = tp->mmio_addr;
2590 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2591 rtl8169_tx_interrupt(dev, tp, ioaddr);
2593 *budget -= work_done;
2594 dev->quota -= work_done;
2596 if (work_done < work_to_do) {
2597 netif_rx_complete(dev);
2598 tp->intr_mask = 0xffff;
2600 * 20040426: the barrier is not strictly required but the
2601 * behavior of the irq handler could be less predictable
2602 * without it. Btw, the lack of flush for the posted pci
2603 * write is safe - FR
2606 RTL_W16(IntrMask, rtl8169_intr_mask);
2609 return (work_done >= work_to_do);
2613 static void rtl8169_down(struct net_device *dev)
2615 struct rtl8169_private *tp = netdev_priv(dev);
2616 void __iomem *ioaddr = tp->mmio_addr;
2617 unsigned int poll_locked = 0;
2619 rtl8169_delete_timer(dev);
2621 netif_stop_queue(dev);
2623 flush_scheduled_work();
2626 spin_lock_irq(&tp->lock);
2628 rtl8169_asic_down(ioaddr);
2630 /* Update the error counts. */
2631 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2632 RTL_W32(RxMissed, 0);
2634 spin_unlock_irq(&tp->lock);
2636 synchronize_irq(dev->irq);
2639 netif_poll_disable(dev);
2643 /* Give a racing hard_start_xmit a few cycles to complete. */
2644 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2647 * And now for the 50k$ question: are IRQ disabled or not ?
2649 * Two paths lead here:
2651 * -> netif_running() is available to sync the current code and the
2652 * IRQ handler. See rtl8169_interrupt for details.
2653 * 2) dev->change_mtu
2654 * -> rtl8169_poll can not be issued again and re-enable the
2655 * interruptions. Let's simply issue the IRQ down sequence again.
2657 if (RTL_R16(IntrMask))
2660 rtl8169_tx_clear(tp);
2662 rtl8169_rx_clear(tp);
2665 static int rtl8169_close(struct net_device *dev)
2667 struct rtl8169_private *tp = netdev_priv(dev);
2668 struct pci_dev *pdev = tp->pci_dev;
2672 free_irq(dev->irq, dev);
2674 netif_poll_enable(dev);
2676 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2678 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2680 tp->TxDescArray = NULL;
2681 tp->RxDescArray = NULL;
2687 rtl8169_set_rx_mode(struct net_device *dev)
2689 struct rtl8169_private *tp = netdev_priv(dev);
2690 void __iomem *ioaddr = tp->mmio_addr;
2691 unsigned long flags;
2692 u32 mc_filter[2]; /* Multicast hash filter */
2696 if (dev->flags & IFF_PROMISC) {
2697 /* Unconditionally log net taps. */
2698 if (netif_msg_link(tp)) {
2699 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2703 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2705 mc_filter[1] = mc_filter[0] = 0xffffffff;
2706 } else if ((dev->mc_count > multicast_filter_limit)
2707 || (dev->flags & IFF_ALLMULTI)) {
2708 /* Too many to filter perfectly -- accept all multicasts. */
2709 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2710 mc_filter[1] = mc_filter[0] = 0xffffffff;
2712 struct dev_mc_list *mclist;
2713 rx_mode = AcceptBroadcast | AcceptMyPhys;
2714 mc_filter[1] = mc_filter[0] = 0;
2715 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2716 i++, mclist = mclist->next) {
2717 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2718 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2719 rx_mode |= AcceptMulticast;
2723 spin_lock_irqsave(&tp->lock, flags);
2725 tmp = rtl8169_rx_config | rx_mode |
2726 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2728 RTL_W32(RxConfig, tmp);
2729 RTL_W32(MAR0 + 0, mc_filter[0]);
2730 RTL_W32(MAR0 + 4, mc_filter[1]);
2732 spin_unlock_irqrestore(&tp->lock, flags);
2736 * rtl8169_get_stats - Get rtl8169 read/write statistics
2737 * @dev: The Ethernet Device to get statistics for
2739 * Get TX/RX statistics for rtl8169
2741 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2743 struct rtl8169_private *tp = netdev_priv(dev);
2744 void __iomem *ioaddr = tp->mmio_addr;
2745 unsigned long flags;
2747 if (netif_running(dev)) {
2748 spin_lock_irqsave(&tp->lock, flags);
2749 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2750 RTL_W32(RxMissed, 0);
2751 spin_unlock_irqrestore(&tp->lock, flags);
2759 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2761 struct net_device *dev = pci_get_drvdata(pdev);
2762 struct rtl8169_private *tp = netdev_priv(dev);
2763 void __iomem *ioaddr = tp->mmio_addr;
2765 if (!netif_running(dev))
2768 netif_device_detach(dev);
2769 netif_stop_queue(dev);
2771 spin_lock_irq(&tp->lock);
2773 rtl8169_asic_down(ioaddr);
2775 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2776 RTL_W32(RxMissed, 0);
2778 spin_unlock_irq(&tp->lock);
2780 pci_save_state(pdev);
2781 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2782 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2787 static int rtl8169_resume(struct pci_dev *pdev)
2789 struct net_device *dev = pci_get_drvdata(pdev);
2791 if (!netif_running(dev))
2794 netif_device_attach(dev);
2796 pci_set_power_state(pdev, PCI_D0);
2797 pci_restore_state(pdev);
2798 pci_enable_wake(pdev, PCI_D0, 0);
2800 rtl8169_schedule_work(dev, rtl8169_reset_task);
2805 #endif /* CONFIG_PM */
2807 static struct pci_driver rtl8169_pci_driver = {
2809 .id_table = rtl8169_pci_tbl,
2810 .probe = rtl8169_init_one,
2811 .remove = __devexit_p(rtl8169_remove_one),
2813 .suspend = rtl8169_suspend,
2814 .resume = rtl8169_resume,
2819 rtl8169_init_module(void)
2821 return pci_module_init(&rtl8169_pci_driver);
2825 rtl8169_cleanup_module(void)
2827 pci_unregister_driver(&rtl8169_pci_driver);
2830 module_init(rtl8169_init_module);
2831 module_exit(rtl8169_cleanup_module);