git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  *
  33  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
  34  */
  35
  36 #include <linux/init.h>
  37 #include <linux/hardirq.h>
  38
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_cmd.h"
  43 #include "mthca_memfree.h"
  44
  45 enum {
  46         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  47 };
  48
  49 enum {
  50         MTHCA_CQ_ENTRY_SIZE = 0x20
  51 };
  52
  53 /*
  54  * Must be packed because start is 64 bits but only aligned to 32 bits.
  55  */
  56 struct mthca_cq_context {
  57         u32 flags;
  58         u64 start;
  59         u32 logsize_usrpage;
  60         u32 error_eqn;          /* Tavor only */
  61         u32 comp_eqn;
  62         u32 pd;
  63         u32 lkey;
  64         u32 last_notified_index;
  65         u32 solicit_producer_index;
  66         u32 consumer_index;
  67         u32 producer_index;
  68         u32 cqn;
  69         u32 ci_db;              /* Arbel only */
  70         u32 state_db;           /* Arbel only */
  71         u32 reserved;
  72 } __attribute__((packed));
  73
  74 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  75 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  76 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  77 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  78 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  79 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  80 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  81 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  82 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  83
  84 enum {
  85         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  86 };
  87
  88 enum {
  89         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
  90         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
  91         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
  92         SYNDROME_LOCAL_PROT_ERR          = 0x04,
  93         SYNDROME_WR_FLUSH_ERR            = 0x05,
  94         SYNDROME_MW_BIND_ERR             = 0x06,
  95         SYNDROME_BAD_RESP_ERR            = 0x10,
  96         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
  97         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
  98         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
  99         SYNDROME_REMOTE_OP_ERR           = 0x14,
 100         SYNDROME_RETRY_EXC_ERR           = 0x15,
 101         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 102         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 103         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 104         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 105         SYNDROME_INVAL_EECN_ERR          = 0x23,
 106         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 107 };
 108
 109 struct mthca_cqe {
 110         u32 my_qpn;
 111         u32 my_ee;
 112         u32 rqpn;
 113         u16 sl_g_mlpath;
 114         u16 rlid;
 115         u32 imm_etype_pkey_eec;
 116         u32 byte_cnt;
 117         u32 wqe;
 118         u8  opcode;
 119         u8  is_send;
 120         u8  reserved;
 121         u8  owner;
 122 };
 123
 124 struct mthca_err_cqe {
 125         u32 my_qpn;
 126         u32 reserved1[3];
 127         u8  syndrome;
 128         u8  reserved2;
 129         u16 db_cnt;
 130         u32 reserved3;
 131         u32 wqe;
 132         u8  opcode;
 133         u8  reserved4[2];
 134         u8  owner;
 135 };
 136
 137 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 138 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 139
 140 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 141 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 142 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 143 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 145
 146 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 147 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 148 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 149
 150 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 151 {
 152         if (cq->is_direct)
 153                 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
 154         else
 155                 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
 156                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
 157 }
 158
 159 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
 160 {
 161         struct mthca_cqe *cqe = get_cqe(cq, i);
 162         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 163 }
 164
 165 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 166 {
 167         return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
 168 }
 169
 170 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 171 {
 172         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 173 }
 174
 175 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
 176 {
 177         __be32 *cqe = cqe_ptr;
 178
 179         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 180         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 181                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
 182                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
 183                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
 184 }
 185
 186 /*
 187  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 188  * should be correct before calling update_cons_index().
 189  */
 190 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 191                                      int incr)
 192 {
 193         u32 doorbell[2];
 194
 195         if (mthca_is_memfree(dev)) {
 196                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
 197                 wmb();
 198         } else {
 199                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 200                 doorbell[1] = cpu_to_be32(incr - 1);
 201
 202                 mthca_write64(doorbell,
 203                               dev->kar + MTHCA_CQ_DOORBELL,
 204                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 205         }
 206 }
 207
 208 void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
 209 {
 210         struct mthca_cq *cq;
 211
 212         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 213
 214         if (!cq) {
 215                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
 216                 return;
 217         }
 218
 219         ++cq->arm_sn;
 220
 221         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 222 }
 223
 224 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn)
 225 {
 226         struct mthca_cq *cq;
 227         struct mthca_cqe *cqe;
 228         int prod_index;
 229         int nfreed = 0;
 230
 231         spin_lock_irq(&dev->cq_table.lock);
 232         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 233         if (cq)
 234                 atomic_inc(&cq->refcount);
 235         spin_unlock_irq(&dev->cq_table.lock);
 236
 237         if (!cq)
 238                 return;
 239
 240         spin_lock_irq(&cq->lock);
 241
 242         /*
 243          * First we need to find the current producer index, so we
 244          * know where to start cleaning from.  It doesn't matter if HW
 245          * adds new entries after this loop -- the QP we're worried
 246          * about is already in RESET, so the new entries won't come
 247          * from our QP and therefore don't need to be checked.
 248          */
 249         for (prod_index = cq->cons_index;
 250              cqe_sw(cq, prod_index & cq->ibcq.cqe);
 251              ++prod_index)
 252                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 253                         break;
 254
 255         if (0)
 256                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 257                           qpn, cqn, cq->cons_index, prod_index);
 258
 259         /*
 260          * Now sweep backwards through the CQ, removing CQ entries
 261          * that match our QP by copying older entries on top of them.
 262          */
 263         while (prod_index > cq->cons_index) {
 264                 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
 265                 if (cqe->my_qpn == cpu_to_be32(qpn))
 266                         ++nfreed;
 267                 else if (nfreed)
 268                         memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
 269                                        cq->ibcq.cqe),
 270                                cqe,
 271                                MTHCA_CQ_ENTRY_SIZE);
 272                 --prod_index;
 273         }
 274
 275         if (nfreed) {
 276                 wmb();
 277                 cq->cons_index += nfreed;
 278                 update_cons_index(dev, cq, nfreed);
 279         }
 280
 281         spin_unlock_irq(&cq->lock);
 282         if (atomic_dec_and_test(&cq->refcount))
 283                 wake_up(&cq->wait);
 284 }
 285
 286 static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 287                             struct mthca_qp *qp, int wqe_index, int is_send,
 288                             struct mthca_err_cqe *cqe,
 289                             struct ib_wc *entry, int *free_cqe)
 290 {
 291         int err;
 292         int dbd;
 293         u32 new_wqe;
 294
 295         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
 296                 mthca_dbg(dev, "local QP operation err "
 297                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 298                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
 299                           cq->cqn, cq->cons_index);
 300                 dump_cqe(dev, cqe);
 301         }
 302
 303         /*
 304          * For completions in error, only work request ID, status (and
 305          * freed resource count for RD) have to be set.
 306          */
 307         switch (cqe->syndrome) {
 308         case SYNDROME_LOCAL_LENGTH_ERR:
 309                 entry->status = IB_WC_LOC_LEN_ERR;
 310                 break;
 311         case SYNDROME_LOCAL_QP_OP_ERR:
 312                 entry->status = IB_WC_LOC_QP_OP_ERR;
 313                 break;
 314         case SYNDROME_LOCAL_EEC_OP_ERR:
 315                 entry->status = IB_WC_LOC_EEC_OP_ERR;
 316                 break;
 317         case SYNDROME_LOCAL_PROT_ERR:
 318                 entry->status = IB_WC_LOC_PROT_ERR;
 319                 break;
 320         case SYNDROME_WR_FLUSH_ERR:
 321                 entry->status = IB_WC_WR_FLUSH_ERR;
 322                 break;
 323         case SYNDROME_MW_BIND_ERR:
 324                 entry->status = IB_WC_MW_BIND_ERR;
 325                 break;
 326         case SYNDROME_BAD_RESP_ERR:
 327                 entry->status = IB_WC_BAD_RESP_ERR;
 328                 break;
 329         case SYNDROME_LOCAL_ACCESS_ERR:
 330                 entry->status = IB_WC_LOC_ACCESS_ERR;
 331                 break;
 332         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 333                 entry->status = IB_WC_REM_INV_REQ_ERR;
 334                 break;
 335         case SYNDROME_REMOTE_ACCESS_ERR:
 336                 entry->status = IB_WC_REM_ACCESS_ERR;
 337                 break;
 338         case SYNDROME_REMOTE_OP_ERR:
 339                 entry->status = IB_WC_REM_OP_ERR;
 340                 break;
 341         case SYNDROME_RETRY_EXC_ERR:
 342                 entry->status = IB_WC_RETRY_EXC_ERR;
 343                 break;
 344         case SYNDROME_RNR_RETRY_EXC_ERR:
 345                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
 346                 break;
 347         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 348                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
 349                 break;
 350         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 351                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
 352                 break;
 353         case SYNDROME_REMOTE_ABORTED_ERR:
 354                 entry->status = IB_WC_REM_ABORT_ERR;
 355                 break;
 356         case SYNDROME_INVAL_EECN_ERR:
 357                 entry->status = IB_WC_INV_EECN_ERR;
 358                 break;
 359         case SYNDROME_INVAL_EEC_STATE_ERR:
 360                 entry->status = IB_WC_INV_EEC_STATE_ERR;
 361                 break;
 362         default:
 363                 entry->status = IB_WC_GENERAL_ERR;
 364                 break;
 365         }
 366
 367         err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 368         if (err)
 369                 return err;
 370
 371         /*
 372          * If we're at the end of the WQE chain, or we've used up our
 373          * doorbell count, free the CQE.  Otherwise just update it for
 374          * the next poll operation.
 375          */
 376         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 377                 return 0;
 378
 379         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
 380         cqe->wqe      = new_wqe;
 381         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 382
 383         *free_cqe = 0;
 384
 385         return 0;
 386 }
 387
 388 static inline int mthca_poll_one(struct mthca_dev *dev,
 389                                  struct mthca_cq *cq,
 390                                  struct mthca_qp **cur_qp,
 391                                  int *freed,
 392                                  struct ib_wc *entry)
 393 {
 394         struct mthca_wq *wq;
 395         struct mthca_cqe *cqe;
 396         int wqe_index;
 397         int is_error;
 398         int is_send;
 399         int free_cqe = 1;
 400         int err = 0;
 401
 402         cqe = next_cqe_sw(cq);
 403         if (!cqe)
 404                 return -EAGAIN;
 405
 406         /*
 407          * Make sure we read CQ entry contents after we've checked the
 408          * ownership bit.
 409          */
 410         rmb();
 411
 412         if (0) {
 413                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
 414                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
 415                           be32_to_cpu(cqe->wqe));
 416                 dump_cqe(dev, cqe);
 417         }
 418
 419         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 420                 MTHCA_ERROR_CQE_OPCODE_MASK;
 421         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 422
 423         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
 424                 /*
 425                  * We do not have to take the QP table lock here,
 426                  * because CQs will be locked while QPs are removed
 427                  * from the table.
 428                  */
 429                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 430                                           be32_to_cpu(cqe->my_qpn) &
 431                                           (dev->limits.num_qps - 1));
 432                 if (!*cur_qp) {
 433                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
 434                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
 435                         err = -EINVAL;
 436                         goto out;
 437                 }
 438         }
 439
 440         entry->qp_num = (*cur_qp)->qpn;
 441
 442         if (is_send) {
 443                 wq = &(*cur_qp)->sq;
 444                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 445                              >> wq->wqe_shift);
 446                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 447                                                (*cur_qp)->rq.max];
 448         } else {
 449                 wq = &(*cur_qp)->rq;
 450                 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
 451                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 452         }
 453
 454         if (wq->last_comp < wqe_index)
 455                 wq->tail += wqe_index - wq->last_comp;
 456         else
 457                 wq->tail += wqe_index + wq->max - wq->last_comp;
 458
 459         wq->last_comp = wqe_index;
 460
 461         if (0)
 462                 mthca_dbg(dev, "%s completion for QP %06x, index %d (nr %d)\n",
 463                           is_send ? "Send" : "Receive",
 464                           (*cur_qp)->qpn, wqe_index, wq->max);
 465
 466         if (is_error) {
 467                 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 468                                        (struct mthca_err_cqe *) cqe,
 469                                        entry, &free_cqe);
 470                 goto out;
 471         }
 472
 473         if (is_send) {
 474                 entry->wc_flags = 0;
 475                 switch (cqe->opcode) {
 476                 case MTHCA_OPCODE_RDMA_WRITE:
 477                         entry->opcode    = IB_WC_RDMA_WRITE;
 478                         break;
 479                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 480                         entry->opcode    = IB_WC_RDMA_WRITE;
 481                         entry->wc_flags |= IB_WC_WITH_IMM;
 482                         break;
 483                 case MTHCA_OPCODE_SEND:
 484                         entry->opcode    = IB_WC_SEND;
 485                         break;
 486                 case MTHCA_OPCODE_SEND_IMM:
 487                         entry->opcode    = IB_WC_SEND;
 488                         entry->wc_flags |= IB_WC_WITH_IMM;
 489                         break;
 490                 case MTHCA_OPCODE_RDMA_READ:
 491                         entry->opcode    = IB_WC_RDMA_READ;
 492                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 493                         break;
 494                 case MTHCA_OPCODE_ATOMIC_CS:
 495                         entry->opcode    = IB_WC_COMP_SWAP;
 496                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 497                         break;
 498                 case MTHCA_OPCODE_ATOMIC_FA:
 499                         entry->opcode    = IB_WC_FETCH_ADD;
 500                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 501                         break;
 502                 case MTHCA_OPCODE_BIND_MW:
 503                         entry->opcode    = IB_WC_BIND_MW;
 504                         break;
 505                 default:
 506                         entry->opcode    = MTHCA_OPCODE_INVALID;
 507                         break;
 508                 }
 509         } else {
 510                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
 511                 switch (cqe->opcode & 0x1f) {
 512                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 513                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 514                         entry->wc_flags = IB_WC_WITH_IMM;
 515                         entry->imm_data = cqe->imm_etype_pkey_eec;
 516                         entry->opcode = IB_WC_RECV;
 517                         break;
 518                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 519                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 520                         entry->wc_flags = IB_WC_WITH_IMM;
 521                         entry->imm_data = cqe->imm_etype_pkey_eec;
 522                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
 523                         break;
 524                 default:
 525                         entry->wc_flags = 0;
 526                         entry->opcode = IB_WC_RECV;
 527                         break;
 528                 }
 529                 entry->slid        = be16_to_cpu(cqe->rlid);
 530                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
 531                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
 532                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
 533                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
 534                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
 535                                         IB_WC_GRH : 0;
 536         }
 537
 538         entry->status = IB_WC_SUCCESS;
 539
 540  out:
 541         if (likely(free_cqe)) {
 542                 set_cqe_hw(cqe);
 543                 ++(*freed);
 544                 ++cq->cons_index;
 545         }
 546
 547         return err;
 548 }
 549
 550 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 551                   struct ib_wc *entry)
 552 {
 553         struct mthca_dev *dev = to_mdev(ibcq->device);
 554         struct mthca_cq *cq = to_mcq(ibcq);
 555         struct mthca_qp *qp = NULL;
 556         unsigned long flags;
 557         int err = 0;
 558         int freed = 0;
 559         int npolled;
 560
 561         spin_lock_irqsave(&cq->lock, flags);
 562
 563         for (npolled = 0; npolled < num_entries; ++npolled) {
 564                 err = mthca_poll_one(dev, cq, &qp,
 565                                      &freed, entry + npolled);
 566                 if (err)
 567                         break;
 568         }
 569
 570         if (freed) {
 571                 wmb();
 572                 update_cons_index(dev, cq, freed);
 573         }
 574
 575         spin_unlock_irqrestore(&cq->lock, flags);
 576
 577         return err == 0 || err == -EAGAIN ? npolled : err;
 578 }
 579
 580 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
 581 {
 582         u32 doorbell[2];
 583
 584         doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
 585                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 586                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 587                                   to_mcq(cq)->cqn);
 588         doorbell[1] = 0xffffffff;
 589
 590         mthca_write64(doorbell,
 591                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 592                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 593
 594         return 0;
 595 }
 596
 597 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
 598 {
 599         struct mthca_cq *cq = to_mcq(ibcq);
 600         u32 doorbell[2];
 601         u32 sn;
 602         u32 ci;
 603
 604         sn = cq->arm_sn & 3;
 605         ci = cpu_to_be32(cq->cons_index);
 606
 607         doorbell[0] = ci;
 608         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 609                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
 610
 611         mthca_write_db_rec(doorbell, cq->arm_db);
 612
 613         /*
 614          * Make sure that the doorbell record in host memory is
 615          * written before ringing the doorbell via PCI MMIO.
 616          */
 617         wmb();
 618
 619         doorbell[0] = cpu_to_be32((sn << 28)                       |
 620                                   (notify == IB_CQ_SOLICITED ?
 621                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 622                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 623                                   cq->cqn);
 624         doorbell[1] = ci;
 625
 626         mthca_write64(doorbell,
 627                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 628                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 629
 630         return 0;
 631 }
 632
 633 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
 634 {
 635         int i;
 636         int size;
 637
 638         if (cq->is_direct)
 639                 dma_free_coherent(&dev->pdev->dev,
 640                                   (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
 641                                   cq->queue.direct.buf,
 642                                   pci_unmap_addr(&cq->queue.direct,
 643                                                  mapping));
 644         else {
 645                 size = (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE;
 646                 for (i = 0; i < (size + PAGE_SIZE - 1) / PAGE_SIZE; ++i)
 647                         if (cq->queue.page_list[i].buf)
 648                                 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
 649                                                   cq->queue.page_list[i].buf,
 650                                                   pci_unmap_addr(&cq->queue.page_list[i],
 651                                                                  mapping));
 652
 653                 kfree(cq->queue.page_list);
 654         }
 655 }
 656
 657 static int mthca_alloc_cq_buf(struct mthca_dev *dev, int size,
 658                               struct mthca_cq *cq)
 659 {
 660         int err = -ENOMEM;
 661         int npages, shift;
 662         u64 *dma_list = NULL;
 663         dma_addr_t t;
 664         int i;
 665
 666         if (size <= MTHCA_MAX_DIRECT_CQ_SIZE) {
 667                 cq->is_direct = 1;
 668                 npages        = 1;
 669                 shift         = get_order(size) + PAGE_SHIFT;
 670
 671                 cq->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev,
 672                                                           size, &t, GFP_KERNEL);
 673                 if (!cq->queue.direct.buf)
 674                         return -ENOMEM;
 675
 676                 pci_unmap_addr_set(&cq->queue.direct, mapping, t);
 677
 678                 memset(cq->queue.direct.buf, 0, size);
 679
 680                 while (t & ((1 << shift) - 1)) {
 681                         --shift;
 682                         npages *= 2;
 683                 }
 684
 685                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 686                 if (!dma_list)
 687                         goto err_free;
 688
 689                 for (i = 0; i < npages; ++i)
 690                         dma_list[i] = t + i * (1 << shift);
 691         } else {
 692                 cq->is_direct = 0;
 693                 npages        = (size + PAGE_SIZE - 1) / PAGE_SIZE;
 694                 shift         = PAGE_SHIFT;
 695
 696                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 697                 if (!dma_list)
 698                         return -ENOMEM;
 699
 700                 cq->queue.page_list = kmalloc(npages * sizeof *cq->queue.page_list,
 701                                               GFP_KERNEL);
 702                 if (!cq->queue.page_list)
 703                         goto err_out;
 704
 705                 for (i = 0; i < npages; ++i)
 706                         cq->queue.page_list[i].buf = NULL;
 707
 708                 for (i = 0; i < npages; ++i) {
 709                         cq->queue.page_list[i].buf =
 710                                 dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
 711                                                    &t, GFP_KERNEL);
 712                         if (!cq->queue.page_list[i].buf)
 713                                 goto err_free;
 714
 715                         dma_list[i] = t;
 716                         pci_unmap_addr_set(&cq->queue.page_list[i], mapping, t);
 717
 718                         memset(cq->queue.page_list[i].buf, 0, PAGE_SIZE);
 719                 }
 720         }
 721
 722         err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
 723                                   dma_list, shift, npages,
 724                                   0, size,
 725                                   MTHCA_MPT_FLAG_LOCAL_WRITE |
 726                                   MTHCA_MPT_FLAG_LOCAL_READ,
 727                                   &cq->mr);
 728         if (err)
 729                 goto err_free;
 730
 731         kfree(dma_list);
 732
 733         return 0;
 734
 735 err_free:
 736         mthca_free_cq_buf(dev, cq);
 737
 738 err_out:
 739         kfree(dma_list);
 740
 741         return err;
 742 }
 743
 744 int mthca_init_cq(struct mthca_dev *dev, int nent,
 745                   struct mthca_cq *cq)
 746 {
 747         int size = nent * MTHCA_CQ_ENTRY_SIZE;
 748         struct mthca_mailbox *mailbox;
 749         struct mthca_cq_context *cq_context;
 750         int err = -ENOMEM;
 751         u8 status;
 752         int i;
 753
 754         might_sleep();
 755
 756         cq->ibcq.cqe = nent - 1;
 757
 758         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 759         if (cq->cqn == -1)
 760                 return -ENOMEM;
 761
 762         if (mthca_is_memfree(dev)) {
 763                 cq->arm_sn = 1;
 764
 765                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 766                 if (err)
 767                         goto err_out;
 768
 769                 err = -ENOMEM;
 770
 771                 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 772                                                      cq->cqn, &cq->set_ci_db);
 773                 if (cq->set_ci_db_index < 0)
 774                         goto err_out_icm;
 775
 776                 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 777                                                   cq->cqn, &cq->arm_db);
 778                 if (cq->arm_db_index < 0)
 779                         goto err_out_ci;
 780         }
 781
 782         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 783         if (IS_ERR(mailbox))
 784                 goto err_out_arm;
 785
 786         cq_context = mailbox->buf;
 787
 788         err = mthca_alloc_cq_buf(dev, size, cq);
 789         if (err)
 790                 goto err_out_mailbox;
 791
 792         for (i = 0; i < nent; ++i)
 793                 set_cqe_hw(get_cqe(cq, i));
 794
 795         spin_lock_init(&cq->lock);
 796         atomic_set(&cq->refcount, 1);
 797         init_waitqueue_head(&cq->wait);
 798
 799         memset(cq_context, 0, sizeof *cq_context);
 800         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
 801                                                   MTHCA_CQ_STATE_DISARMED |
 802                                                   MTHCA_CQ_FLAG_TR);
 803         cq_context->start           = cpu_to_be64(0);
 804         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24 |
 805                                                   dev->driver_uar.index);
 806         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 807         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 808         cq_context->pd              = cpu_to_be32(dev->driver_pd.pd_num);
 809         cq_context->lkey            = cpu_to_be32(cq->mr.ibmr.lkey);
 810         cq_context->cqn             = cpu_to_be32(cq->cqn);
 811
 812         if (mthca_is_memfree(dev)) {
 813                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
 814                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
 815         }
 816
 817         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 818         if (err) {
 819                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
 820                 goto err_out_free_mr;
 821         }
 822
 823         if (status) {
 824                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
 825                            status);
 826                 err = -EINVAL;
 827                 goto err_out_free_mr;
 828         }
 829
 830         spin_lock_irq(&dev->cq_table.lock);
 831         if (mthca_array_set(&dev->cq_table.cq,
 832                             cq->cqn & (dev->limits.num_cqs - 1),
 833                             cq)) {
 834                 spin_unlock_irq(&dev->cq_table.lock);
 835                 goto err_out_free_mr;
 836         }
 837         spin_unlock_irq(&dev->cq_table.lock);
 838
 839         cq->cons_index = 0;
 840
 841         mthca_free_mailbox(dev, mailbox);
 842
 843         return 0;
 844
 845 err_out_free_mr:
 846         mthca_free_mr(dev, &cq->mr);
 847         mthca_free_cq_buf(dev, cq);
 848
 849 err_out_mailbox:
 850         mthca_free_mailbox(dev, mailbox);
 851
 852 err_out_arm:
 853         if (mthca_is_memfree(dev))
 854                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 855
 856 err_out_ci:
 857         if (mthca_is_memfree(dev))
 858                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 859
 860 err_out_icm:
 861         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 862
 863 err_out:
 864         mthca_free(&dev->cq_table.alloc, cq->cqn);
 865
 866         return err;
 867 }
 868
 869 void mthca_free_cq(struct mthca_dev *dev,
 870                    struct mthca_cq *cq)
 871 {
 872         struct mthca_mailbox *mailbox;
 873         int err;
 874         u8 status;
 875
 876         might_sleep();
 877
 878         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 879         if (IS_ERR(mailbox)) {
 880                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
 881                 return;
 882         }
 883
 884         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 885         if (err)
 886                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
 887         else if (status)
 888                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
 889
 890         if (0) {
 891                 u32 *ctx = mailbox->buf;
 892                 int j;
 893
 894                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
 895                        cq->cqn, cq->cons_index, !!next_cqe_sw(cq));
 896                 for (j = 0; j < 16; ++j)
 897                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
 898         }
 899
 900         spin_lock_irq(&dev->cq_table.lock);
 901         mthca_array_clear(&dev->cq_table.cq,
 902                           cq->cqn & (dev->limits.num_cqs - 1));
 903         spin_unlock_irq(&dev->cq_table.lock);
 904
 905         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
 906                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
 907         else
 908                 synchronize_irq(dev->pdev->irq);
 909
 910         atomic_dec(&cq->refcount);
 911         wait_event(cq->wait, !atomic_read(&cq->refcount));
 912
 913         mthca_free_mr(dev, &cq->mr);
 914         mthca_free_cq_buf(dev, cq);
 915
 916         if (mthca_is_memfree(dev)) {
 917                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 918                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 919         }
 920
 921         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 922         mthca_free(&dev->cq_table.alloc, cq->cqn);
 923         mthca_free_mailbox(dev, mailbox);
 924 }
 925
 926 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
 927 {
 928         int err;
 929
 930         spin_lock_init(&dev->cq_table.lock);
 931
 932         err = mthca_alloc_init(&dev->cq_table.alloc,
 933                                dev->limits.num_cqs,
 934                                (1 << 24) - 1,
 935                                dev->limits.reserved_cqs);
 936         if (err)
 937                 return err;
 938
 939         err = mthca_array_init(&dev->cq_table.cq,
 940                                dev->limits.num_cqs);
 941         if (err)
 942                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 943
 944         return err;
 945 }
 946
 947 void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
 948 {
 949         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
 950         mthca_alloc_cleanup(&dev->cq_table.alloc);
 951 }