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   1 /*
   2  *  linux/arch/arm/mach-pxa/mainstone.c
   3  *
   4  *  Support for the Intel HCDDBBVA0 Development Platform.
   5  *  (go figure how they came up with such name...)
   6  *
   7  *  Author:     Nicolas Pitre
   8  *  Created:    Nov 05, 2002
   9  *  Copyright:  MontaVista Software Inc.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License version 2 as
  13  *  published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/sched.h>
  21 #include <linux/bitops.h>
  22 #include <linux/fb.h>
  23 #include <linux/ioport.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <asm/types.h>
  28 #include <asm/setup.h>
  29 #include <asm/memory.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/hardware.h>
  32 #include <asm/irq.h>
  33 #include <asm/sizes.h>
  34
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/mach/flash.h>
  39
  40 #include <asm/arch/pxa-regs.h>
  41 #include <asm/arch/mainstone.h>
  42 #include <asm/arch/audio.h>
  43 #include <asm/arch/pxafb.h>
  44 #include <asm/arch/mmc.h>
  45 #include <asm/arch/irda.h>
  46 #include <asm/arch/ohci.h>
  47
  48 #include "generic.h"
  49
  50
  51 static unsigned long mainstone_irq_enabled;
  52
  53 static void mainstone_mask_irq(unsigned int irq)
  54 {
  55         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  56         MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
  57 }
  58
  59 static void mainstone_unmask_irq(unsigned int irq)
  60 {
  61         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  62         /* the irq can be acknowledged only if deasserted, so it's done here */
  63         MST_INTSETCLR &= ~(1 << mainstone_irq);
  64         MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
  65 }
  66
  67 static struct irqchip mainstone_irq_chip = {
  68         .ack            = mainstone_mask_irq,
  69         .mask           = mainstone_mask_irq,
  70         .unmask         = mainstone_unmask_irq,
  71 };
  72
  73 static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
  74                                   struct pt_regs *regs)
  75 {
  76         unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
  77         do {
  78                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
  79                 if (likely(pending)) {
  80                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
  81                         desc = irq_desc + irq;
  82                         desc_handle_irq(irq, desc, regs);
  83                 }
  84                 pending = MST_INTSETCLR & mainstone_irq_enabled;
  85         } while (pending);
  86 }
  87
  88 static void __init mainstone_init_irq(void)
  89 {
  90         int irq;
  91
  92         pxa_init_irq();
  93
  94         /* setup extra Mainstone irqs */
  95         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
  96                 set_irq_chip(irq, &mainstone_irq_chip);
  97                 set_irq_handler(irq, do_level_IRQ);
  98                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  99         }
 100         set_irq_flags(MAINSTONE_IRQ(8), 0);
 101         set_irq_flags(MAINSTONE_IRQ(12), 0);
 102
 103         MST_INTMSKENA = 0;
 104         MST_INTSETCLR = 0;
 105
 106         set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
 107         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
 108 }
 109
 110 #ifdef CONFIG_PM
 111
 112 static int mainstone_irq_resume(struct sys_device *dev)
 113 {
 114         MST_INTMSKENA = mainstone_irq_enabled;
 115         return 0;
 116 }
 117
 118 static struct sysdev_class mainstone_irq_sysclass = {
 119         set_kset_name("cpld_irq"),
 120         .resume = mainstone_irq_resume,
 121 };
 122
 123 static struct sys_device mainstone_irq_device = {
 124         .cls = &mainstone_irq_sysclass,
 125 };
 126
 127 static int __init mainstone_irq_device_init(void)
 128 {
 129         int ret = sysdev_class_register(&mainstone_irq_sysclass);
 130         if (ret == 0)
 131                 ret = sysdev_register(&mainstone_irq_device);
 132         return ret;
 133 }
 134
 135 device_initcall(mainstone_irq_device_init);
 136
 137 #endif
 138
 139
 140 static struct resource smc91x_resources[] = {
 141         [0] = {
 142                 .start  = (MST_ETH_PHYS + 0x300),
 143                 .end    = (MST_ETH_PHYS + 0xfffff),
 144                 .flags  = IORESOURCE_MEM,
 145         },
 146         [1] = {
 147                 .start  = MAINSTONE_IRQ(3),
 148                 .end    = MAINSTONE_IRQ(3),
 149                 .flags  = IORESOURCE_IRQ,
 150         }
 151 };
 152
 153 static struct platform_device smc91x_device = {
 154         .name           = "smc91x",
 155         .id             = 0,
 156         .num_resources  = ARRAY_SIZE(smc91x_resources),
 157         .resource       = smc91x_resources,
 158 };
 159
 160 static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
 161 {
 162         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 163                 MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
 164         return 0;
 165 }
 166
 167 static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
 168 {
 169         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 170                 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
 171 }
 172
 173 static long mst_audio_suspend_mask;
 174
 175 static void mst_audio_suspend(void *priv)
 176 {
 177         mst_audio_suspend_mask = MST_MSCWR2;
 178         MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
 179 }
 180
 181 static void mst_audio_resume(void *priv)
 182 {
 183         MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
 184 }
 185
 186 static pxa2xx_audio_ops_t mst_audio_ops = {
 187         .startup        = mst_audio_startup,
 188         .shutdown       = mst_audio_shutdown,
 189         .suspend        = mst_audio_suspend,
 190         .resume         = mst_audio_resume,
 191 };
 192
 193 static struct platform_device mst_audio_device = {
 194         .name           = "pxa2xx-ac97",
 195         .id             = -1,
 196         .dev            = { .platform_data = &mst_audio_ops },
 197 };
 198
 199 static struct resource flash_resources[] = {
 200         [0] = {
 201                 .start  = PXA_CS0_PHYS,
 202                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
 203                 .flags  = IORESOURCE_MEM,
 204         },
 205         [1] = {
 206                 .start  = PXA_CS1_PHYS,
 207                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210 };
 211
 212 static struct mtd_partition mainstoneflash0_partitions[] = {
 213         {
 214                 .name =         "Bootloader",
 215                 .size =         0x00040000,
 216                 .offset =       0,
 217                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
 218         },{
 219                 .name =         "Kernel",
 220                 .size =         0x00400000,
 221                 .offset =       0x00040000,
 222         },{
 223                 .name =         "Filesystem",
 224                 .size =         MTDPART_SIZ_FULL,
 225                 .offset =       0x00440000
 226         }
 227 };
 228
 229 static struct flash_platform_data mst_flash_data[2] = {
 230         {
 231                 .map_name       = "cfi_probe",
 232                 .parts          = mainstoneflash0_partitions,
 233                 .nr_parts       = ARRAY_SIZE(mainstoneflash0_partitions),
 234         }, {
 235                 .map_name       = "cfi_probe",
 236                 .parts          = NULL,
 237                 .nr_parts       = 0,
 238         }
 239 };
 240
 241 static struct platform_device mst_flash_device[2] = {
 242         {
 243                 .name           = "pxa2xx-flash",
 244                 .id             = 0,
 245                 .dev = {
 246                         .platform_data = &mst_flash_data[0],
 247                 },
 248                 .resource = &flash_resources[0],
 249                 .num_resources = 1,
 250         },
 251         {
 252                 .name           = "pxa2xx-flash",
 253                 .id             = 1,
 254                 .dev = {
 255                         .platform_data = &mst_flash_data[1],
 256                 },
 257                 .resource = &flash_resources[1],
 258                 .num_resources = 1,
 259         },
 260 };
 261
 262 static void mainstone_backlight_power(int on)
 263 {
 264         if (on) {
 265                 pxa_gpio_mode(GPIO16_PWM0_MD);
 266                 pxa_set_cken(CKEN0_PWM0, 1);
 267                 PWM_CTRL0 = 0;
 268                 PWM_PWDUTY0 = 0x3ff;
 269                 PWM_PERVAL0 = 0x3ff;
 270         } else {
 271                 PWM_CTRL0 = 0;
 272                 PWM_PWDUTY0 = 0x0;
 273                 PWM_PERVAL0 = 0x3FF;
 274                 pxa_set_cken(CKEN0_PWM0, 0);
 275         }
 276 }
 277
 278 static struct pxafb_mach_info toshiba_ltm04c380k __initdata = {
 279         .pixclock               = 50000,
 280         .xres                   = 640,
 281         .yres                   = 480,
 282         .bpp                    = 16,
 283         .hsync_len              = 1,
 284         .left_margin            = 0x9f,
 285         .right_margin           = 1,
 286         .vsync_len              = 44,
 287         .upper_margin           = 0,
 288         .lower_margin           = 0,
 289         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
 290         .lccr0                  = LCCR0_Act,
 291         .lccr3                  = LCCR3_PCP,
 292         .pxafb_backlight_power  = mainstone_backlight_power,
 293 };
 294
 295 static struct pxafb_mach_info toshiba_ltm035a776c __initdata = {
 296         .pixclock               = 110000,
 297         .xres                   = 240,
 298         .yres                   = 320,
 299         .bpp                    = 16,
 300         .hsync_len              = 4,
 301         .left_margin            = 8,
 302         .right_margin           = 20,
 303         .vsync_len              = 3,
 304         .upper_margin           = 1,
 305         .lower_margin           = 10,
 306         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
 307         .lccr0                  = LCCR0_Act,
 308         .lccr3                  = LCCR3_PCP,
 309         .pxafb_backlight_power  = mainstone_backlight_power,
 310 };
 311
 312 static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
 313 {
 314         int err;
 315
 316         /*
 317          * setup GPIO for PXA27x MMC controller
 318          */
 319         pxa_gpio_mode(GPIO32_MMCCLK_MD);
 320         pxa_gpio_mode(GPIO112_MMCCMD_MD);
 321         pxa_gpio_mode(GPIO92_MMCDAT0_MD);
 322         pxa_gpio_mode(GPIO109_MMCDAT1_MD);
 323         pxa_gpio_mode(GPIO110_MMCDAT2_MD);
 324         pxa_gpio_mode(GPIO111_MMCDAT3_MD);
 325
 326         /* make sure SD/Memory Stick multiplexer's signals
 327          * are routed to MMC controller
 328          */
 329         MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
 330
 331         err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, SA_INTERRUPT,
 332                              "MMC card detect", data);
 333         if (err) {
 334                 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
 335                 return -1;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
 342 {
 343         struct pxamci_platform_data* p_d = dev->platform_data;
 344
 345         if (( 1 << vdd) & p_d->ocr_mask) {
 346                 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
 347                 MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
 348                 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
 349         } else {
 350                 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
 351                 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
 352         }
 353 }
 354
 355 static void mainstone_mci_exit(struct device *dev, void *data)
 356 {
 357         free_irq(MAINSTONE_MMC_IRQ, data);
 358 }
 359
 360 static struct pxamci_platform_data mainstone_mci_platform_data = {
 361         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 362         .init           = mainstone_mci_init,
 363         .setpower       = mainstone_mci_setpower,
 364         .exit           = mainstone_mci_exit,
 365 };
 366
 367 static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
 368 {
 369         unsigned long flags;
 370
 371         local_irq_save(flags);
 372         if (mode & IR_SIRMODE) {
 373                 MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
 374         } else if (mode & IR_FIRMODE) {
 375                 MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
 376         }
 377         if (mode & IR_OFF) {
 378                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
 379         } else {
 380                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
 381         }
 382         local_irq_restore(flags);
 383 }
 384
 385 static struct pxaficp_platform_data mainstone_ficp_platform_data = {
 386         .transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
 387         .transceiver_mode = mainstone_irda_transceiver_mode,
 388 };
 389
 390 static struct platform_device *platform_devices[] __initdata = {
 391         &smc91x_device,
 392         &mst_audio_device,
 393         &mst_flash_device[0],
 394         &mst_flash_device[1],
 395 };
 396
 397 static int mainstone_ohci_init(struct device *dev)
 398 {
 399         /* setup Port1 GPIO pin. */
 400         pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
 401         pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
 402
 403         /* Set the Power Control Polarity Low and Power Sense
 404            Polarity Low to active low. */
 405         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
 406                 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
 407
 408         return 0;
 409 }
 410
 411 static struct pxaohci_platform_data mainstone_ohci_platform_data = {
 412         .port_mode      = PMM_PERPORT_MODE,
 413         .init           = mainstone_ohci_init,
 414 };
 415
 416 static void __init mainstone_init(void)
 417 {
 418         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
 419
 420         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
 421         mst_flash_data[1].width = 4;
 422
 423         /* Compensate for SW7 which swaps the flash banks */
 424         mst_flash_data[SW7].name = "processor-flash";
 425         mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
 426
 427         printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
 428                mst_flash_data[0].name);
 429
 430         /* system bus arbiter setting
 431          * - Core_Park
 432          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
 433          */
 434         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 435
 436         /*
 437          * On Mainstone, we route AC97_SYSCLK via GPIO45 to
 438          * the audio daughter card
 439          */
 440         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
 441
 442         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 443
 444         /* reading Mainstone's "Virtual Configuration Register"
 445            might be handy to select LCD type here */
 446         if (0)
 447                 set_pxa_fb_info(&toshiba_ltm04c380k);
 448         else
 449                 set_pxa_fb_info(&toshiba_ltm035a776c);
 450
 451         pxa_set_mci_info(&mainstone_mci_platform_data);
 452         pxa_set_ficp_info(&mainstone_ficp_platform_data);
 453         pxa_set_ohci_info(&mainstone_ohci_platform_data);
 454 }
 455
 456
 457 static struct map_desc mainstone_io_desc[] __initdata = {
 458         {       /* CPLD */
 459                 .virtual        =  MST_FPGA_VIRT,
 460                 .pfn            = __phys_to_pfn(MST_FPGA_PHYS),
 461                 .length         = 0x00100000,
 462                 .type           = MT_DEVICE
 463         }
 464 };
 465
 466 static void __init mainstone_map_io(void)
 467 {
 468         pxa_map_io();
 469         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 470
 471         /* initialize sleep mode regs (wake-up sources, etc) */
 472         PGSR0 = 0x00008800;
 473         PGSR1 = 0x00000002;
 474         PGSR2 = 0x0001FC00;
 475         PGSR3 = 0x00001F81;
 476         PWER  = 0xC0000002;
 477         PRER  = 0x00000002;
 478         PFER  = 0x00000002;
 479         /*      for use I SRAM as framebuffer.  */
 480         PSLR |= 0xF04;
 481         PCFR = 0x66;
 482         /*      For Keypad wakeup.      */
 483         KPC &=~KPC_ASACT;
 484         KPC |=KPC_AS;
 485         PKWR  = 0x000FD000;
 486         /*      Need read PKWR back after set it.       */
 487         PKWR;
 488 }
 489
 490 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
 491         /* Maintainer: MontaVista Software Inc. */
 492         .phys_io        = 0x40000000,
 493         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
 494         .map_io         = mainstone_map_io,
 495         .init_irq       = mainstone_init_irq,
 496         .timer          = &pxa_timer,
 497         .init_machine   = mainstone_init,
 498 MACHINE_END