Merge branch 'master'
[linux-2.6] / drivers / edac / i82875p_edac.c
1 /*
2  * Intel D82875P Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Thayne Harbaugh
8  * Contributors:
9  *      Wang Zhenyu at intel.com
10  *
11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
12  *
13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
14  */
15
16 #include <linux/config.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
22 #include "edac_mc.h"
23
24 #define i82875p_printk(level, fmt, arg...) \
25         edac_printk(level, "i82875p", fmt, ##arg)
26
27 #define i82875p_mc_printk(mci, level, fmt, arg...) \
28         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
29
30 #ifndef PCI_DEVICE_ID_INTEL_82875_0
31 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
32 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
33
34 #ifndef PCI_DEVICE_ID_INTEL_82875_6
35 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
36 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
37
38 /* four csrows in dual channel, eight in single channel */
39 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
40
41 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
42 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
43                                          *
44                                          * 31:12 block address
45                                          * 11:0  reserved
46                                          */
47
48 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
49                                          *
50                                          *  7:0  DRAM ECC Syndrome
51                                          */
52
53 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
54                                          *
55                                          *  7:1  reserved
56                                          *  0    Error channel 0/1
57                                          */
58
59 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
60                                          *
61                                          * 15:10 reserved
62                                          *  9    non-DRAM lock error (ndlock)
63                                          *  8    Sftwr Generated SMI
64                                          *  7    ECC UE
65                                          *  6    reserved
66                                          *  5    MCH detects unimplemented cycle
67                                          *  4    AGP access outside GA
68                                          *  3    Invalid AGP access
69                                          *  2    Invalid GA translation table
70                                          *  1    Unsupported AGP command
71                                          *  0    ECC CE
72                                          */
73
74 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
75                                          *
76                                          * 15:10 reserved
77                                          *  9    SERR on non-DRAM lock
78                                          *  8    SERR on ECC UE
79                                          *  7    SERR on ECC CE
80                                          *  6    target abort on high exception
81                                          *  5    detect unimplemented cyc
82                                          *  4    AGP access outside of GA
83                                          *  3    SERR on invalid AGP access
84                                          *  2    invalid translation table
85                                          *  1    SERR on unsupported AGP command
86                                          *  0    reserved
87                                          */
88
89 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
90 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
91                                          *
92                                          * 15:10 reserved
93                                          *  9    fast back-to-back - ro 0
94                                          *  8    SERR enable - ro 0
95                                          *  7    addr/data stepping - ro 0
96                                          *  6    parity err enable - ro 0
97                                          *  5    VGA palette snoop - ro 0
98                                          *  4    mem wr & invalidate - ro 0
99                                          *  3    special cycle - ro 0
100                                          *  2    bus master - ro 0
101                                          *  1    mem access dev6 - 0(dis),1(en)
102                                          *  0    IO access dev3 - 0(dis),1(en)
103                                          */
104
105 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
106                                          *
107                                          * 31:12 mem base addr [31:12]
108                                          * 11:4  address mask - ro 0
109                                          *  3    prefetchable - ro 0(non),1(pre)
110                                          *  2:1  mem type - ro 0
111                                          *  0    mem space - ro 0
112                                          */
113
114 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
115
116 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
117 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
118                                          *
119                                          *  7    reserved
120                                          *  6:0  64MiB row boundary addr
121                                          */
122
123 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
124                                          *
125                                          *  7    reserved
126                                          *  6:4  row attr row 1
127                                          *  3    reserved
128                                          *  2:0  row attr row 0
129                                          *
130                                          * 000 =  4KiB
131                                          * 001 =  8KiB
132                                          * 010 = 16KiB
133                                          * 011 = 32KiB
134                                          */
135
136 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
137                                          *
138                                          * 31:30 reserved
139                                          * 29    init complete
140                                          * 28:23 reserved
141                                          * 22:21 nr chan 00=1,01=2
142                                          * 20    reserved
143                                          * 19:18 Data Integ Mode 00=none,01=ecc
144                                          * 17:11 reserved
145                                          * 10:8  refresh mode
146                                          *  7    reserved
147                                          *  6:4  mode select
148                                          *  3:2  reserved
149                                          *  1:0  DRAM type 01=DDR
150                                          */
151
152 enum i82875p_chips {
153         I82875P = 0,
154 };
155
156 struct i82875p_pvt {
157         struct pci_dev *ovrfl_pdev;
158         void __iomem *ovrfl_window;
159 };
160
161 struct i82875p_dev_info {
162         const char *ctl_name;
163 };
164
165 struct i82875p_error_info {
166         u16 errsts;
167         u32 eap;
168         u8 des;
169         u8 derrsyn;
170         u16 errsts2;
171 };
172
173 static const struct i82875p_dev_info i82875p_devs[] = {
174         [I82875P] = {
175                 .ctl_name = "i82875p"
176         },
177 };
178
179 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
180                                          * already registered driver
181                                          */
182
183 static int i82875p_registered = 1;
184
185 static void i82875p_get_error_info(struct mem_ctl_info *mci,
186                 struct i82875p_error_info *info)
187 {
188         /*
189          * This is a mess because there is no atomic way to read all the
190          * registers at once and the registers can transition from CE being
191          * overwritten by UE.
192          */
193         pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
194         pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
195         pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
196         pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
197         pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);
198
199         pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
200
201         /*
202          * If the error is the same then we can for both reads then
203          * the first set of reads is valid.  If there is a change then
204          * there is a CE no info and the second set of reads is valid
205          * and should be UE info.
206          */
207         if (!(info->errsts2 & 0x0081))
208                 return;
209
210         if ((info->errsts ^ info->errsts2) & 0x0081) {
211                 pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
212                 pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
213                 pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
214                                 &info->derrsyn);
215         }
216 }
217
218 static int i82875p_process_error_info(struct mem_ctl_info *mci,
219                 struct i82875p_error_info *info, int handle_errors)
220 {
221         int row, multi_chan;
222
223         multi_chan = mci->csrows[0].nr_channels - 1;
224
225         if (!(info->errsts2 & 0x0081))
226                 return 0;
227
228         if (!handle_errors)
229                 return 1;
230
231         if ((info->errsts ^ info->errsts2) & 0x0081) {
232                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
233                 info->errsts = info->errsts2;
234         }
235
236         info->eap >>= PAGE_SHIFT;
237         row = edac_mc_find_csrow_by_page(mci, info->eap);
238
239         if (info->errsts & 0x0080)
240                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
241         else
242                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
243                                 multi_chan ? (info->des & 0x1) : 0,
244                                 "i82875p CE");
245
246         return 1;
247 }
248
249 static void i82875p_check(struct mem_ctl_info *mci)
250 {
251         struct i82875p_error_info info;
252
253         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
254         i82875p_get_error_info(mci, &info);
255         i82875p_process_error_info(mci, &info, 1);
256 }
257
258 #ifdef CONFIG_PROC_FS
259 extern int pci_proc_attach_device(struct pci_dev *);
260 #endif
261
262 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
263 {
264         int rc = -ENODEV;
265         int index;
266         struct mem_ctl_info *mci = NULL;
267         struct i82875p_pvt *pvt = NULL;
268         unsigned long last_cumul_size;
269         struct pci_dev *ovrfl_pdev;
270         void __iomem *ovrfl_window = NULL;
271         u32 drc;
272         u32 drc_chan;           /* Number of channels 0=1chan,1=2chan */
273         u32 nr_chans;
274         u32 drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
275         struct i82875p_error_info discard;
276
277         debugf0("%s()\n", __func__);
278         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
279
280         if (!ovrfl_pdev) {
281                 /*
282                  * Intel tells BIOS developers to hide device 6 which
283                  * configures the overflow device access containing
284                  * the DRBs - this is where we expose device 6.
285                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
286                  */
287                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
288                 ovrfl_pdev =
289                         pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
290
291                 if (!ovrfl_pdev)
292                         return -ENODEV;
293         }
294
295 #ifdef CONFIG_PROC_FS
296         if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
297                 i82875p_printk(KERN_ERR,
298                         "%s(): Failed to attach overflow device\n", __func__);
299                 return -ENODEV;
300         }
301 #endif
302                                 /* CONFIG_PROC_FS */
303         if (pci_enable_device(ovrfl_pdev)) {
304                 i82875p_printk(KERN_ERR,
305                         "%s(): Failed to enable overflow device\n", __func__);
306                 return -ENODEV;
307         }
308
309         if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
310 #ifdef CORRECT_BIOS
311                 goto fail0;
312 #endif
313         }
314
315         /* cache is irrelevant for PCI bus reads/writes */
316         ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
317                                 pci_resource_len(ovrfl_pdev, 0));
318
319         if (!ovrfl_window) {
320                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
321                         __func__);
322                 goto fail1;
323         }
324
325         /* need to find out the number of channels */
326         drc = readl(ovrfl_window + I82875P_DRC);
327         drc_chan = ((drc >> 21) & 0x1);
328         nr_chans = drc_chan + 1;
329
330         drc_ddim = (drc >> 18) & 0x1;
331         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
332                                 nr_chans);
333
334         if (!mci) {
335                 rc = -ENOMEM;
336                 goto fail2;
337         }
338
339         debugf3("%s(): init mci\n", __func__);
340         mci->pdev = pdev;
341         mci->mtype_cap = MEM_FLAG_DDR;
342         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
343         mci->edac_cap = EDAC_FLAG_UNKNOWN;
344         /* adjust FLAGS */
345
346         mci->mod_name = EDAC_MOD_STR;
347         mci->mod_ver = "$Revision: 1.5.2.11 $";
348         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
349         mci->edac_check = i82875p_check;
350         mci->ctl_page_to_phys = NULL;
351         debugf3("%s(): init pvt\n", __func__);
352         pvt = (struct i82875p_pvt *) mci->pvt_info;
353         pvt->ovrfl_pdev = ovrfl_pdev;
354         pvt->ovrfl_window = ovrfl_window;
355
356         /*
357          * The dram row boundary (DRB) reg values are boundary address
358          * for each DRAM row with a granularity of 32 or 64MB (single/dual
359          * channel operation).  DRB regs are cumulative; therefore DRB7 will
360          * contain the total memory contained in all eight rows.
361          */
362         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
363                 u8 value;
364                 u32 cumul_size;
365                 struct csrow_info *csrow = &mci->csrows[index];
366
367                 value = readb(ovrfl_window + I82875P_DRB + index);
368                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
369                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
370                         cumul_size);
371
372                 if (cumul_size == last_cumul_size)
373                         continue;       /* not populated */
374
375                 csrow->first_page = last_cumul_size;
376                 csrow->last_page = cumul_size - 1;
377                 csrow->nr_pages = cumul_size - last_cumul_size;
378                 last_cumul_size = cumul_size;
379                 csrow->grain = 1 << 12;  /* I82875P_EAP has 4KiB reolution */
380                 csrow->mtype = MEM_DDR;
381                 csrow->dtype = DEV_UNKNOWN;
382                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
383         }
384
385         i82875p_get_error_info(mci, &discard);  /* clear counters */
386
387         if (edac_mc_add_mc(mci)) {
388                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
389                 goto fail3;
390         }
391
392         /* get this far and it's successful */
393         debugf3("%s(): success\n", __func__);
394         return 0;
395
396 fail3:
397         edac_mc_free(mci);
398
399 fail2:
400         iounmap(ovrfl_window);
401
402 fail1:
403         pci_release_regions(ovrfl_pdev);
404
405 #ifdef CORRECT_BIOS
406 fail0:
407 #endif
408         pci_disable_device(ovrfl_pdev);
409         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
410         return rc;
411 }
412
413 /* returns count (>= 0), or negative on error */
414 static int __devinit i82875p_init_one(struct pci_dev *pdev,
415                 const struct pci_device_id *ent)
416 {
417         int rc;
418
419         debugf0("%s()\n", __func__);
420         i82875p_printk(KERN_INFO, "i82875p init one\n");
421
422         if (pci_enable_device(pdev) < 0)
423                 return -EIO;
424
425         rc = i82875p_probe1(pdev, ent->driver_data);
426
427         if (mci_pdev == NULL)
428                 mci_pdev = pci_dev_get(pdev);
429
430         return rc;
431 }
432
433 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
434 {
435         struct mem_ctl_info *mci;
436         struct i82875p_pvt *pvt = NULL;
437
438         debugf0("%s()\n", __func__);
439
440         if ((mci = edac_mc_del_mc(pdev)) == NULL)
441                 return;
442
443         pvt = (struct i82875p_pvt *) mci->pvt_info;
444
445         if (pvt->ovrfl_window)
446                 iounmap(pvt->ovrfl_window);
447
448         if (pvt->ovrfl_pdev) {
449 #ifdef CORRECT_BIOS
450                 pci_release_regions(pvt->ovrfl_pdev);
451 #endif                          /*CORRECT_BIOS */
452                 pci_disable_device(pvt->ovrfl_pdev);
453                 pci_dev_put(pvt->ovrfl_pdev);
454         }
455
456         edac_mc_free(mci);
457 }
458
459 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
460         {
461                 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
462                 I82875P
463         },
464         {
465                 0,
466         }       /* 0 terminated list. */
467 };
468
469 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
470
471 static struct pci_driver i82875p_driver = {
472         .name = EDAC_MOD_STR,
473         .probe = i82875p_init_one,
474         .remove = __devexit_p(i82875p_remove_one),
475         .id_table = i82875p_pci_tbl,
476 };
477
478 static int __init i82875p_init(void)
479 {
480         int pci_rc;
481
482         debugf3("%s()\n", __func__);
483         pci_rc = pci_register_driver(&i82875p_driver);
484
485         if (pci_rc < 0)
486                 goto fail0;
487
488         if (mci_pdev == NULL) {
489                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
490                                 PCI_DEVICE_ID_INTEL_82875_0, NULL);
491
492                 if (!mci_pdev) {
493                         debugf0("875p pci_get_device fail\n");
494                         pci_rc = -ENODEV;
495                         goto fail1;
496                 }
497
498                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
499
500                 if (pci_rc < 0) {
501                         debugf0("875p init fail\n");
502                         pci_rc = -ENODEV;
503                         goto fail1;
504                 }
505         }
506
507         return 0;
508
509 fail1:
510         pci_unregister_driver(&i82875p_driver);
511
512 fail0:
513         if (mci_pdev != NULL)
514                 pci_dev_put(mci_pdev);
515
516         return pci_rc;
517 }
518
519 static void __exit i82875p_exit(void)
520 {
521         debugf3("%s()\n", __func__);
522
523         pci_unregister_driver(&i82875p_driver);
524
525         if (!i82875p_registered) {
526                 i82875p_remove_one(mci_pdev);
527                 pci_dev_put(mci_pdev);
528         }
529 }
530
531 module_init(i82875p_init);
532 module_exit(i82875p_exit);
533
534 MODULE_LICENSE("GPL");
535 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
536 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");