2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/acpi.h>
23 #include <linux/module.h>
27 #include <asm/mpspec.h>
28 #include <asm/pgalloc.h>
29 #include <asm/io_apic.h>
30 #include <asm/proto.h>
32 #include <asm/bios_ebda.h>
34 #include <mach_apic.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
45 int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
47 static int mp_current_pci_id = 0;
48 /* I/O APIC entries */
49 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51 /* # of MP IRQ source entries */
52 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54 /* MP IRQ source entries */
60 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
61 = {[0 ... NR_CPUS - 1] = BAD_APICID };
62 void *x86_bios_cpu_apicid_early_ptr;
64 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
65 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
68 * Intel MP BIOS table parsing routines:
72 * Checksum an MP configuration block.
75 static int __init mpf_checksum(unsigned char *mp, int len)
85 void __cpuinit generic_processor_info(int apicid, int version)
90 if (num_processors >= NR_CPUS) {
91 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
92 " Processor ignored.\n", NR_CPUS);
96 if (num_processors >= maxcpus) {
97 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
98 " Processor ignored.\n", maxcpus);
103 cpus_complement(tmp_map, cpu_present_map);
104 cpu = first_cpu(tmp_map);
106 physid_set(apicid, phys_cpu_present_map);
107 if (apicid == boot_cpu_physical_apicid) {
109 * x86_bios_cpu_apicid is required to have processors listed
110 * in same order as logical cpu numbers. Hence the first
111 * entry is BSP, and so on.
115 /* are we being called early in kernel startup? */
116 if (x86_cpu_to_apicid_early_ptr) {
117 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
118 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
120 cpu_to_apicid[cpu] = apicid;
121 bios_cpu_apicid[cpu] = apicid;
123 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
124 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
127 cpu_set(cpu, cpu_possible_map);
128 cpu_set(cpu, cpu_present_map);
131 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
133 char *bootup_cpu = "";
135 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
139 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
140 bootup_cpu = " (Bootup-CPU)";
141 boot_cpu_physical_apicid = m->mpc_apicid;
144 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
145 generic_processor_info(m->mpc_apicid, 0);
148 static void __init MP_bus_info(struct mpc_config_bus *m)
152 memcpy(str, m->mpc_bustype, 6);
154 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
156 if (strncmp(str, "ISA", 3) == 0) {
157 set_bit(m->mpc_busid, mp_bus_not_pci);
158 } else if (strncmp(str, "PCI", 3) == 0) {
159 clear_bit(m->mpc_busid, mp_bus_not_pci);
160 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
163 printk(KERN_ERR "Unknown bustype %s\n", str);
167 static int bad_ioapic(unsigned long address)
169 if (nr_ioapics >= MAX_IO_APICS) {
170 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
171 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
172 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
175 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
176 " found in table, skipping!\n");
182 static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
184 if (!(m->mpc_flags & MPC_APIC_USABLE))
187 printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid,
190 if (bad_ioapic(m->mpc_apicaddr))
193 mp_ioapics[nr_ioapics] = *m;
197 static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
199 mp_irqs[mp_irq_entries] = *m;
200 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
201 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
202 m->mpc_irqtype, m->mpc_irqflag & 3,
203 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
204 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
205 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
206 panic("Max # of irq sources exceeded!!\n");
209 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
211 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
212 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
213 m->mpc_irqtype, m->mpc_irqflag & 3,
214 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
215 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
221 static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
224 int count = sizeof(*mpc);
225 unsigned char *mpt = ((unsigned char *)mpc) + count;
227 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
228 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
229 mpc->mpc_signature[0],
230 mpc->mpc_signature[1],
231 mpc->mpc_signature[2], mpc->mpc_signature[3]);
234 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
235 printk(KERN_ERR "MPTABLE: checksum error!\n");
238 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
239 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
243 if (!mpc->mpc_lapic) {
244 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
247 memcpy(str, mpc->mpc_oem, 8);
249 printk(KERN_INFO "MPTABLE: OEM ID: %s ", str);
251 memcpy(str, mpc->mpc_productid, 12);
253 printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
255 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
257 /* save the local APIC address, it might be non-default */
259 mp_lapic_addr = mpc->mpc_lapic;
265 * Now process the configuration blocks.
267 while (count < mpc->mpc_length) {
271 struct mpc_config_processor *m =
272 (struct mpc_config_processor *)mpt;
274 MP_processor_info(m);
281 struct mpc_config_bus *m =
282 (struct mpc_config_bus *)mpt;
290 struct mpc_config_ioapic *m =
291 (struct mpc_config_ioapic *)mpt;
299 struct mpc_config_intsrc *m =
300 (struct mpc_config_intsrc *)mpt;
309 struct mpc_config_lintsrc *m =
310 (struct mpc_config_lintsrc *)mpt;
318 setup_apic_routing();
320 printk(KERN_ERR "MPTABLE: no processors registered!\n");
321 return num_processors;
324 static int __init ELCR_trigger(unsigned int irq)
328 port = 0x4d0 + (irq >> 3);
329 return (inb(port) >> (irq & 7)) & 1;
332 static void __init construct_default_ioirq_mptable(int mpc_default_type)
334 struct mpc_config_intsrc intsrc;
336 int ELCR_fallback = 0;
338 intsrc.mpc_type = MP_INTSRC;
339 intsrc.mpc_irqflag = 0; /* conforming */
340 intsrc.mpc_srcbus = 0;
341 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
343 intsrc.mpc_irqtype = mp_INT;
346 * If true, we have an ISA/PCI system with no IRQ entries
347 * in the MP table. To prevent the PCI interrupts from being set up
348 * incorrectly, we try to use the ELCR. The sanity check to see if
349 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
350 * never be level sensitive, so we simply see if the ELCR agrees.
351 * If it does, we assume it's valid.
353 if (mpc_default_type == 5) {
354 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
355 "falling back to ELCR\n");
357 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
359 printk(KERN_ERR "ELCR contains invalid data... "
363 "Using ELCR to identify PCI interrupts\n");
368 for (i = 0; i < 16; i++) {
369 switch (mpc_default_type) {
371 if (i == 0 || i == 13)
372 continue; /* IRQ0 & IRQ13 not connected */
376 continue; /* IRQ2 is never connected */
381 * If the ELCR indicates a level-sensitive interrupt, we
382 * copy that information over to the MP table in the
383 * irqflag field (level sensitive, active high polarity).
386 intsrc.mpc_irqflag = 13;
388 intsrc.mpc_irqflag = 0;
391 intsrc.mpc_srcbusirq = i;
392 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
393 MP_intsrc_info(&intsrc);
396 intsrc.mpc_irqtype = mp_ExtINT;
397 intsrc.mpc_srcbusirq = 0;
398 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
399 MP_intsrc_info(&intsrc);
402 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
404 struct mpc_config_processor processor;
405 struct mpc_config_bus bus;
406 struct mpc_config_ioapic ioapic;
407 struct mpc_config_lintsrc lintsrc;
408 int linttypes[2] = { mp_ExtINT, mp_NMI };
412 * local APIC has default address
414 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
417 * 2 CPUs, numbered 0 & 1.
419 processor.mpc_type = MP_PROCESSOR;
420 processor.mpc_apicver = 0;
421 processor.mpc_cpuflag = CPU_ENABLED;
422 processor.mpc_cpufeature = 0;
423 processor.mpc_featureflag = 0;
424 processor.mpc_reserved[0] = 0;
425 processor.mpc_reserved[1] = 0;
426 for (i = 0; i < 2; i++) {
427 processor.mpc_apicid = i;
428 MP_processor_info(&processor);
431 bus.mpc_type = MP_BUS;
433 switch (mpc_default_type) {
435 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
440 memcpy(bus.mpc_bustype, "ISA ", 6);
444 if (mpc_default_type > 4) {
446 memcpy(bus.mpc_bustype, "PCI ", 6);
450 ioapic.mpc_type = MP_IOAPIC;
451 ioapic.mpc_apicid = 2;
452 ioapic.mpc_apicver = 0;
453 ioapic.mpc_flags = MPC_APIC_USABLE;
454 ioapic.mpc_apicaddr = 0xFEC00000;
455 MP_ioapic_info(&ioapic);
458 * We set up most of the low 16 IO-APIC pins according to MPS rules.
460 construct_default_ioirq_mptable(mpc_default_type);
462 lintsrc.mpc_type = MP_LINTSRC;
463 lintsrc.mpc_irqflag = 0; /* conforming */
464 lintsrc.mpc_srcbusid = 0;
465 lintsrc.mpc_srcbusirq = 0;
466 lintsrc.mpc_destapic = MP_APIC_ALL;
467 for (i = 0; i < 2; i++) {
468 lintsrc.mpc_irqtype = linttypes[i];
469 lintsrc.mpc_destapiclint = i;
470 MP_lintsrc_info(&lintsrc);
474 static struct intel_mp_floating *mpf_found;
477 * Scan the memory blocks for an SMP configuration block.
479 static void __init __get_smp_config(unsigned early)
481 struct intel_mp_floating *mpf = mpf_found;
483 if (acpi_lapic && early)
486 * ACPI supports both logical (e.g. Hyper-Threading) and physical
487 * processors, where MPS only supports physical.
489 if (acpi_lapic && acpi_ioapic) {
490 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
493 } else if (acpi_lapic)
494 printk(KERN_INFO "Using ACPI for processor (LAPIC) "
495 "configuration information\n");
497 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
498 mpf->mpf_specification);
501 * Now see if we need to read further.
503 if (mpf->mpf_feature1 != 0) {
506 * local APIC has default address
508 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
512 printk(KERN_INFO "Default MP configuration #%d\n",
514 construct_default_ISA_mptable(mpf->mpf_feature1);
516 } else if (mpf->mpf_physptr) {
519 * Read the physical hardware table. Anything here will
520 * override the defaults.
522 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
523 smp_found_config = 0;
525 "BIOS bug, MP table errors detected!...\n");
526 printk(KERN_ERR "... disabling SMP support. "
527 "(tell your hw vendor)\n");
534 * If there are no explicit MP IRQ entries, then we are
535 * broken. We set up most of the low 16 IO-APIC pins to
536 * ISA defaults and hope it will work.
538 if (!mp_irq_entries) {
539 struct mpc_config_bus bus;
541 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
542 "using default mptable. "
543 "(tell your hw vendor)\n");
545 bus.mpc_type = MP_BUS;
547 memcpy(bus.mpc_bustype, "ISA ", 6);
550 construct_default_ioirq_mptable(0);
557 printk(KERN_INFO "Processors: %d\n", num_processors);
559 * Only use the first configuration found.
563 void __init early_get_smp_config(void)
568 void __init get_smp_config(void)
573 static int __init smp_scan_config(unsigned long base, unsigned long length,
576 extern void __bad_mpf_size(void);
577 unsigned int *bp = phys_to_virt(base);
578 struct intel_mp_floating *mpf;
580 Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
581 if (sizeof(*mpf) != 16)
585 mpf = (struct intel_mp_floating *)bp;
586 if ((*bp == SMP_MAGIC_IDENT) &&
587 (mpf->mpf_length == 1) &&
588 !mpf_checksum((unsigned char *)bp, 16) &&
589 ((mpf->mpf_specification == 1)
590 || (mpf->mpf_specification == 4))) {
592 smp_found_config = 1;
598 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
599 if (mpf->mpf_physptr)
600 reserve_bootmem_generic(mpf->mpf_physptr,
610 static void __init __find_smp_config(unsigned reserve)
612 unsigned int address;
615 * FIXME: Linux assumes you have 640K of base ram..
616 * this continues the error...
618 * 1) Scan the bottom 1K for a signature
619 * 2) Scan the top 1K of base RAM
620 * 3) Scan the 64K of bios
622 if (smp_scan_config(0x0, 0x400, reserve) ||
623 smp_scan_config(639 * 0x400, 0x400, reserve) ||
624 smp_scan_config(0xF0000, 0x10000, reserve))
627 * If it is an SMP machine we should know now.
629 * there is a real-mode segmented pointer pointing to the
630 * 4K EBDA area at 0x40E, calculate and scan it here.
632 * NOTE! There are Linux loaders that will corrupt the EBDA
633 * area, and as such this kind of SMP config may be less
634 * trustworthy, simply because the SMP table may have been
635 * stomped on during early boot. These loaders are buggy and
638 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
641 address = get_bios_ebda();
643 smp_scan_config(address, 0x400, reserve);
646 void __init early_find_smp_config(void)
648 __find_smp_config(0);
651 void __init find_smp_config(void)
653 __find_smp_config(1);
656 /* --------------------------------------------------------------------------
657 ACPI-based MP Configuration
658 -------------------------------------------------------------------------- */
662 void __init mp_register_lapic_address(u64 address)
664 mp_lapic_addr = (unsigned long)address;
665 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
666 if (boot_cpu_physical_apicid == -1U)
667 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
670 void __cpuinit mp_register_lapic(u8 id, u8 enabled)
677 generic_processor_info(id, 0);
681 #define MP_MAX_IOAPIC_PIN 127
683 static struct mp_ioapic_routing {
687 u32 pin_programmed[4];
688 } mp_ioapic_routing[MAX_IO_APICS];
690 static int mp_find_ioapic(int gsi)
694 /* Find the IOAPIC that manages this GSI. */
695 for (i = 0; i < nr_ioapics; i++) {
696 if ((gsi >= mp_ioapic_routing[i].gsi_base)
697 && (gsi <= mp_ioapic_routing[i].gsi_end))
701 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
705 static u8 uniq_ioapic_id(u8 id)
708 DECLARE_BITMAP(used, 256);
709 bitmap_zero(used, 256);
710 for (i = 0; i < nr_ioapics; i++) {
711 struct mpc_config_ioapic *ia = &mp_ioapics[i];
712 __set_bit(ia->mpc_apicid, used);
714 if (!test_bit(id, used))
716 return find_first_zero_bit(used, 256);
719 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
723 if (bad_ioapic(address))
728 mp_ioapics[idx].mpc_type = MP_IOAPIC;
729 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
730 mp_ioapics[idx].mpc_apicaddr = address;
732 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
733 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
734 mp_ioapics[idx].mpc_apicver = 0;
737 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
738 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
740 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
741 mp_ioapic_routing[idx].gsi_base = gsi_base;
742 mp_ioapic_routing[idx].gsi_end = gsi_base +
743 io_apic_get_redir_entries(idx);
745 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
746 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
747 mp_ioapics[idx].mpc_apicaddr,
748 mp_ioapic_routing[idx].gsi_base,
749 mp_ioapic_routing[idx].gsi_end);
754 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
756 struct mpc_config_intsrc intsrc;
761 * Convert 'gsi' to 'ioapic.pin'.
763 ioapic = mp_find_ioapic(gsi);
766 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
769 * TBD: This check is for faulty timer entries, where the override
770 * erroneously sets the trigger to level, resulting in a HUGE
771 * increase of timer interrupts!
773 if ((bus_irq == 0) && (trigger == 3))
776 intsrc.mpc_type = MP_INTSRC;
777 intsrc.mpc_irqtype = mp_INT;
778 intsrc.mpc_irqflag = (trigger << 2) | polarity;
779 intsrc.mpc_srcbus = MP_ISA_BUS;
780 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
781 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
782 intsrc.mpc_dstirq = pin; /* INTIN# */
784 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
785 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
786 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
787 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
789 mp_irqs[mp_irq_entries] = intsrc;
790 if (++mp_irq_entries == MAX_IRQ_SOURCES)
791 panic("Max # of irq sources exceeded!\n");
794 void __init mp_config_acpi_legacy_irqs(void)
796 struct mpc_config_intsrc intsrc;
801 * Fabricate the legacy ISA bus (bus #31).
803 set_bit(MP_ISA_BUS, mp_bus_not_pci);
806 * Locate the IOAPIC that manages the ISA IRQs (0-15).
808 ioapic = mp_find_ioapic(0);
812 intsrc.mpc_type = MP_INTSRC;
813 intsrc.mpc_irqflag = 0; /* Conforming */
814 intsrc.mpc_srcbus = MP_ISA_BUS;
815 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
818 * Use the default configuration for the IRQs 0-15. Unless
819 * overridden by (MADT) interrupt source override entries.
821 for (i = 0; i < 16; i++) {
824 for (idx = 0; idx < mp_irq_entries; idx++) {
825 struct mpc_config_intsrc *irq = mp_irqs + idx;
827 /* Do we already have a mapping for this ISA IRQ? */
828 if (irq->mpc_srcbus == MP_ISA_BUS
829 && irq->mpc_srcbusirq == i)
832 /* Do we already have a mapping for this IOAPIC pin */
833 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
834 (irq->mpc_dstirq == i))
838 if (idx != mp_irq_entries) {
839 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
840 continue; /* IRQ already used */
843 intsrc.mpc_irqtype = mp_INT;
844 intsrc.mpc_srcbusirq = i; /* Identity mapped */
845 intsrc.mpc_dstirq = i;
847 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
848 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
849 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
850 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
853 mp_irqs[mp_irq_entries] = intsrc;
854 if (++mp_irq_entries == MAX_IRQ_SOURCES)
855 panic("Max # of irq sources exceeded!\n");
859 int mp_register_gsi(u32 gsi, int triggering, int polarity)
865 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
868 /* Don't set up the ACPI SCI because it's already set up */
869 if (acpi_gbl_FADT.sci_interrupt == gsi)
872 ioapic = mp_find_ioapic(gsi);
874 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
878 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
881 * Avoid pin reprogramming. PRTs typically include entries
882 * with redundant pin->gsi mappings (but unique PCI devices);
883 * we only program the IOAPIC on the first.
885 bit = ioapic_pin % 32;
886 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
888 printk(KERN_ERR "Invalid reference to IOAPIC pin "
889 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
893 if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
894 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
895 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
899 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
901 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
902 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
903 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
906 #endif /* CONFIG_ACPI */