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   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  *
   6  * Author: Jon Mason <jdmason@us.ibm.com>
   7  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44
  45 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  46 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  47         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  48
  49 /* we need these for register space address calculation */
  50 #define START_ADDRESS           0xfe000000
  51 #define CHASSIS_BASE            0
  52 #define ONE_BASED_CHASSIS_NUM   1
  53
  54 /* register offsets inside the host bridge space */
  55 #define PHB_CSR_OFFSET          0x0110
  56 #define PHB_PLSSR_OFFSET        0x0120
  57 #define PHB_CONFIG_RW_OFFSET    0x0160
  58 #define PHB_IOBASE_BAR_LOW      0x0170
  59 #define PHB_IOBASE_BAR_HIGH     0x0180
  60 #define PHB_MEM_1_LOW           0x0190
  61 #define PHB_MEM_1_HIGH          0x01A0
  62 #define PHB_IO_ADDR_SIZE        0x01B0
  63 #define PHB_MEM_1_SIZE          0x01C0
  64 #define PHB_MEM_ST_OFFSET       0x01D0
  65 #define PHB_AER_OFFSET          0x0200
  66 #define PHB_CONFIG_0_HIGH       0x0220
  67 #define PHB_CONFIG_0_LOW        0x0230
  68 #define PHB_CONFIG_0_END        0x0240
  69 #define PHB_MEM_2_LOW           0x02B0
  70 #define PHB_MEM_2_HIGH          0x02C0
  71 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  72 #define PHB_MEM_2_SIZE_LOW      0x02E0
  73 #define PHB_DOSHOLE_OFFSET      0x08E0
  74
  75 /* PHB_CONFIG_RW */
  76 #define PHB_TCE_ENABLE          0x20000000
  77 #define PHB_SLOT_DISABLE        0x1C000000
  78 #define PHB_DAC_DISABLE         0x01000000
  79 #define PHB_MEM2_ENABLE         0x00400000
  80 #define PHB_MCSR_ENABLE         0x00100000
  81 /* TAR (Table Address Register) */
  82 #define TAR_SW_BITS             0x0000ffffffff800fUL
  83 #define TAR_VALID               0x0000000000000008UL
  84 /* CSR (Channel/DMA Status Register) */
  85 #define CSR_AGENT_MASK          0xffe0ffff
  86
  87 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  88 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  89 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) /* max dev->bus->number */
  90 #define PHBS_PER_CALGARY        4
  91
  92 /* register offsets in Calgary's internal register space */
  93 static const unsigned long tar_offsets[] = {
  94         0x0580 /* TAR0 */,
  95         0x0588 /* TAR1 */,
  96         0x0590 /* TAR2 */,
  97         0x0598 /* TAR3 */
  98 };
  99
 100 static const unsigned long split_queue_offsets[] = {
 101         0x4870 /* SPLIT QUEUE 0 */,
 102         0x5870 /* SPLIT QUEUE 1 */,
 103         0x6870 /* SPLIT QUEUE 2 */,
 104         0x7870 /* SPLIT QUEUE 3 */
 105 };
 106
 107 static const unsigned long phb_offsets[] = {
 108         0x8000 /* PHB0 */,
 109         0x9000 /* PHB1 */,
 110         0xA000 /* PHB2 */,
 111         0xB000 /* PHB3 */
 112 };
 113
 114 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 115 static int translate_empty_slots __read_mostly = 0;
 116 static int calgary_detected __read_mostly = 0;
 117
 118 struct calgary_bus_info {
 119         void *tce_space;
 120         int translation_disabled;
 121         signed char phbid;
 122 };
 123
 124 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 125
 126 static void tce_cache_blast(struct iommu_table *tbl);
 127
 128 /* enable this to stress test the chip's TCE cache */
 129 #ifdef CONFIG_IOMMU_DEBUG
 130 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 131 {
 132         tce_cache_blast(tbl);
 133 }
 134 #else
 135 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 136 {
 137 }
 138 #endif /* BLAST_TCE_CACHE_ON_UNMAP */
 139
 140 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 141 {
 142         unsigned int npages;
 143
 144         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 145         npages >>= PAGE_SHIFT;
 146
 147         return npages;
 148 }
 149
 150 static inline int translate_phb(struct pci_dev* dev)
 151 {
 152         int disabled = bus_info[dev->bus->number].translation_disabled;
 153         return !disabled;
 154 }
 155
 156 static void iommu_range_reserve(struct iommu_table *tbl,
 157         unsigned long start_addr, unsigned int npages)
 158 {
 159         unsigned long index;
 160         unsigned long end;
 161
 162         index = start_addr >> PAGE_SHIFT;
 163
 164         /* bail out if we're asked to reserve a region we don't cover */
 165         if (index >= tbl->it_size)
 166                 return;
 167
 168         end = index + npages;
 169         if (end > tbl->it_size) /* don't go off the table */
 170                 end = tbl->it_size;
 171
 172         while (index < end) {
 173                 if (test_bit(index, tbl->it_map))
 174                         printk(KERN_ERR "Calgary: entry already allocated at "
 175                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 176                                index, tbl, start_addr, npages);
 177                 ++index;
 178         }
 179         set_bit_string(tbl->it_map, start_addr >> PAGE_SHIFT, npages);
 180 }
 181
 182 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 183         unsigned int npages)
 184 {
 185         unsigned long offset;
 186
 187         BUG_ON(npages == 0);
 188
 189         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 190                                        tbl->it_size, npages);
 191         if (offset == ~0UL) {
 192                 tce_cache_blast(tbl);
 193                 offset = find_next_zero_string(tbl->it_map, 0,
 194                                                tbl->it_size, npages);
 195                 if (offset == ~0UL) {
 196                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 197                         if (panic_on_overflow)
 198                                 panic("Calgary: fix the allocator.\n");
 199                         else
 200                                 return bad_dma_address;
 201                 }
 202         }
 203
 204         set_bit_string(tbl->it_map, offset, npages);
 205         tbl->it_hint = offset + npages;
 206         BUG_ON(tbl->it_hint > tbl->it_size);
 207
 208         return offset;
 209 }
 210
 211 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 212         unsigned int npages, int direction)
 213 {
 214         unsigned long entry, flags;
 215         dma_addr_t ret = bad_dma_address;
 216
 217         spin_lock_irqsave(&tbl->it_lock, flags);
 218
 219         entry = iommu_range_alloc(tbl, npages);
 220
 221         if (unlikely(entry == bad_dma_address))
 222                 goto error;
 223
 224         /* set the return dma address */
 225         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 226
 227         /* put the TCEs in the HW table */
 228         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 229                   direction);
 230
 231         spin_unlock_irqrestore(&tbl->it_lock, flags);
 232
 233         return ret;
 234
 235 error:
 236         spin_unlock_irqrestore(&tbl->it_lock, flags);
 237         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 238                "iommu %p\n", npages, tbl);
 239         return bad_dma_address;
 240 }
 241
 242 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 243         unsigned int npages)
 244 {
 245         unsigned long entry;
 246         unsigned long i;
 247
 248         entry = dma_addr >> PAGE_SHIFT;
 249
 250         BUG_ON(entry + npages > tbl->it_size);
 251
 252         tce_free(tbl, entry, npages);
 253
 254         for (i = 0; i < npages; ++i) {
 255                 if (!test_bit(entry + i, tbl->it_map))
 256                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 257                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 258                                entry + i, tbl, dma_addr, entry, npages);
 259         }
 260
 261         __clear_bit_string(tbl->it_map, entry, npages);
 262
 263         tce_cache_blast_stress(tbl);
 264 }
 265
 266 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 267         unsigned int npages)
 268 {
 269         unsigned long flags;
 270
 271         spin_lock_irqsave(&tbl->it_lock, flags);
 272
 273         __iommu_free(tbl, dma_addr, npages);
 274
 275         spin_unlock_irqrestore(&tbl->it_lock, flags);
 276 }
 277
 278 static void __calgary_unmap_sg(struct iommu_table *tbl,
 279         struct scatterlist *sglist, int nelems, int direction)
 280 {
 281         while (nelems--) {
 282                 unsigned int npages;
 283                 dma_addr_t dma = sglist->dma_address;
 284                 unsigned int dmalen = sglist->dma_length;
 285
 286                 if (dmalen == 0)
 287                         break;
 288
 289                 npages = num_dma_pages(dma, dmalen);
 290                 __iommu_free(tbl, dma, npages);
 291                 sglist++;
 292         }
 293 }
 294
 295 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 296                       int nelems, int direction)
 297 {
 298         unsigned long flags;
 299         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 300
 301         if (!translate_phb(to_pci_dev(dev)))
 302                 return;
 303
 304         spin_lock_irqsave(&tbl->it_lock, flags);
 305
 306         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 307
 308         spin_unlock_irqrestore(&tbl->it_lock, flags);
 309 }
 310
 311 static int calgary_nontranslate_map_sg(struct device* dev,
 312         struct scatterlist *sg, int nelems, int direction)
 313 {
 314         int i;
 315
 316         for (i = 0; i < nelems; i++ ) {
 317                 struct scatterlist *s = &sg[i];
 318                 BUG_ON(!s->page);
 319                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 320                 s->dma_length = s->length;
 321         }
 322         return nelems;
 323 }
 324
 325 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 326         int nelems, int direction)
 327 {
 328         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 329         unsigned long flags;
 330         unsigned long vaddr;
 331         unsigned int npages;
 332         unsigned long entry;
 333         int i;
 334
 335         if (!translate_phb(to_pci_dev(dev)))
 336                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 337
 338         spin_lock_irqsave(&tbl->it_lock, flags);
 339
 340         for (i = 0; i < nelems; i++ ) {
 341                 struct scatterlist *s = &sg[i];
 342                 BUG_ON(!s->page);
 343
 344                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 345                 npages = num_dma_pages(vaddr, s->length);
 346
 347                 entry = iommu_range_alloc(tbl, npages);
 348                 if (entry == bad_dma_address) {
 349                         /* makes sure unmap knows to stop */
 350                         s->dma_length = 0;
 351                         goto error;
 352                 }
 353
 354                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 355
 356                 /* insert into HW table */
 357                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 358                           direction);
 359
 360                 s->dma_length = s->length;
 361         }
 362
 363         spin_unlock_irqrestore(&tbl->it_lock, flags);
 364
 365         return nelems;
 366 error:
 367         __calgary_unmap_sg(tbl, sg, nelems, direction);
 368         for (i = 0; i < nelems; i++) {
 369                 sg[i].dma_address = bad_dma_address;
 370                 sg[i].dma_length = 0;
 371         }
 372         spin_unlock_irqrestore(&tbl->it_lock, flags);
 373         return 0;
 374 }
 375
 376 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 377         size_t size, int direction)
 378 {
 379         dma_addr_t dma_handle = bad_dma_address;
 380         unsigned long uaddr;
 381         unsigned int npages;
 382         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 383
 384         uaddr = (unsigned long)vaddr;
 385         npages = num_dma_pages(uaddr, size);
 386
 387         if (translate_phb(to_pci_dev(dev)))
 388                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 389         else
 390                 dma_handle = virt_to_bus(vaddr);
 391
 392         return dma_handle;
 393 }
 394
 395 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 396         size_t size, int direction)
 397 {
 398         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 399         unsigned int npages;
 400
 401         if (!translate_phb(to_pci_dev(dev)))
 402                 return;
 403
 404         npages = num_dma_pages(dma_handle, size);
 405         iommu_free(tbl, dma_handle, npages);
 406 }
 407
 408 void* calgary_alloc_coherent(struct device *dev, size_t size,
 409         dma_addr_t *dma_handle, gfp_t flag)
 410 {
 411         void *ret = NULL;
 412         dma_addr_t mapping;
 413         unsigned int npages, order;
 414         struct iommu_table *tbl;
 415
 416         tbl = to_pci_dev(dev)->bus->self->sysdata;
 417
 418         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 419         npages = size >> PAGE_SHIFT;
 420         order = get_order(size);
 421
 422         /* alloc enough pages (and possibly more) */
 423         ret = (void *)__get_free_pages(flag, order);
 424         if (!ret)
 425                 goto error;
 426         memset(ret, 0, size);
 427
 428         if (translate_phb(to_pci_dev(dev))) {
 429                 /* set up tces to cover the allocated range */
 430                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 431                 if (mapping == bad_dma_address)
 432                         goto free;
 433
 434                 *dma_handle = mapping;
 435         } else /* non translated slot */
 436                 *dma_handle = virt_to_bus(ret);
 437
 438         return ret;
 439
 440 free:
 441         free_pages((unsigned long)ret, get_order(size));
 442         ret = NULL;
 443 error:
 444         return ret;
 445 }
 446
 447 static struct dma_mapping_ops calgary_dma_ops = {
 448         .alloc_coherent = calgary_alloc_coherent,
 449         .map_single = calgary_map_single,
 450         .unmap_single = calgary_unmap_single,
 451         .map_sg = calgary_map_sg,
 452         .unmap_sg = calgary_unmap_sg,
 453 };
 454
 455 static inline int busno_to_phbid(unsigned char num)
 456 {
 457         return bus_info[num].phbid;
 458 }
 459
 460 static inline unsigned long split_queue_offset(unsigned char num)
 461 {
 462         size_t idx = busno_to_phbid(num);
 463
 464         return split_queue_offsets[idx];
 465 }
 466
 467 static inline unsigned long tar_offset(unsigned char num)
 468 {
 469         size_t idx = busno_to_phbid(num);
 470
 471         return tar_offsets[idx];
 472 }
 473
 474 static inline unsigned long phb_offset(unsigned char num)
 475 {
 476         size_t idx = busno_to_phbid(num);
 477
 478         return phb_offsets[idx];
 479 }
 480
 481 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 482 {
 483         unsigned long target = ((unsigned long)bar) | offset;
 484         return (void __iomem*)target;
 485 }
 486
 487 static void tce_cache_blast(struct iommu_table *tbl)
 488 {
 489         u64 val;
 490         u32 aer;
 491         int i = 0;
 492         void __iomem *bbar = tbl->bbar;
 493         void __iomem *target;
 494
 495         /* disable arbitration on the bus */
 496         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 497         aer = readl(target);
 498         writel(0, target);
 499
 500         /* read plssr to ensure it got there */
 501         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 502         val = readl(target);
 503
 504         /* poll split queues until all DMA activity is done */
 505         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 506         do {
 507                 val = readq(target);
 508                 i++;
 509         } while ((val & 0xff) != 0xff && i < 100);
 510         if (i == 100)
 511                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 512                        "continuing anyway\n");
 513
 514         /* invalidate TCE cache */
 515         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 516         writeq(tbl->tar_val, target);
 517
 518         /* enable arbitration */
 519         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 520         writel(aer, target);
 521         (void)readl(target); /* flush */
 522 }
 523
 524 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 525         u64 limit)
 526 {
 527         unsigned int numpages;
 528
 529         limit = limit | 0xfffff;
 530         limit++;
 531
 532         numpages = ((limit - start) >> PAGE_SHIFT);
 533         iommu_range_reserve(dev->sysdata, start, numpages);
 534 }
 535
 536 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 537 {
 538         void __iomem *target;
 539         u64 low, high, sizelow;
 540         u64 start, limit;
 541         struct iommu_table *tbl = dev->sysdata;
 542         unsigned char busnum = dev->bus->number;
 543         void __iomem *bbar = tbl->bbar;
 544
 545         /* peripheral MEM_1 region */
 546         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 547         low = be32_to_cpu(readl(target));
 548         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 549         high = be32_to_cpu(readl(target));
 550         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 551         sizelow = be32_to_cpu(readl(target));
 552
 553         start = (high << 32) | low;
 554         limit = sizelow;
 555
 556         calgary_reserve_mem_region(dev, start, limit);
 557 }
 558
 559 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 560 {
 561         void __iomem *target;
 562         u32 val32;
 563         u64 low, high, sizelow, sizehigh;
 564         u64 start, limit;
 565         struct iommu_table *tbl = dev->sysdata;
 566         unsigned char busnum = dev->bus->number;
 567         void __iomem *bbar = tbl->bbar;
 568
 569         /* is it enabled? */
 570         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 571         val32 = be32_to_cpu(readl(target));
 572         if (!(val32 & PHB_MEM2_ENABLE))
 573                 return;
 574
 575         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 576         low = be32_to_cpu(readl(target));
 577         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 578         high = be32_to_cpu(readl(target));
 579         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 580         sizelow = be32_to_cpu(readl(target));
 581         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 582         sizehigh = be32_to_cpu(readl(target));
 583
 584         start = (high << 32) | low;
 585         limit = (sizehigh << 32) | sizelow;
 586
 587         calgary_reserve_mem_region(dev, start, limit);
 588 }
 589
 590 /*
 591  * some regions of the IO address space do not get translated, so we
 592  * must not give devices IO addresses in those regions. The regions
 593  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 594  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 595  * later.
 596  */
 597 static void __init calgary_reserve_regions(struct pci_dev *dev)
 598 {
 599         unsigned int npages;
 600         void __iomem *bbar;
 601         unsigned char busnum;
 602         u64 start;
 603         struct iommu_table *tbl = dev->sysdata;
 604
 605         bbar = tbl->bbar;
 606         busnum = dev->bus->number;
 607
 608         /* reserve bad_dma_address in case it's a legal address */
 609         iommu_range_reserve(tbl, bad_dma_address, 1);
 610
 611         /* avoid the BIOS/VGA first 640KB-1MB region */
 612         start = (640 * 1024);
 613         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 614         iommu_range_reserve(tbl, start, npages);
 615
 616         /* reserve the two PCI peripheral memory regions in IO space */
 617         calgary_reserve_peripheral_mem_1(dev);
 618         calgary_reserve_peripheral_mem_2(dev);
 619 }
 620
 621 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 622 {
 623         u64 val64;
 624         u64 table_phys;
 625         void __iomem *target;
 626         int ret;
 627         struct iommu_table *tbl;
 628
 629         /* build TCE tables for each PHB */
 630         ret = build_tce_table(dev, bbar);
 631         if (ret)
 632                 return ret;
 633
 634         tbl = dev->sysdata;
 635         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 636         tce_free(tbl, 0, tbl->it_size);
 637
 638         calgary_reserve_regions(dev);
 639
 640         /* set TARs for each PHB */
 641         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 642         val64 = be64_to_cpu(readq(target));
 643
 644         /* zero out all TAR bits under sw control */
 645         val64 &= ~TAR_SW_BITS;
 646
 647         tbl = dev->sysdata;
 648         table_phys = (u64)__pa(tbl->it_base);
 649         val64 |= table_phys;
 650
 651         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 652         val64 |= (u64) specified_table_size;
 653
 654         tbl->tar_val = cpu_to_be64(val64);
 655         writeq(tbl->tar_val, target);
 656         readq(target); /* flush */
 657
 658         return 0;
 659 }
 660
 661 static void __init calgary_free_bus(struct pci_dev *dev)
 662 {
 663         u64 val64;
 664         struct iommu_table *tbl = dev->sysdata;
 665         void __iomem *target;
 666         unsigned int bitmapsz;
 667
 668         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 669         val64 = be64_to_cpu(readq(target));
 670         val64 &= ~TAR_SW_BITS;
 671         writeq(cpu_to_be64(val64), target);
 672         readq(target); /* flush */
 673
 674         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 675         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 676         tbl->it_map = NULL;
 677
 678         kfree(tbl);
 679         dev->sysdata = NULL;
 680
 681         /* Can't free bootmem allocated memory after system is up :-( */
 682         bus_info[dev->bus->number].tce_space = NULL;
 683 }
 684
 685 static void calgary_watchdog(unsigned long data)
 686 {
 687         struct pci_dev *dev = (struct pci_dev *)data;
 688         struct iommu_table *tbl = dev->sysdata;
 689         void __iomem *bbar = tbl->bbar;
 690         u32 val32;
 691         void __iomem *target;
 692
 693         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 694         val32 = be32_to_cpu(readl(target));
 695
 696         /* If no error, the agent ID in the CSR is not valid */
 697         if (val32 & CSR_AGENT_MASK) {
 698                 printk(KERN_EMERG "calgary_watchdog: DMA error on bus %d, "
 699                                   "CSR = %#x\n", dev->bus->number, val32);
 700                 writel(0, target);
 701
 702                 /* Disable bus that caused the error */
 703                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 704                                            PHB_CONFIG_RW_OFFSET);
 705                 val32 = be32_to_cpu(readl(target));
 706                 val32 |= PHB_SLOT_DISABLE;
 707                 writel(cpu_to_be32(val32), target);
 708                 readl(target); /* flush */
 709         } else {
 710                 /* Reset the timer */
 711                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 712         }
 713 }
 714
 715 static void __init calgary_enable_translation(struct pci_dev *dev)
 716 {
 717         u32 val32;
 718         unsigned char busnum;
 719         void __iomem *target;
 720         void __iomem *bbar;
 721         struct iommu_table *tbl;
 722
 723         busnum = dev->bus->number;
 724         tbl = dev->sysdata;
 725         bbar = tbl->bbar;
 726
 727         /* enable TCE in PHB Config Register */
 728         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 729         val32 = be32_to_cpu(readl(target));
 730         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 731
 732         printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
 733         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 734                "bus.\n");
 735
 736         writel(cpu_to_be32(val32), target);
 737         readl(target); /* flush */
 738
 739         init_timer(&tbl->watchdog_timer);
 740         tbl->watchdog_timer.function = &calgary_watchdog;
 741         tbl->watchdog_timer.data = (unsigned long)dev;
 742         mod_timer(&tbl->watchdog_timer, jiffies);
 743 }
 744
 745 static void __init calgary_disable_translation(struct pci_dev *dev)
 746 {
 747         u32 val32;
 748         unsigned char busnum;
 749         void __iomem *target;
 750         void __iomem *bbar;
 751         struct iommu_table *tbl;
 752
 753         busnum = dev->bus->number;
 754         tbl = dev->sysdata;
 755         bbar = tbl->bbar;
 756
 757         /* disable TCE in PHB Config Register */
 758         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 759         val32 = be32_to_cpu(readl(target));
 760         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 761
 762         printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
 763         writel(cpu_to_be32(val32), target);
 764         readl(target); /* flush */
 765
 766         del_timer_sync(&tbl->watchdog_timer);
 767 }
 768
 769 static inline unsigned int __init locate_register_space(struct pci_dev *dev)
 770 {
 771         int rionodeid;
 772         u32 address;
 773
 774         rionodeid = (dev->bus->number % 15 > 4) ? 3 : 2;
 775         /*
 776          * register space address calculation as follows:
 777          * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
 778          * ChassisBase is always zero for x366/x260/x460
 779          * RioNodeId is 2 for first Calgary, 3 for second Calgary
 780          */
 781         address = START_ADDRESS -
 782                 (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 15)) +
 783                 (0x100000) * (rionodeid - CHASSIS_BASE);
 784         return address;
 785 }
 786
 787 static int __init calgary_init_one_nontraslated(struct pci_dev *dev)
 788 {
 789         pci_dev_get(dev);
 790         dev->sysdata = NULL;
 791         dev->bus->self = dev;
 792
 793         return 0;
 794 }
 795
 796 static int __init calgary_init_one(struct pci_dev *dev)
 797 {
 798         u32 address;
 799         void __iomem *bbar;
 800         int ret;
 801
 802         address = locate_register_space(dev);
 803         /* map entire 1MB of Calgary config space */
 804         bbar = ioremap_nocache(address, 1024 * 1024);
 805         if (!bbar) {
 806                 ret = -ENODATA;
 807                 goto done;
 808         }
 809
 810         ret = calgary_setup_tar(dev, bbar);
 811         if (ret)
 812                 goto iounmap;
 813
 814         pci_dev_get(dev);
 815         dev->bus->self = dev;
 816         calgary_enable_translation(dev);
 817
 818         return 0;
 819
 820 iounmap:
 821         iounmap(bbar);
 822 done:
 823         return ret;
 824 }
 825
 826 static int __init calgary_init(void)
 827 {
 828         int i, ret = -ENODEV;
 829         struct pci_dev *dev = NULL;
 830
 831         for (i = 0; i < MAX_PHB_BUS_NUM; i++) {
 832                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 833                                      PCI_DEVICE_ID_IBM_CALGARY,
 834                                      dev);
 835                 if (!dev)
 836                         break;
 837                 if (!translate_phb(dev)) {
 838                         calgary_init_one_nontraslated(dev);
 839                         continue;
 840                 }
 841                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 842                         continue;
 843
 844                 ret = calgary_init_one(dev);
 845                 if (ret)
 846                         goto error;
 847         }
 848
 849         return ret;
 850
 851 error:
 852         for (i--; i >= 0; i--) {
 853                 dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
 854                                               PCI_DEVICE_ID_IBM_CALGARY,
 855                                               dev);
 856                 if (!dev)
 857                         break;
 858                 if (!translate_phb(dev)) {
 859                         pci_dev_put(dev);
 860                         continue;
 861                 }
 862                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 863                         continue;
 864
 865                 calgary_disable_translation(dev);
 866                 calgary_free_bus(dev);
 867                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
 868         }
 869
 870         return ret;
 871 }
 872
 873 static inline int __init determine_tce_table_size(u64 ram)
 874 {
 875         int ret;
 876
 877         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 878                 return specified_table_size;
 879
 880         /*
 881          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
 882          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
 883          * larger table size has twice as many entries, so shift the
 884          * max ram address by 13 to divide by 8K and then look at the
 885          * order of the result to choose between 0-7.
 886          */
 887         ret = get_order(ram >> 13);
 888         if (ret > TCE_TABLE_SIZE_8M)
 889                 ret = TCE_TABLE_SIZE_8M;
 890
 891         return ret;
 892 }
 893
 894 void __init detect_calgary(void)
 895 {
 896         u32 val;
 897         int bus;
 898         void *tbl;
 899         int calgary_found = 0;
 900         int phb = -1;
 901
 902         /*
 903          * if the user specified iommu=off or iommu=soft or we found
 904          * another HW IOMMU already, bail out.
 905          */
 906         if (swiotlb || no_iommu || iommu_detected)
 907                 return;
 908
 909         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
 910
 911         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
 912                 int dev;
 913                 struct calgary_bus_info *info = &bus_info[bus];
 914                 info->phbid = -1;
 915
 916                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
 917                         continue;
 918
 919                 /*
 920                  * There are 4 PHBs per Calgary chip.  Set phb to which phb (0-3)
 921                  * it is connected to releative to the clagary chip.
 922                  */
 923                 phb = (phb + 1) % PHBS_PER_CALGARY;
 924
 925                 if (info->translation_disabled)
 926                         continue;
 927
 928                 /*
 929                  * Scan the slots of the PCI bus to see if there is a device present.
 930                  * The parent bus will be the zero-ith device, so start at 1.
 931                  */
 932                 for (dev = 1; dev < 8; dev++) {
 933                         val = read_pci_config(bus, dev, 0, 0);
 934                         if (val != 0xffffffff || translate_empty_slots) {
 935                                 tbl = alloc_tce_table();
 936                                 if (!tbl)
 937                                         goto cleanup;
 938                                 info->tce_space = tbl;
 939                                 info->phbid = phb;
 940                                 calgary_found = 1;
 941                                 break;
 942                         }
 943                 }
 944         }
 945
 946         if (calgary_found) {
 947                 iommu_detected = 1;
 948                 calgary_detected = 1;
 949                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. "
 950                        "TCE table spec is %d.\n", specified_table_size);
 951         }
 952         return;
 953
 954 cleanup:
 955         for (--bus; bus >= 0; --bus) {
 956                 struct calgary_bus_info *info = &bus_info[bus];
 957
 958                 if (info->tce_space)
 959                         free_tce_table(info->tce_space);
 960         }
 961 }
 962
 963 int __init calgary_iommu_init(void)
 964 {
 965         int ret;
 966
 967         if (no_iommu || swiotlb)
 968                 return -ENODEV;
 969
 970         if (!calgary_detected)
 971                 return -ENODEV;
 972
 973         /* ok, we're trying to use Calgary - let's roll */
 974         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
 975
 976         ret = calgary_init();
 977         if (ret) {
 978                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
 979                        "falling back to no_iommu\n", ret);
 980                 if (end_pfn > MAX_DMA32_PFN)
 981                         printk(KERN_ERR "WARNING more than 4GB of memory, "
 982                                         "32bit PCI may malfunction.\n");
 983                 return ret;
 984         }
 985
 986         force_iommu = 1;
 987         dma_ops = &calgary_dma_ops;
 988
 989         return 0;
 990 }
 991
 992 static int __init calgary_parse_options(char *p)
 993 {
 994         unsigned int bridge;
 995         size_t len;
 996         char* endp;
 997
 998         while (*p) {
 999                 if (!strncmp(p, "64k", 3))
1000                         specified_table_size = TCE_TABLE_SIZE_64K;
1001                 else if (!strncmp(p, "128k", 4))
1002                         specified_table_size = TCE_TABLE_SIZE_128K;
1003                 else if (!strncmp(p, "256k", 4))
1004                         specified_table_size = TCE_TABLE_SIZE_256K;
1005                 else if (!strncmp(p, "512k", 4))
1006                         specified_table_size = TCE_TABLE_SIZE_512K;
1007                 else if (!strncmp(p, "1M", 2))
1008                         specified_table_size = TCE_TABLE_SIZE_1M;
1009                 else if (!strncmp(p, "2M", 2))
1010                         specified_table_size = TCE_TABLE_SIZE_2M;
1011                 else if (!strncmp(p, "4M", 2))
1012                         specified_table_size = TCE_TABLE_SIZE_4M;
1013                 else if (!strncmp(p, "8M", 2))
1014                         specified_table_size = TCE_TABLE_SIZE_8M;
1015
1016                 len = strlen("translate_empty_slots");
1017                 if (!strncmp(p, "translate_empty_slots", len))
1018                         translate_empty_slots = 1;
1019
1020                 len = strlen("disable");
1021                 if (!strncmp(p, "disable", len)) {
1022                         p += len;
1023                         if (*p == '=')
1024                                 ++p;
1025                         if (*p == '\0')
1026                                 break;
1027                         bridge = simple_strtol(p, &endp, 0);
1028                         if (p == endp)
1029                                 break;
1030
1031                         if (bridge < MAX_PHB_BUS_NUM) {
1032                                 printk(KERN_INFO "Calgary: disabling "
1033                                        "translation for PHB 0x%x\n", bridge);
1034                                 bus_info[bridge].translation_disabled = 1;
1035                         }
1036                 }
1037
1038                 p = strpbrk(p, ",");
1039                 if (!p)
1040                         break;
1041
1042                 p++; /* skip ',' */
1043         }
1044         return 1;
1045 }
1046 __setup("calgary=", calgary_parse_options);