2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $
35 #include <linux/slab.h>
36 #include <linux/string.h>
37 #include <linux/sched.h>
41 #include "mthca_dev.h"
42 #include "mthca_cmd.h"
43 #include "mthca_memfree.h"
44 #include "mthca_wqe.h"
47 MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE
50 struct mthca_tavor_srq_context {
51 __be64 wqe_base_ds; /* low 6 bits is descriptor size */
55 __be16 limit_watermark;
60 struct mthca_arbel_srq_context {
61 __be32 state_logsize_srqn;
64 __be32 logstride_usrpage;
67 __be16 limit_watermark;
74 static void *get_wqe(struct mthca_srq *srq, int n)
77 return srq->queue.direct.buf + (n << srq->wqe_shift);
79 return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf +
80 ((n << srq->wqe_shift) & (PAGE_SIZE - 1));
84 * Return a pointer to the location within a WQE that we're using as a
85 * link when the WQE is in the free list. We use the imm field
86 * because in the Tavor case, posting a WQE may overwrite the next
87 * segment of the previous WQE, but a receive WQE will never touch the
88 * imm field. This avoids corrupting our free list if the previous
89 * WQE has already completed and been put on the free list when we
92 static inline int *wqe_to_link(void *wqe)
94 return (int *) (wqe + offsetof(struct mthca_next_seg, imm));
97 static void mthca_tavor_init_srq_context(struct mthca_dev *dev,
99 struct mthca_srq *srq,
100 struct mthca_tavor_srq_context *context)
102 memset(context, 0, sizeof *context);
104 context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4));
105 context->state_pd = cpu_to_be32(pd->pd_num);
106 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
108 if (pd->ibpd.uobject)
110 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
112 context->uar = cpu_to_be32(dev->driver_uar.index);
115 static void mthca_arbel_init_srq_context(struct mthca_dev *dev,
117 struct mthca_srq *srq,
118 struct mthca_arbel_srq_context *context)
122 memset(context, 0, sizeof *context);
125 * Put max in a temporary variable to work around gcc bug
126 * triggered by ilog2() on sparc64.
129 logsize = ilog2(max);
130 context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn);
131 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
132 context->db_index = cpu_to_be32(srq->db_index);
133 context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29);
134 if (pd->ibpd.uobject)
135 context->logstride_usrpage |=
136 cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
138 context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index);
139 context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num);
142 static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq)
144 mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue,
145 srq->is_direct, &srq->mr);
149 static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd,
150 struct mthca_srq *srq)
152 struct mthca_data_seg *scatter;
157 if (pd->ibpd.uobject)
160 srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL);
164 err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift,
165 MTHCA_MAX_DIRECT_SRQ_SIZE,
166 &srq->queue, &srq->is_direct, pd, 1, &srq->mr);
173 * Now initialize the SRQ buffer so that all of the WQEs are
174 * linked into the list of free WQEs. In addition, set the
175 * scatter list L_Keys to the sentry value of 0x100.
177 for (i = 0; i < srq->max; ++i) {
178 struct mthca_next_seg *next;
180 next = wqe = get_wqe(srq, i);
182 if (i < srq->max - 1) {
183 *wqe_to_link(wqe) = i + 1;
184 next->nda_op = htonl(((i + 1) << srq->wqe_shift) | 1);
186 *wqe_to_link(wqe) = -1;
190 for (scatter = wqe + sizeof (struct mthca_next_seg);
191 (void *) scatter < wqe + (1 << srq->wqe_shift);
193 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
196 srq->last = get_wqe(srq, srq->max - 1);
201 int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
202 struct ib_srq_attr *attr, struct mthca_srq *srq)
204 struct mthca_mailbox *mailbox;
209 /* Sanity check SRQ size before proceeding */
210 if (attr->max_wr > dev->limits.max_srq_wqes ||
211 attr->max_sge > dev->limits.max_srq_sge)
214 srq->max = attr->max_wr;
215 srq->max_gs = attr->max_sge;
218 if (mthca_is_memfree(dev))
219 srq->max = roundup_pow_of_two(srq->max + 1);
221 srq->max = srq->max + 1;
224 roundup_pow_of_two(sizeof (struct mthca_next_seg) +
225 srq->max_gs * sizeof (struct mthca_data_seg)));
227 if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz))
230 srq->wqe_shift = ilog2(ds);
232 srq->srqn = mthca_alloc(&dev->srq_table.alloc);
236 if (mthca_is_memfree(dev)) {
237 err = mthca_table_get(dev, dev->srq_table.table, srq->srqn);
241 if (!pd->ibpd.uobject) {
242 srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ,
243 srq->srqn, &srq->db);
244 if (srq->db_index < 0) {
251 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
252 if (IS_ERR(mailbox)) {
253 err = PTR_ERR(mailbox);
257 err = mthca_alloc_srq_buf(dev, pd, srq);
259 goto err_out_mailbox;
261 spin_lock_init(&srq->lock);
263 init_waitqueue_head(&srq->wait);
264 mutex_init(&srq->mutex);
266 if (mthca_is_memfree(dev))
267 mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf);
269 mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf);
271 err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status);
274 mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err);
275 goto err_out_free_buf;
278 mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n",
281 goto err_out_free_buf;
284 spin_lock_irq(&dev->srq_table.lock);
285 if (mthca_array_set(&dev->srq_table.srq,
286 srq->srqn & (dev->limits.num_srqs - 1),
288 spin_unlock_irq(&dev->srq_table.lock);
289 goto err_out_free_srq;
291 spin_unlock_irq(&dev->srq_table.lock);
293 mthca_free_mailbox(dev, mailbox);
296 srq->last_free = srq->max - 1;
298 attr->max_wr = srq->max - 1;
299 attr->max_sge = srq->max_gs;
304 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
306 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
308 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
311 if (!pd->ibpd.uobject)
312 mthca_free_srq_buf(dev, srq);
315 mthca_free_mailbox(dev, mailbox);
318 if (!pd->ibpd.uobject && mthca_is_memfree(dev))
319 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
322 mthca_table_put(dev, dev->srq_table.table, srq->srqn);
325 mthca_free(&dev->srq_table.alloc, srq->srqn);
330 static inline int get_srq_refcount(struct mthca_dev *dev, struct mthca_srq *srq)
334 spin_lock_irq(&dev->srq_table.lock);
336 spin_unlock_irq(&dev->srq_table.lock);
341 void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq)
343 struct mthca_mailbox *mailbox;
347 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
348 if (IS_ERR(mailbox)) {
349 mthca_warn(dev, "No memory for mailbox to free SRQ.\n");
353 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
355 mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
357 mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
359 spin_lock_irq(&dev->srq_table.lock);
360 mthca_array_clear(&dev->srq_table.srq,
361 srq->srqn & (dev->limits.num_srqs - 1));
363 spin_unlock_irq(&dev->srq_table.lock);
365 wait_event(srq->wait, !get_srq_refcount(dev, srq));
367 if (!srq->ibsrq.uobject) {
368 mthca_free_srq_buf(dev, srq);
369 if (mthca_is_memfree(dev))
370 mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
373 mthca_table_put(dev, dev->srq_table.table, srq->srqn);
374 mthca_free(&dev->srq_table.alloc, srq->srqn);
375 mthca_free_mailbox(dev, mailbox);
378 int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
379 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
381 struct mthca_dev *dev = to_mdev(ibsrq->device);
382 struct mthca_srq *srq = to_msrq(ibsrq);
386 /* We don't support resizing SRQs (yet?) */
387 if (attr_mask & IB_SRQ_MAX_WR)
390 if (attr_mask & IB_SRQ_LIMIT) {
391 u32 max_wr = mthca_is_memfree(dev) ? srq->max - 1 : srq->max;
392 if (attr->srq_limit > max_wr)
395 mutex_lock(&srq->mutex);
396 ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status);
397 mutex_unlock(&srq->mutex);
408 int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
410 struct mthca_dev *dev = to_mdev(ibsrq->device);
411 struct mthca_srq *srq = to_msrq(ibsrq);
412 struct mthca_mailbox *mailbox;
413 struct mthca_arbel_srq_context *arbel_ctx;
414 struct mthca_tavor_srq_context *tavor_ctx;
418 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
420 return PTR_ERR(mailbox);
422 err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status);
426 if (mthca_is_memfree(dev)) {
427 arbel_ctx = mailbox->buf;
428 srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark);
430 tavor_ctx = mailbox->buf;
431 srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark);
434 srq_attr->max_wr = srq->max - 1;
435 srq_attr->max_sge = srq->max_gs;
438 mthca_free_mailbox(dev, mailbox);
443 void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
444 enum ib_event_type event_type)
446 struct mthca_srq *srq;
447 struct ib_event event;
449 spin_lock(&dev->srq_table.lock);
450 srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1));
453 spin_unlock(&dev->srq_table.lock);
456 mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
460 if (!srq->ibsrq.event_handler)
463 event.device = &dev->ib_dev;
464 event.event = event_type;
465 event.element.srq = &srq->ibsrq;
466 srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context);
469 spin_lock(&dev->srq_table.lock);
470 if (!--srq->refcount)
472 spin_unlock(&dev->srq_table.lock);
476 * This function must be called with IRQs disabled.
478 void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr)
481 struct mthca_next_seg *last_free;
483 ind = wqe_addr >> srq->wqe_shift;
485 spin_lock(&srq->lock);
487 last_free = get_wqe(srq, srq->last_free);
488 *wqe_to_link(last_free) = ind;
489 last_free->nda_op = htonl((ind << srq->wqe_shift) | 1);
490 *wqe_to_link(get_wqe(srq, ind)) = -1;
491 srq->last_free = ind;
493 spin_unlock(&srq->lock);
496 int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
497 struct ib_recv_wr **bad_wr)
499 struct mthca_dev *dev = to_mdev(ibsrq->device);
500 struct mthca_srq *srq = to_msrq(ibsrq);
511 spin_lock_irqsave(&srq->lock, flags);
513 first_ind = srq->first_free;
515 for (nreq = 0; wr; wr = wr->next) {
516 ind = srq->first_free;
517 wqe = get_wqe(srq, ind);
518 next_ind = *wqe_to_link(wqe);
520 if (unlikely(next_ind < 0)) {
521 mthca_err(dev, "SRQ %06x full\n", srq->srqn);
527 prev_wqe = srq->last;
530 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
531 /* flags field will always remain 0 */
533 wqe += sizeof (struct mthca_next_seg);
535 if (unlikely(wr->num_sge > srq->max_gs)) {
538 srq->last = prev_wqe;
542 for (i = 0; i < wr->num_sge; ++i) {
543 mthca_set_data_seg(wqe, wr->sg_list + i);
544 wqe += sizeof (struct mthca_data_seg);
548 mthca_set_data_seg_inval(wqe);
550 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
551 cpu_to_be32(MTHCA_NEXT_DBD);
553 srq->wrid[ind] = wr->wr_id;
554 srq->first_free = next_ind;
557 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
561 * Make sure that descriptors are written
562 * before doorbell is rung.
566 mthca_write64(first_ind << srq->wqe_shift, srq->srqn << 8,
567 dev->kar + MTHCA_RECEIVE_DOORBELL,
568 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
570 first_ind = srq->first_free;
576 * Make sure that descriptors are written before
581 mthca_write64(first_ind << srq->wqe_shift, (srq->srqn << 8) | nreq,
582 dev->kar + MTHCA_RECEIVE_DOORBELL,
583 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
587 * Make sure doorbells don't leak out of SRQ spinlock and
588 * reach the HCA out of order:
592 spin_unlock_irqrestore(&srq->lock, flags);
596 int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
597 struct ib_recv_wr **bad_wr)
599 struct mthca_dev *dev = to_mdev(ibsrq->device);
600 struct mthca_srq *srq = to_msrq(ibsrq);
609 spin_lock_irqsave(&srq->lock, flags);
611 for (nreq = 0; wr; ++nreq, wr = wr->next) {
612 ind = srq->first_free;
613 wqe = get_wqe(srq, ind);
614 next_ind = *wqe_to_link(wqe);
616 if (unlikely(next_ind < 0)) {
617 mthca_err(dev, "SRQ %06x full\n", srq->srqn);
623 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
624 /* flags field will always remain 0 */
626 wqe += sizeof (struct mthca_next_seg);
628 if (unlikely(wr->num_sge > srq->max_gs)) {
634 for (i = 0; i < wr->num_sge; ++i) {
635 mthca_set_data_seg(wqe, wr->sg_list + i);
636 wqe += sizeof (struct mthca_data_seg);
640 mthca_set_data_seg_inval(wqe);
642 srq->wrid[ind] = wr->wr_id;
643 srq->first_free = next_ind;
647 srq->counter += nreq;
650 * Make sure that descriptors are written before
651 * we write doorbell record.
654 *srq->db = cpu_to_be32(srq->counter);
657 spin_unlock_irqrestore(&srq->lock, flags);
661 int mthca_max_srq_sge(struct mthca_dev *dev)
663 if (mthca_is_memfree(dev))
664 return dev->limits.max_sg;
667 * SRQ allocations are based on powers of 2 for Tavor,
668 * (although they only need to be multiples of 16 bytes).
670 * Therefore, we need to base the max number of sg entries on
671 * the largest power of 2 descriptor size that is <= to the
672 * actual max WQE descriptor size, rather than return the
673 * max_sg value given by the firmware (which is based on WQE
674 * sizes as multiples of 16, not powers of 2).
676 * If SRQ implementation is changed for Tavor to be based on
677 * multiples of 16, the calculation below can be deleted and
678 * the FW max_sg value returned.
680 return min_t(int, dev->limits.max_sg,
681 ((1 << (fls(dev->limits.max_desc_sz) - 1)) -
682 sizeof (struct mthca_next_seg)) /
683 sizeof (struct mthca_data_seg));
686 int mthca_init_srq_table(struct mthca_dev *dev)
690 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
693 spin_lock_init(&dev->srq_table.lock);
695 err = mthca_alloc_init(&dev->srq_table.alloc,
696 dev->limits.num_srqs,
697 dev->limits.num_srqs - 1,
698 dev->limits.reserved_srqs);
702 err = mthca_array_init(&dev->srq_table.srq,
703 dev->limits.num_srqs);
705 mthca_alloc_cleanup(&dev->srq_table.alloc);
710 void mthca_cleanup_srq_table(struct mthca_dev *dev)
712 if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
715 mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs);
716 mthca_alloc_cleanup(&dev->srq_table.alloc);