Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6] / arch / arm / mach-pxa / corgi_lcd.c
1 /*
2  * linux/arch/arm/mach-pxa/corgi_lcd.c
3  *
4  * Corgi/Spitz LCD Specific Code
5  *
6  * Copyright (C) 2005 Richard Purdie
7  *
8  * Connectivity:
9  *   Corgi - LCD to ATI Imageon w100 (Wallaby)
10  *   Spitz - LCD to PXA Framebuffer
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  */
17
18 #include <linux/delay.h>
19 #include <linux/kernel.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/string.h>
23 #include <mach/corgi.h>
24 #include <mach/hardware.h>
25 #include <mach/sharpsl.h>
26 #include <mach/spitz.h>
27 #include <asm/hardware/scoop.h>
28 #include <asm/mach/sharpsl_param.h>
29 #include "generic.h"
30
31 /* Register Addresses */
32 #define RESCTL_ADRS     0x00
33 #define PHACTRL_ADRS    0x01
34 #define DUTYCTRL_ADRS   0x02
35 #define POWERREG0_ADRS  0x03
36 #define POWERREG1_ADRS  0x04
37 #define GPOR3_ADRS      0x05
38 #define PICTRL_ADRS     0x06
39 #define POLCTRL_ADRS    0x07
40
41 /* Register Bit Definitions */
42 #define RESCTL_QVGA     0x01
43 #define RESCTL_VGA      0x00
44
45 #define POWER1_VW_ON    0x01  /* VW Supply FET ON */
46 #define POWER1_GVSS_ON  0x02  /* GVSS(-8V) Power Supply ON */
47 #define POWER1_VDD_ON   0x04  /* VDD(8V),SVSS(-4V) Power Supply ON */
48
49 #define POWER1_VW_OFF   0x00  /* VW Supply FET OFF */
50 #define POWER1_GVSS_OFF 0x00  /* GVSS(-8V) Power Supply OFF */
51 #define POWER1_VDD_OFF  0x00  /* VDD(8V),SVSS(-4V) Power Supply OFF */
52
53 #define POWER0_COM_DCLK 0x01  /* COM Voltage DC Bias DAC Serial Data Clock */
54 #define POWER0_COM_DOUT 0x02  /* COM Voltage DC Bias DAC Serial Data Out */
55 #define POWER0_DAC_ON   0x04  /* DAC Power Supply ON */
56 #define POWER0_COM_ON   0x08  /* COM Power Supply ON */
57 #define POWER0_VCC5_ON  0x10  /* VCC5 Power Supply ON */
58
59 #define POWER0_DAC_OFF  0x00  /* DAC Power Supply OFF */
60 #define POWER0_COM_OFF  0x00  /* COM Power Supply OFF */
61 #define POWER0_VCC5_OFF 0x00  /* VCC5 Power Supply OFF */
62
63 #define PICTRL_INIT_STATE      0x01
64 #define PICTRL_INIOFF          0x02
65 #define PICTRL_POWER_DOWN      0x04
66 #define PICTRL_COM_SIGNAL_OFF  0x08
67 #define PICTRL_DAC_SIGNAL_OFF  0x10
68
69 #define POLCTRL_SYNC_POL_FALL  0x01
70 #define POLCTRL_EN_POL_FALL    0x02
71 #define POLCTRL_DATA_POL_FALL  0x04
72 #define POLCTRL_SYNC_ACT_H     0x08
73 #define POLCTRL_EN_ACT_L       0x10
74
75 #define POLCTRL_SYNC_POL_RISE  0x00
76 #define POLCTRL_EN_POL_RISE    0x00
77 #define POLCTRL_DATA_POL_RISE  0x00
78 #define POLCTRL_SYNC_ACT_L     0x00
79 #define POLCTRL_EN_ACT_H       0x00
80
81 #define PHACTRL_PHASE_MANUAL   0x01
82 #define DEFAULT_PHAD_QVGA     (9)
83 #define DEFAULT_COMADJ        (125)
84
85 /*
86  * This is only a psuedo I2C interface. We can't use the standard kernel
87  * routines as the interface is write only. We just assume the data is acked...
88  */
89 static void lcdtg_ssp_i2c_send(u8 data)
90 {
91         corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
92         udelay(10);
93 }
94
95 static void lcdtg_i2c_send_bit(u8 data)
96 {
97         lcdtg_ssp_i2c_send(data);
98         lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
99         lcdtg_ssp_i2c_send(data);
100 }
101
102 static void lcdtg_i2c_send_start(u8 base)
103 {
104         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
105         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
106         lcdtg_ssp_i2c_send(base);
107 }
108
109 static void lcdtg_i2c_send_stop(u8 base)
110 {
111         lcdtg_ssp_i2c_send(base);
112         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
113         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
114 }
115
116 static void lcdtg_i2c_send_byte(u8 base, u8 data)
117 {
118         int i;
119         for (i = 0; i < 8; i++) {
120                 if (data & 0x80)
121                         lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
122                 else
123                         lcdtg_i2c_send_bit(base);
124                 data <<= 1;
125         }
126 }
127
128 static void lcdtg_i2c_wait_ack(u8 base)
129 {
130         lcdtg_i2c_send_bit(base);
131 }
132
133 static void lcdtg_set_common_voltage(u8 base_data, u8 data)
134 {
135         /* Set Common Voltage to M62332FP via I2C */
136         lcdtg_i2c_send_start(base_data);
137         lcdtg_i2c_send_byte(base_data, 0x9c);
138         lcdtg_i2c_wait_ack(base_data);
139         lcdtg_i2c_send_byte(base_data, 0x00);
140         lcdtg_i2c_wait_ack(base_data);
141         lcdtg_i2c_send_byte(base_data, data);
142         lcdtg_i2c_wait_ack(base_data);
143         lcdtg_i2c_send_stop(base_data);
144 }
145
146 /* Set Phase Adjust */
147 static void lcdtg_set_phadadj(int mode)
148 {
149         int adj;
150         switch(mode) {
151                 case 480:
152                 case 640:
153                         /* Setting for VGA */
154                         adj = sharpsl_param.phadadj;
155                         if (adj < 0) {
156                                 adj = PHACTRL_PHASE_MANUAL;
157                         } else {
158                                 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
159                         }
160                         break;
161                 case 240:
162                 case 320:
163                 default:
164                         /* Setting for QVGA */
165                         adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
166                         break;
167         }
168
169         corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
170 }
171
172 static int lcd_inited;
173
174 void corgi_lcdtg_hw_init(int mode)
175 {
176         if (!lcd_inited) {
177                 int comadj;
178
179                 /* Initialize Internal Logic & Port */
180                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
181                                 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
182
183                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
184                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
185
186                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
187
188                 /* VDD(+8V), SVSS(-4V) ON */
189                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
190                 mdelay(3);
191
192                 /* DAC ON */
193                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
194                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
195
196                 /* INIB = H, INI = L  */
197                 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
198                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
199
200                 /* Set Common Voltage */
201                 comadj = sharpsl_param.comadj;
202                 if (comadj < 0)
203                         comadj = DEFAULT_COMADJ;
204                 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
205
206                 /* VCC5 ON, DAC ON */
207                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
208                                 POWER0_COM_OFF | POWER0_VCC5_ON);
209
210                 /* GVSS(-8V) ON, VDD ON */
211                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
212                 mdelay(2);
213
214                 /* COM SIGNAL ON (PICTL[3] = L) */
215                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
216
217                 /* COM ON, DAC ON, VCC5_ON */
218                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
219                                 | POWER0_COM_ON | POWER0_VCC5_ON);
220
221                 /* VW ON, GVSS ON, VDD ON */
222                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
223
224                 /* Signals output enable */
225                 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
226
227                 /* Set Phase Adjust */
228                 lcdtg_set_phadadj(mode);
229
230                 /* Initialize for Input Signals from ATI */
231                 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
232                                 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
233                 udelay(1000);
234
235                 lcd_inited=1;
236         } else {
237                 lcdtg_set_phadadj(mode);
238         }
239
240         switch(mode) {
241                 case 480:
242                 case 640:
243                         /* Set Lcd Resolution (VGA) */
244                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
245                         break;
246                 case 240:
247                 case 320:
248                 default:
249                         /* Set Lcd Resolution (QVGA) */
250                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
251                         break;
252         }
253 }
254
255 void corgi_lcdtg_suspend(void)
256 {
257         /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
258         mdelay(34);
259
260         /* (1)VW OFF */
261         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
262
263         /* (2)COM OFF */
264         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
265         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
266
267         /* (3)Set Common Voltage Bias 0V */
268         lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
269
270         /* (4)GVSS OFF */
271         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
272
273         /* (5)VCC5 OFF */
274         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
275
276         /* (6)Set PDWN, INIOFF, DACOFF */
277         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
278                         PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
279
280         /* (7)DAC OFF */
281         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
282
283         /* (8)VDD OFF */
284         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
285
286         lcd_inited = 0;
287 }
288