git.oblomov.eu Git - linux-2.6/blob - sound/pci/cmipci.c

   1 /*
   2  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   3  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program; if not, write to the Free Software
  17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 /* Does not work. Warning may block system in capture mode */
  21 /* #define USE_VAR48KRATE */
  22
  23 #include <sound/driver.h>
  24 #include <asm/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/init.h>
  28 #include <linux/pci.h>
  29 #include <linux/slab.h>
  30 #include <linux/gameport.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/mutex.h>
  33 #include <sound/core.h>
  34 #include <sound/info.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/rawmidi.h>
  38 #include <sound/mpu401.h>
  39 #include <sound/opl3.h>
  40 #include <sound/sb.h>
  41 #include <sound/asoundef.h>
  42 #include <sound/initval.h>
  43
  44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  46 MODULE_LICENSE("GPL");
  47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  48                 "{C-Media,CMI8738B},"
  49                 "{C-Media,CMI8338A},"
  50                 "{C-Media,CMI8338B}}");
  51
  52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  53 #define SUPPORT_JOYSTICK 1
  54 #endif
  55
  56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  59 static long mpu_port[SNDRV_CARDS];
  60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  62 #ifdef SUPPORT_JOYSTICK
  63 static int joystick_port[SNDRV_CARDS];
  64 #endif
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  68 module_param_array(id, charp, NULL, 0444);
  69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  70 module_param_array(enable, bool, NULL, 0444);
  71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  72 module_param_array(mpu_port, long, NULL, 0444);
  73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  74 module_param_array(fm_port, long, NULL, 0444);
  75 MODULE_PARM_DESC(fm_port, "FM port.");
  76 module_param_array(soft_ac3, bool, NULL, 0444);
  77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
  78 #ifdef SUPPORT_JOYSTICK
  79 module_param_array(joystick_port, int, NULL, 0444);
  80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  81 #endif
  82
  83 /*
  84  * CM8x38 registers definition
  85  */
  86
  87 #define CM_REG_FUNCTRL0         0x00
  88 #define CM_RST_CH1              0x00080000
  89 #define CM_RST_CH0              0x00040000
  90 #define CM_CHEN1                0x00020000      /* ch1: enable */
  91 #define CM_CHEN0                0x00010000      /* ch0: enable */
  92 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  93 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  94 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  95 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  96
  97 #define CM_REG_FUNCTRL1         0x04
  98 #define CM_ASFC_MASK            0x0000E000      /* ADC sampling frequency */
  99 #define CM_ASFC_SHIFT           13
 100 #define CM_DSFC_MASK            0x00001C00      /* DAC sampling frequency */
 101 #define CM_DSFC_SHIFT           10
 102 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
 103 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
 104 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/OUT -> IN loopback */
 105 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
 106 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
 107 #define CM_BREQ                 0x00000010      /* bus master enabled */
 108 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
 109 #define CM_UART_EN              0x00000004      /* UART */
 110 #define CM_JYSTK_EN             0x00000002      /* joy stick */
 111
 112 #define CM_REG_CHFORMAT         0x08
 113
 114 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 115 #define CM_CHB3D                0x20000000      /* 4 channels */
 116
 117 #define CM_CHIP_MASK1           0x1f000000
 118 #define CM_CHIP_037             0x01000000
 119
 120 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 121 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 122 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 123 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 124
 125 #define CM_ADCBITLEN_MASK       0x0000C000
 126 #define CM_ADCBITLEN_16         0x00000000
 127 #define CM_ADCBITLEN_15         0x00004000
 128 #define CM_ADCBITLEN_14         0x00008000
 129 #define CM_ADCBITLEN_13         0x0000C000
 130
 131 #define CM_ADCDACLEN_MASK       0x00003000
 132 #define CM_ADCDACLEN_060        0x00000000
 133 #define CM_ADCDACLEN_066        0x00001000
 134 #define CM_ADCDACLEN_130        0x00002000
 135 #define CM_ADCDACLEN_280        0x00003000
 136
 137 #define CM_CH1_SRATE_176K       0x00000800
 138 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 139 #define CM_CH1_SRATE_88K        0x00000400
 140 #define CM_CH0_SRATE_176K       0x00000200
 141 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 142 #define CM_CH0_SRATE_88K        0x00000100
 143
 144 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 145 #define CM_DBLSPDS              0x00000040
 146
 147 #define CM_CH1FMT_MASK          0x0000000C
 148 #define CM_CH1FMT_SHIFT         2
 149 #define CM_CH0FMT_MASK          0x00000003
 150 #define CM_CH0FMT_SHIFT         0
 151
 152 #define CM_REG_INT_HLDCLR       0x0C
 153 #define CM_CHIP_MASK2           0xff000000
 154 #define CM_CHIP_039             0x04000000
 155 #define CM_CHIP_039_6CH         0x01000000
 156 #define CM_CHIP_055             0x08000000
 157 #define CM_CHIP_8768            0x20000000
 158 #define CM_TDMA_INT_EN          0x00040000
 159 #define CM_CH1_INT_EN           0x00020000
 160 #define CM_CH0_INT_EN           0x00010000
 161 #define CM_INT_HOLD             0x00000002
 162 #define CM_INT_CLEAR            0x00000001
 163
 164 #define CM_REG_INT_STATUS       0x10
 165 #define CM_INTR                 0x80000000
 166 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 167 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 168 #define CM_UARTINT              0x00010000
 169 #define CM_LTDMAINT             0x00008000
 170 #define CM_HTDMAINT             0x00004000
 171 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 172 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 173 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 174 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 175 #define CM_CH1BUSY              0x00000008
 176 #define CM_CH0BUSY              0x00000004
 177 #define CM_CHINT1               0x00000002
 178 #define CM_CHINT0               0x00000001
 179
 180 #define CM_REG_LEGACY_CTRL      0x14
 181 #define CM_NXCHG                0x80000000      /* h/w multi channels? */
 182 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 183 #define CM_VMPU_330             0x00000000
 184 #define CM_VMPU_320             0x20000000
 185 #define CM_VMPU_310             0x40000000
 186 #define CM_VMPU_300             0x60000000
 187 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 188 #define CM_VSBSEL_220           0x00000000
 189 #define CM_VSBSEL_240           0x04000000
 190 #define CM_VSBSEL_260           0x08000000
 191 #define CM_VSBSEL_280           0x0C000000
 192 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 193 #define CM_FMSEL_388            0x00000000
 194 #define CM_FMSEL_3C8            0x01000000
 195 #define CM_FMSEL_3E0            0x02000000
 196 #define CM_FMSEL_3E8            0x03000000
 197 #define CM_ENSPDOUT             0x00800000      /* enable XPDIF/OUT to I/O interface */
 198 #define CM_SPDCOPYRHT           0x00400000      /* set copyright spdif in/out */
 199 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 200 #define CM_SETRETRY             0x00010000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 201 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 202 #define CM_LINE_AS_BASS         0x00006000      /* use line-in as bass */
 203
 204 #define CM_REG_MISC_CTRL        0x18
 205 #define CM_PWD                  0x80000000
 206 #define CM_RESET                0x40000000
 207 #define CM_SFIL_MASK            0x30000000
 208 #define CM_TXVX                 0x08000000
 209 #define CM_N4SPK3D              0x04000000      /* 4ch output */
 210 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 211 #define CM_SPDIF48K             0x01000000      /* write */
 212 #define CM_SPATUS48K            0x01000000      /* read */
 213 #define CM_ENDBDAC              0x00800000      /* enable dual dac */
 214 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 215 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 216 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-IN -> int. OUT */
 217 #define CM_FM_EN                0x00080000      /* enalbe FM */
 218 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 219 #define CM_VIDWPDSB             0x00010000
 220 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 221 #define CM_MASK_EN              0x00004000
 222 #define CM_VIDWPPRT             0x00002000
 223 #define CM_SFILENB              0x00001000
 224 #define CM_MMODE_MASK           0x00000E00
 225 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 226 #define CM_ENCENTER             0x00000080
 227 #define CM_FLINKON              0x00000040
 228 #define CM_FLINKOFF             0x00000020
 229 #define CM_MIDSMP               0x00000010
 230 #define CM_UPDDMA_MASK          0x0000000C
 231 #define CM_TWAIT_MASK           0x00000003
 232
 233         /* byte */
 234 #define CM_REG_MIXER0           0x20
 235
 236 #define CM_REG_SB16_DATA        0x22
 237 #define CM_REG_SB16_ADDR        0x23
 238
 239 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 240 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 241 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 242 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 243
 244 #define CM_REG_MIXER1           0x24
 245 #define CM_FMMUTE               0x80    /* mute FM */
 246 #define CM_FMMUTE_SHIFT         7
 247 #define CM_WSMUTE               0x40    /* mute PCM */
 248 #define CM_WSMUTE_SHIFT         6
 249 #define CM_SPK4                 0x20    /* lin-in -> rear line out */
 250 #define CM_SPK4_SHIFT           5
 251 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 252 #define CM_REAR2FRONT_SHIFT     4
 253 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 254 #define CM_WAVEINL_SHIFT        3
 255 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 256 #define CM_WAVEINR_SHIFT        2
 257 #define CM_X3DEN                0x02    /* 3D surround enable */
 258 #define CM_X3DEN_SHIFT          1
 259 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 260 #define CM_CDPLAY_SHIFT         0
 261
 262 #define CM_REG_MIXER2           0x25
 263 #define CM_RAUXREN              0x80    /* AUX right capture */
 264 #define CM_RAUXREN_SHIFT        7
 265 #define CM_RAUXLEN              0x40    /* AUX left capture */
 266 #define CM_RAUXLEN_SHIFT        6
 267 #define CM_VAUXRM               0x20    /* AUX right mute */
 268 #define CM_VAUXRM_SHIFT         5
 269 #define CM_VAUXLM               0x10    /* AUX left mute */
 270 #define CM_VAUXLM_SHIFT         4
 271 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 272 #define CM_VADMIC_SHIFT         1
 273 #define CM_MICGAINZ             0x01    /* mic boost */
 274 #define CM_MICGAINZ_SHIFT       0
 275
 276 #define CM_REG_MIXER3           0x24
 277 #define CM_REG_AUX_VOL          0x26
 278 #define CM_VAUXL_MASK           0xf0
 279 #define CM_VAUXR_MASK           0x0f
 280
 281 #define CM_REG_MISC             0x27
 282 #define CM_XGPO1                0x20
 283 // #define CM_XGPBIO            0x04
 284 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 285 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 286 #define CM_SPDVALID             0x02    /* spdif input valid check */
 287 #define CM_DMAUTO               0x01
 288
 289 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 290 /*
 291  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 292  * or identical with AC97 codec?
 293  */
 294 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 295
 296 /*
 297  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 298  */
 299 #define CM_REG_MPU_PCI          0x40
 300
 301 /*
 302  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 303  */
 304 #define CM_REG_FM_PCI           0x50
 305
 306 /*
 307  * access from SB-mixer port
 308  */
 309 #define CM_REG_EXTENT_IND       0xf0
 310 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 311 #define CM_VPHONE_SHIFT         5
 312 #define CM_VPHOM                0x10    /* Phone mute control */
 313 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 314 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 315 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 316 #define CM_VADMIC3              0x01    /* Mic record boost */
 317
 318 /*
 319  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 320  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 321  * unit (readonly?).
 322  */
 323 #define CM_REG_PLL              0xf8
 324
 325 /*
 326  * extended registers
 327  */
 328 #define CM_REG_CH0_FRAME1       0x80    /* base address */
 329 #define CM_REG_CH0_FRAME2       0x84
 330 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 331 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 332 #define CM_REG_EXT_MISC         0x90
 333 #define CM_REG_MISC_CTRL_8768   0x92    /* reg. name the same as 0x18 */
 334 #define CM_CHB3D8C              0x20    /* 7.1 channels support */
 335 #define CM_SPD32FMT             0x10    /* SPDIF/IN 32k */
 336 #define CM_ADC2SPDIF            0x08    /* ADC output to SPDIF/OUT */
 337 #define CM_SHAREADC             0x04    /* DAC in ADC as Center/LFE */
 338 #define CM_REALTCMP             0x02    /* monitor the CMPL/CMPR of ADC */
 339 #define CM_INVLRCK              0x01    /* invert ZVPORT's LRCK */
 340
 341 /*
 342  * size of i/o region
 343  */
 344 #define CM_EXTENT_CODEC   0x100
 345 #define CM_EXTENT_MIDI    0x2
 346 #define CM_EXTENT_SYNTH   0x4
 347
 348
 349 /*
 350  * channels for playback / capture
 351  */
 352 #define CM_CH_PLAY      0
 353 #define CM_CH_CAPT      1
 354
 355 /*
 356  * flags to check device open/close
 357  */
 358 #define CM_OPEN_NONE    0
 359 #define CM_OPEN_CH_MASK 0x01
 360 #define CM_OPEN_DAC     0x10
 361 #define CM_OPEN_ADC     0x20
 362 #define CM_OPEN_SPDIF   0x40
 363 #define CM_OPEN_MCHAN   0x80
 364 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 365 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 366 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 367 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 368 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 369 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 370
 371
 372 #if CM_CH_PLAY == 1
 373 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 374 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 375 #define CM_CAPTURE_SPDF         CM_SPDF_0
 376 #else
 377 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 378 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 379 #define CM_CAPTURE_SPDF         CM_SPDF_1
 380 #endif
 381
 382
 383 /*
 384  * driver data
 385  */
 386
 387 struct cmipci_pcm {
 388         struct snd_pcm_substream *substream;
 389         int running;            /* dac/adc running? */
 390         unsigned int dma_size;  /* in frames */
 391         unsigned int period_size;       /* in frames */
 392         unsigned int offset;    /* physical address of the buffer */
 393         unsigned int fmt;       /* format bits */
 394         int ch;                 /* channel (0/1) */
 395         unsigned int is_dac;            /* is dac? */
 396         int bytes_per_frame;
 397         int shift;
 398 };
 399
 400 /* mixer elements toggled/resumed during ac3 playback */
 401 struct cmipci_mixer_auto_switches {
 402         const char *name;       /* switch to toggle */
 403         int toggle_on;          /* value to change when ac3 mode */
 404 };
 405 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 406         {"PCM Playback Switch", 0},
 407         {"IEC958 Output Switch", 1},
 408         {"IEC958 Mix Analog", 0},
 409         // {"IEC958 Out To DAC", 1}, // no longer used
 410         {"IEC958 Loop", 0},
 411 };
 412 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 413
 414 struct cmipci {
 415         struct snd_card *card;
 416
 417         struct pci_dev *pci;
 418         unsigned int device;    /* device ID */
 419         int irq;
 420
 421         unsigned long iobase;
 422         unsigned int ctrl;      /* FUNCTRL0 current value */
 423
 424         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 425         struct snd_pcm *pcm2;   /* 2nd DAC */
 426         struct snd_pcm *pcm_spdif;      /* SPDIF */
 427
 428         int chip_version;
 429         int max_channels;
 430         unsigned int can_ac3_sw: 1;
 431         unsigned int can_ac3_hw: 1;
 432         unsigned int can_multi_ch: 1;
 433         unsigned int do_soft_ac3: 1;
 434
 435         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 436         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 437         int spdif_counter;      /* for software AC3 */
 438
 439         unsigned int dig_status;
 440         unsigned int dig_pcm_status;
 441
 442         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 443
 444         int opened[2];  /* open mode */
 445         struct mutex open_mutex;
 446
 447         unsigned int mixer_insensitive: 1;
 448         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 449         int mixer_res_status[CM_SAVED_MIXERS];
 450
 451         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 452
 453         /* external MIDI */
 454         struct snd_rawmidi *rmidi;
 455
 456 #ifdef SUPPORT_JOYSTICK
 457         struct gameport *gameport;
 458 #endif
 459
 460         spinlock_t reg_lock;
 461
 462 #ifdef CONFIG_PM
 463         unsigned int saved_regs[0x20];
 464         unsigned char saved_mixers[0x20];
 465 #endif
 466 };
 467
 468
 469 /* read/write operations for dword register */
 470 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 471 {
 472         outl(data, cm->iobase + cmd);
 473 }
 474
 475 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 476 {
 477         return inl(cm->iobase + cmd);
 478 }
 479
 480 /* read/write operations for word register */
 481 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 482 {
 483         outw(data, cm->iobase + cmd);
 484 }
 485
 486 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 487 {
 488         return inw(cm->iobase + cmd);
 489 }
 490
 491 /* read/write operations for byte register */
 492 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 493 {
 494         outb(data, cm->iobase + cmd);
 495 }
 496
 497 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 498 {
 499         return inb(cm->iobase + cmd);
 500 }
 501
 502 /* bit operations for dword register */
 503 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 504 {
 505         unsigned int val, oval;
 506         val = oval = inl(cm->iobase + cmd);
 507         val |= flag;
 508         if (val == oval)
 509                 return 0;
 510         outl(val, cm->iobase + cmd);
 511         return 1;
 512 }
 513
 514 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 515 {
 516         unsigned int val, oval;
 517         val = oval = inl(cm->iobase + cmd);
 518         val &= ~flag;
 519         if (val == oval)
 520                 return 0;
 521         outl(val, cm->iobase + cmd);
 522         return 1;
 523 }
 524
 525 /* bit operations for byte register */
 526 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 527 {
 528         unsigned char val, oval;
 529         val = oval = inb(cm->iobase + cmd);
 530         val |= flag;
 531         if (val == oval)
 532                 return 0;
 533         outb(val, cm->iobase + cmd);
 534         return 1;
 535 }
 536
 537 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 538 {
 539         unsigned char val, oval;
 540         val = oval = inb(cm->iobase + cmd);
 541         val &= ~flag;
 542         if (val == oval)
 543                 return 0;
 544         outb(val, cm->iobase + cmd);
 545         return 1;
 546 }
 547
 548
 549 /*
 550  * PCM interface
 551  */
 552
 553 /*
 554  * calculate frequency
 555  */
 556
 557 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 558
 559 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 560 {
 561         unsigned int i;
 562         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 563                 if (rates[i] == rate)
 564                         return i;
 565         }
 566         snd_BUG();
 567         return 0;
 568 }
 569
 570 #ifdef USE_VAR48KRATE
 571 /*
 572  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 573  * does it this way .. maybe not.  Never get any information from C-Media about
 574  * that <werner@suse.de>.
 575  */
 576 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 577 {
 578         unsigned int delta, tolerance;
 579         int xm, xn, xr;
 580
 581         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 582                 rate <<= 1;
 583         *n = -1;
 584         if (*r > 0xff)
 585                 goto out;
 586         tolerance = rate*CM_TOLERANCE_RATE;
 587
 588         for (xn = (1+2); xn < (0x1f+2); xn++) {
 589                 for (xm = (1+2); xm < (0xff+2); xm++) {
 590                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 591
 592                         if (xr < rate)
 593                                 delta = rate - xr;
 594                         else
 595                                 delta = xr - rate;
 596
 597                         /*
 598                          * If we found one, remember this,
 599                          * and try to find a closer one
 600                          */
 601                         if (delta < tolerance) {
 602                                 tolerance = delta;
 603                                 *m = xm - 2;
 604                                 *n = xn - 2;
 605                         }
 606                 }
 607         }
 608 out:
 609         return (*n > -1);
 610 }
 611
 612 /*
 613  * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
 614  * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
 615  * at the register CM_REG_FUNCTRL1 (0x04).
 616  * Problem: other ways are also possible (any information about that?)
 617  */
 618 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 619 {
 620         unsigned int reg = CM_REG_PLL + slot;
 621         /*
 622          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 623          * for DSFC/ASFC (000 upto 111).
 624          */
 625
 626         /* FIXME: Init (Do we've to set an other register first before programming?) */
 627
 628         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 629         snd_cmipci_write_b(cm, reg, rate>>8);
 630         snd_cmipci_write_b(cm, reg, rate&0xff);
 631
 632         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 633 }
 634 #endif /* USE_VAR48KRATE */
 635
 636 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
 637                                 struct snd_pcm_hw_params *hw_params)
 638 {
 639         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 640 }
 641
 642 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 643                                           struct snd_pcm_hw_params *hw_params)
 644 {
 645         struct cmipci *cm = snd_pcm_substream_chip(substream);
 646         if (params_channels(hw_params) > 2) {
 647                 mutex_lock(&cm->open_mutex);
 648                 if (cm->opened[CM_CH_PLAY]) {
 649                         mutex_unlock(&cm->open_mutex);
 650                         return -EBUSY;
 651                 }
 652                 /* reserve the channel A */
 653                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 654                 mutex_unlock(&cm->open_mutex);
 655         }
 656         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 657 }
 658
 659 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 660 {
 661         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 662         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 663         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 664         udelay(10);
 665 }
 666
 667 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
 668 {
 669         return snd_pcm_lib_free_pages(substream);
 670 }
 671
 672
 673 /*
 674  */
 675
 676 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
 677 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 678         .count = 3,
 679         .list = hw_channels,
 680         .mask = 0,
 681 };
 682 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 683         .count = 5,
 684         .list = hw_channels,
 685         .mask = 0,
 686 };
 687 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 688         .count = 6,
 689         .list = hw_channels,
 690         .mask = 0,
 691 };
 692
 693 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 694 {
 695         if (channels > 2) {
 696                 if (! cm->can_multi_ch)
 697                         return -EINVAL;
 698                 if (rec->fmt != 0x03) /* stereo 16bit only */
 699                         return -EINVAL;
 700
 701                 spin_lock_irq(&cm->reg_lock);
 702                 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 703                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 704                 if (channels > 4) {
 705                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 706                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 707                 } else {
 708                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 709                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 710                 }
 711                 if (channels >= 6) {
 712                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 713                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 714                 } else {
 715                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 716                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 717                 }
 718                 if (cm->chip_version == 68) {
 719                         if (channels == 8) {
 720                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
 721                         } else {
 722                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
 723                         }
 724                 }
 725                 spin_unlock_irq(&cm->reg_lock);
 726
 727         } else {
 728                 if (cm->can_multi_ch) {
 729                         spin_lock_irq(&cm->reg_lock);
 730                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 731                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 732                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 733                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 734                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 735                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 736                         spin_unlock_irq(&cm->reg_lock);
 737                 }
 738         }
 739         return 0;
 740 }
 741
 742
 743 /*
 744  * prepare playback/capture channel
 745  * channel to be used must have been set in rec->ch.
 746  */
 747 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 748                                  struct snd_pcm_substream *substream)
 749 {
 750         unsigned int reg, freq, val;
 751         struct snd_pcm_runtime *runtime = substream->runtime;
 752
 753         rec->fmt = 0;
 754         rec->shift = 0;
 755         if (snd_pcm_format_width(runtime->format) >= 16) {
 756                 rec->fmt |= 0x02;
 757                 if (snd_pcm_format_width(runtime->format) > 16)
 758                         rec->shift++; /* 24/32bit */
 759         }
 760         if (runtime->channels > 1)
 761                 rec->fmt |= 0x01;
 762         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 763                 snd_printd("cannot set dac channels\n");
 764                 return -EINVAL;
 765         }
 766
 767         rec->offset = runtime->dma_addr;
 768         /* buffer and period sizes in frame */
 769         rec->dma_size = runtime->buffer_size << rec->shift;
 770         rec->period_size = runtime->period_size << rec->shift;
 771         if (runtime->channels > 2) {
 772                 /* multi-channels */
 773                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 774                 rec->period_size = (rec->period_size * runtime->channels) / 2;
 775         }
 776
 777         spin_lock_irq(&cm->reg_lock);
 778
 779         /* set buffer address */
 780         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 781         snd_cmipci_write(cm, reg, rec->offset);
 782         /* program sample counts */
 783         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 784         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 785         snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
 786
 787         /* set adc/dac flag */
 788         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 789         if (rec->is_dac)
 790                 cm->ctrl &= ~val;
 791         else
 792                 cm->ctrl |= val;
 793         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 794         //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 795
 796         /* set sample rate */
 797         freq = snd_cmipci_rate_freq(runtime->rate);
 798         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 799         if (rec->ch) {
 800                 val &= ~CM_ASFC_MASK;
 801                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 802         } else {
 803                 val &= ~CM_DSFC_MASK;
 804                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 805         }
 806         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 807         //snd_printd("cmipci: functrl1 = %08x\n", val);
 808
 809         /* set format */
 810         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 811         if (rec->ch) {
 812                 val &= ~CM_CH1FMT_MASK;
 813                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 814         } else {
 815                 val &= ~CM_CH0FMT_MASK;
 816                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 817         }
 818         if (cm->chip_version == 68) {
 819                 if (runtime->rate == 88200)
 820                         val |= CM_CH0_SRATE_88K << (rec->ch * 2);
 821                 else
 822                         val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
 823                 if (runtime->rate == 96000)
 824                         val |= CM_CH0_SRATE_96K << (rec->ch * 2);
 825                 else
 826                         val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
 827         }
 828         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 829         //snd_printd("cmipci: chformat = %08x\n", val);
 830
 831         rec->running = 0;
 832         spin_unlock_irq(&cm->reg_lock);
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * PCM trigger/stop
 839  */
 840 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 841                                   struct snd_pcm_substream *substream, int cmd)
 842 {
 843         unsigned int inthld, chen, reset, pause;
 844         int result = 0;
 845
 846         inthld = CM_CH0_INT_EN << rec->ch;
 847         chen = CM_CHEN0 << rec->ch;
 848         reset = CM_RST_CH0 << rec->ch;
 849         pause = CM_PAUSE0 << rec->ch;
 850
 851         spin_lock(&cm->reg_lock);
 852         switch (cmd) {
 853         case SNDRV_PCM_TRIGGER_START:
 854                 rec->running = 1;
 855                 /* set interrupt */
 856                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 857                 cm->ctrl |= chen;
 858                 /* enable channel */
 859                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 860                 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 861                 break;
 862         case SNDRV_PCM_TRIGGER_STOP:
 863                 rec->running = 0;
 864                 /* disable interrupt */
 865                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 866                 /* reset */
 867                 cm->ctrl &= ~chen;
 868                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 869                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 870                 break;
 871         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 872         case SNDRV_PCM_TRIGGER_SUSPEND:
 873                 cm->ctrl |= pause;
 874                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 875                 break;
 876         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 877         case SNDRV_PCM_TRIGGER_RESUME:
 878                 cm->ctrl &= ~pause;
 879                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 880                 break;
 881         default:
 882                 result = -EINVAL;
 883                 break;
 884         }
 885         spin_unlock(&cm->reg_lock);
 886         return result;
 887 }
 888
 889 /*
 890  * return the current pointer
 891  */
 892 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 893                                                 struct snd_pcm_substream *substream)
 894 {
 895         size_t ptr;
 896         unsigned int reg;
 897         if (!rec->running)
 898                 return 0;
 899 #if 1 // this seems better..
 900         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 901         ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
 902         ptr >>= rec->shift;
 903 #else
 904         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 905         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 906         ptr = bytes_to_frames(substream->runtime, ptr);
 907 #endif
 908         if (substream->runtime->channels > 2)
 909                 ptr = (ptr * 2) / substream->runtime->channels;
 910         return ptr;
 911 }
 912
 913 /*
 914  * playback
 915  */
 916
 917 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 918                                        int cmd)
 919 {
 920         struct cmipci *cm = snd_pcm_substream_chip(substream);
 921         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
 922 }
 923
 924 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 925 {
 926         struct cmipci *cm = snd_pcm_substream_chip(substream);
 927         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 928 }
 929
 930
 931
 932 /*
 933  * capture
 934  */
 935
 936 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 937                                      int cmd)
 938 {
 939         struct cmipci *cm = snd_pcm_substream_chip(substream);
 940         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
 941 }
 942
 943 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 944 {
 945         struct cmipci *cm = snd_pcm_substream_chip(substream);
 946         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 947 }
 948
 949
 950 /*
 951  * hw preparation for spdif
 952  */
 953
 954 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 955                                          struct snd_ctl_elem_info *uinfo)
 956 {
 957         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 958         uinfo->count = 1;
 959         return 0;
 960 }
 961
 962 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
 963                                         struct snd_ctl_elem_value *ucontrol)
 964 {
 965         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 966         int i;
 967
 968         spin_lock_irq(&chip->reg_lock);
 969         for (i = 0; i < 4; i++)
 970                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 971         spin_unlock_irq(&chip->reg_lock);
 972         return 0;
 973 }
 974
 975 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
 976                                          struct snd_ctl_elem_value *ucontrol)
 977 {
 978         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 979         int i, change;
 980         unsigned int val;
 981
 982         val = 0;
 983         spin_lock_irq(&chip->reg_lock);
 984         for (i = 0; i < 4; i++)
 985                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
 986         change = val != chip->dig_status;
 987         chip->dig_status = val;
 988         spin_unlock_irq(&chip->reg_lock);
 989         return change;
 990 }
 991
 992 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
 993 {
 994         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
 995         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
 996         .info =         snd_cmipci_spdif_default_info,
 997         .get =          snd_cmipci_spdif_default_get,
 998         .put =          snd_cmipci_spdif_default_put
 999 };
1000
1001 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1002                                       struct snd_ctl_elem_info *uinfo)
1003 {
1004         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1005         uinfo->count = 1;
1006         return 0;
1007 }
1008
1009 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1010                                      struct snd_ctl_elem_value *ucontrol)
1011 {
1012         ucontrol->value.iec958.status[0] = 0xff;
1013         ucontrol->value.iec958.status[1] = 0xff;
1014         ucontrol->value.iec958.status[2] = 0xff;
1015         ucontrol->value.iec958.status[3] = 0xff;
1016         return 0;
1017 }
1018
1019 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1020 {
1021         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1022         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1023         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1024         .info =         snd_cmipci_spdif_mask_info,
1025         .get =          snd_cmipci_spdif_mask_get,
1026 };
1027
1028 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1029                                         struct snd_ctl_elem_info *uinfo)
1030 {
1031         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1032         uinfo->count = 1;
1033         return 0;
1034 }
1035
1036 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1037                                        struct snd_ctl_elem_value *ucontrol)
1038 {
1039         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1040         int i;
1041
1042         spin_lock_irq(&chip->reg_lock);
1043         for (i = 0; i < 4; i++)
1044                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1045         spin_unlock_irq(&chip->reg_lock);
1046         return 0;
1047 }
1048
1049 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1050                                        struct snd_ctl_elem_value *ucontrol)
1051 {
1052         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1053         int i, change;
1054         unsigned int val;
1055
1056         val = 0;
1057         spin_lock_irq(&chip->reg_lock);
1058         for (i = 0; i < 4; i++)
1059                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1060         change = val != chip->dig_pcm_status;
1061         chip->dig_pcm_status = val;
1062         spin_unlock_irq(&chip->reg_lock);
1063         return change;
1064 }
1065
1066 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1067 {
1068         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1069         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1070         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1071         .info =         snd_cmipci_spdif_stream_info,
1072         .get =          snd_cmipci_spdif_stream_get,
1073         .put =          snd_cmipci_spdif_stream_put
1074 };
1075
1076 /*
1077  */
1078
1079 /* save mixer setting and mute for AC3 playback */
1080 static int save_mixer_state(struct cmipci *cm)
1081 {
1082         if (! cm->mixer_insensitive) {
1083                 struct snd_ctl_elem_value *val;
1084                 unsigned int i;
1085
1086                 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1087                 if (!val)
1088                         return -ENOMEM;
1089                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1090                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1091                         if (ctl) {
1092                                 int event;
1093                                 memset(val, 0, sizeof(*val));
1094                                 ctl->get(ctl, val);
1095                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1096                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1097                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1098                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1099                                         ctl->put(ctl, val); /* toggle */
1100                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1101                                 }
1102                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1103                                 snd_ctl_notify(cm->card, event, &ctl->id);
1104                         }
1105                 }
1106                 kfree(val);
1107                 cm->mixer_insensitive = 1;
1108         }
1109         return 0;
1110 }
1111
1112
1113 /* restore the previously saved mixer status */
1114 static void restore_mixer_state(struct cmipci *cm)
1115 {
1116         if (cm->mixer_insensitive) {
1117                 struct snd_ctl_elem_value *val;
1118                 unsigned int i;
1119
1120                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1121                 if (!val)
1122                         return;
1123                 cm->mixer_insensitive = 0; /* at first clear this;
1124                                               otherwise the changes will be ignored */
1125                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1126                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1127                         if (ctl) {
1128                                 int event;
1129
1130                                 memset(val, 0, sizeof(*val));
1131                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1132                                 ctl->get(ctl, val);
1133                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1134                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1135                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1136                                         ctl->put(ctl, val);
1137                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1138                                 }
1139                                 snd_ctl_notify(cm->card, event, &ctl->id);
1140                         }
1141                 }
1142                 kfree(val);
1143         }
1144 }
1145
1146 /* spinlock held! */
1147 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1148 {
1149         if (do_ac3) {
1150                 /* AC3EN for 037 */
1151                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1152                 /* AC3EN for 039 */
1153                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1154
1155                 if (cm->can_ac3_hw) {
1156                         /* SPD24SEL for 037, 0x02 */
1157                         /* SPD24SEL for 039, 0x20, but cannot be set */
1158                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1159                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1160                 } else { /* can_ac3_sw */
1161                         /* SPD32SEL for 037 & 039, 0x20 */
1162                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1163                         /* set 176K sample rate to fix 033 HW bug */
1164                         if (cm->chip_version == 33) {
1165                                 if (rate >= 48000) {
1166                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1167                                 } else {
1168                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1169                                 }
1170                         }
1171                 }
1172
1173         } else {
1174                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1175                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1176
1177                 if (cm->can_ac3_hw) {
1178                         /* chip model >= 37 */
1179                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1180                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1181                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1182                         } else {
1183                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1184                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1185                         }
1186                 } else {
1187                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1189                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1190                 }
1191         }
1192 }
1193
1194 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1195 {
1196         int rate, err;
1197
1198         rate = subs->runtime->rate;
1199
1200         if (up && do_ac3)
1201                 if ((err = save_mixer_state(cm)) < 0)
1202                         return err;
1203
1204         spin_lock_irq(&cm->reg_lock);
1205         cm->spdif_playback_avail = up;
1206         if (up) {
1207                 /* they are controlled via "IEC958 Output Switch" */
1208                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1209                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1210                 if (cm->spdif_playback_enabled)
1211                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1212                 setup_ac3(cm, subs, do_ac3, rate);
1213
1214                 if (rate == 48000 || rate == 96000)
1215                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1216                 else
1217                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1218                 if (rate > 48000)
1219                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1220                 else
1221                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1222         } else {
1223                 /* they are controlled via "IEC958 Output Switch" */
1224                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1225                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1226                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1227                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1228                 setup_ac3(cm, subs, 0, 0);
1229         }
1230         spin_unlock_irq(&cm->reg_lock);
1231         return 0;
1232 }
1233
1234
1235 /*
1236  * preparation
1237  */
1238
1239 /* playback - enable spdif only on the certain condition */
1240 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1241 {
1242         struct cmipci *cm = snd_pcm_substream_chip(substream);
1243         int rate = substream->runtime->rate;
1244         int err, do_spdif, do_ac3 = 0;
1245
1246         do_spdif = (rate >= 44100 &&
1247                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1248                     substream->runtime->channels == 2);
1249         if (do_spdif && cm->can_ac3_hw)
1250                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1251         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1252                 return err;
1253         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1254 }
1255
1256 /* playback  (via device #2) - enable spdif always */
1257 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1258 {
1259         struct cmipci *cm = snd_pcm_substream_chip(substream);
1260         int err, do_ac3;
1261
1262         if (cm->can_ac3_hw)
1263                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1264         else
1265                 do_ac3 = 1; /* doesn't matter */
1266         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1267                 return err;
1268         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1269 }
1270
1271 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1272 {
1273         struct cmipci *cm = snd_pcm_substream_chip(substream);
1274         setup_spdif_playback(cm, substream, 0, 0);
1275         restore_mixer_state(cm);
1276         return snd_cmipci_hw_free(substream);
1277 }
1278
1279 /* capture */
1280 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1281 {
1282         struct cmipci *cm = snd_pcm_substream_chip(substream);
1283         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1284 }
1285
1286 /* capture with spdif (via device #2) */
1287 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1288 {
1289         struct cmipci *cm = snd_pcm_substream_chip(substream);
1290
1291         spin_lock_irq(&cm->reg_lock);
1292         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1293         spin_unlock_irq(&cm->reg_lock);
1294
1295         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1296 }
1297
1298 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1299 {
1300         struct cmipci *cm = snd_pcm_substream_chip(subs);
1301
1302         spin_lock_irq(&cm->reg_lock);
1303         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1304         spin_unlock_irq(&cm->reg_lock);
1305
1306         return snd_cmipci_hw_free(subs);
1307 }
1308
1309
1310 /*
1311  * interrupt handler
1312  */
1313 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1314 {
1315         struct cmipci *cm = dev_id;
1316         unsigned int status, mask = 0;
1317
1318         /* fastpath out, to ease interrupt sharing */
1319         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1320         if (!(status & CM_INTR))
1321                 return IRQ_NONE;
1322
1323         /* acknowledge interrupt */
1324         spin_lock(&cm->reg_lock);
1325         if (status & CM_CHINT0)
1326                 mask |= CM_CH0_INT_EN;
1327         if (status & CM_CHINT1)
1328                 mask |= CM_CH1_INT_EN;
1329         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1330         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1331         spin_unlock(&cm->reg_lock);
1332
1333         if (cm->rmidi && (status & CM_UARTINT))
1334                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1335
1336         if (cm->pcm) {
1337                 if ((status & CM_CHINT0) && cm->channel[0].running)
1338                         snd_pcm_period_elapsed(cm->channel[0].substream);
1339                 if ((status & CM_CHINT1) && cm->channel[1].running)
1340                         snd_pcm_period_elapsed(cm->channel[1].substream);
1341         }
1342         return IRQ_HANDLED;
1343 }
1344
1345 /*
1346  * h/w infos
1347  */
1348
1349 /* playback on channel A */
1350 static struct snd_pcm_hardware snd_cmipci_playback =
1351 {
1352         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1353                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1354                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1355         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1356         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1357         .rate_min =             5512,
1358         .rate_max =             48000,
1359         .channels_min =         1,
1360         .channels_max =         2,
1361         .buffer_bytes_max =     (128*1024),
1362         .period_bytes_min =     64,
1363         .period_bytes_max =     (128*1024),
1364         .periods_min =          2,
1365         .periods_max =          1024,
1366         .fifo_size =            0,
1367 };
1368
1369 /* capture on channel B */
1370 static struct snd_pcm_hardware snd_cmipci_capture =
1371 {
1372         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1373                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1374                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1375         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1376         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1377         .rate_min =             5512,
1378         .rate_max =             48000,
1379         .channels_min =         1,
1380         .channels_max =         2,
1381         .buffer_bytes_max =     (128*1024),
1382         .period_bytes_min =     64,
1383         .period_bytes_max =     (128*1024),
1384         .periods_min =          2,
1385         .periods_max =          1024,
1386         .fifo_size =            0,
1387 };
1388
1389 /* playback on channel B - stereo 16bit only? */
1390 static struct snd_pcm_hardware snd_cmipci_playback2 =
1391 {
1392         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1393                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1394                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1395         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1396         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1397         .rate_min =             5512,
1398         .rate_max =             48000,
1399         .channels_min =         2,
1400         .channels_max =         2,
1401         .buffer_bytes_max =     (128*1024),
1402         .period_bytes_min =     64,
1403         .period_bytes_max =     (128*1024),
1404         .periods_min =          2,
1405         .periods_max =          1024,
1406         .fifo_size =            0,
1407 };
1408
1409 /* spdif playback on channel A */
1410 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1411 {
1412         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1413                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1414                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1415         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1416         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1417         .rate_min =             44100,
1418         .rate_max =             48000,
1419         .channels_min =         2,
1420         .channels_max =         2,
1421         .buffer_bytes_max =     (128*1024),
1422         .period_bytes_min =     64,
1423         .period_bytes_max =     (128*1024),
1424         .periods_min =          2,
1425         .periods_max =          1024,
1426         .fifo_size =            0,
1427 };
1428
1429 /* spdif playback on channel A (32bit, IEC958 subframes) */
1430 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1431 {
1432         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1433                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1434                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1435         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1436         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1437         .rate_min =             44100,
1438         .rate_max =             48000,
1439         .channels_min =         2,
1440         .channels_max =         2,
1441         .buffer_bytes_max =     (128*1024),
1442         .period_bytes_min =     64,
1443         .period_bytes_max =     (128*1024),
1444         .periods_min =          2,
1445         .periods_max =          1024,
1446         .fifo_size =            0,
1447 };
1448
1449 /* spdif capture on channel B */
1450 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1451 {
1452         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1453                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1454                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1455         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1456         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1457         .rate_min =             44100,
1458         .rate_max =             48000,
1459         .channels_min =         2,
1460         .channels_max =         2,
1461         .buffer_bytes_max =     (128*1024),
1462         .period_bytes_min =     64,
1463         .period_bytes_max =     (128*1024),
1464         .periods_min =          2,
1465         .periods_max =          1024,
1466         .fifo_size =            0,
1467 };
1468
1469 /*
1470  * check device open/close
1471  */
1472 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1473 {
1474         int ch = mode & CM_OPEN_CH_MASK;
1475
1476         /* FIXME: a file should wait until the device becomes free
1477          * when it's opened on blocking mode.  however, since the current
1478          * pcm framework doesn't pass file pointer before actually opened,
1479          * we can't know whether blocking mode or not in open callback..
1480          */
1481         mutex_lock(&cm->open_mutex);
1482         if (cm->opened[ch]) {
1483                 mutex_unlock(&cm->open_mutex);
1484                 return -EBUSY;
1485         }
1486         cm->opened[ch] = mode;
1487         cm->channel[ch].substream = subs;
1488         if (! (mode & CM_OPEN_DAC)) {
1489                 /* disable dual DAC mode */
1490                 cm->channel[ch].is_dac = 0;
1491                 spin_lock_irq(&cm->reg_lock);
1492                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1493                 spin_unlock_irq(&cm->reg_lock);
1494         }
1495         mutex_unlock(&cm->open_mutex);
1496         return 0;
1497 }
1498
1499 static void close_device_check(struct cmipci *cm, int mode)
1500 {
1501         int ch = mode & CM_OPEN_CH_MASK;
1502
1503         mutex_lock(&cm->open_mutex);
1504         if (cm->opened[ch] == mode) {
1505                 if (cm->channel[ch].substream) {
1506                         snd_cmipci_ch_reset(cm, ch);
1507                         cm->channel[ch].running = 0;
1508                         cm->channel[ch].substream = NULL;
1509                 }
1510                 cm->opened[ch] = 0;
1511                 if (! cm->channel[ch].is_dac) {
1512                         /* enable dual DAC mode again */
1513                         cm->channel[ch].is_dac = 1;
1514                         spin_lock_irq(&cm->reg_lock);
1515                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1516                         spin_unlock_irq(&cm->reg_lock);
1517                 }
1518         }
1519         mutex_unlock(&cm->open_mutex);
1520 }
1521
1522 /*
1523  */
1524
1525 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1526 {
1527         struct cmipci *cm = snd_pcm_substream_chip(substream);
1528         struct snd_pcm_runtime *runtime = substream->runtime;
1529         int err;
1530
1531         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1532                 return err;
1533         runtime->hw = snd_cmipci_playback;
1534         if (cm->chip_version == 68) {
1535                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1536                                      SNDRV_PCM_RATE_96000;
1537                 runtime->hw.rate_max = 96000;
1538         }
1539         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1540         cm->dig_pcm_status = cm->dig_status;
1541         return 0;
1542 }
1543
1544 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1545 {
1546         struct cmipci *cm = snd_pcm_substream_chip(substream);
1547         struct snd_pcm_runtime *runtime = substream->runtime;
1548         int err;
1549
1550         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1551                 return err;
1552         runtime->hw = snd_cmipci_capture;
1553         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1554                 runtime->hw.rate_min = 41000;
1555                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1556         }
1557         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1558         return 0;
1559 }
1560
1561 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1562 {
1563         struct cmipci *cm = snd_pcm_substream_chip(substream);
1564         struct snd_pcm_runtime *runtime = substream->runtime;
1565         int err;
1566
1567         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1568                 return err;
1569         runtime->hw = snd_cmipci_playback2;
1570         mutex_lock(&cm->open_mutex);
1571         if (! cm->opened[CM_CH_PLAY]) {
1572                 if (cm->can_multi_ch) {
1573                         runtime->hw.channels_max = cm->max_channels;
1574                         if (cm->max_channels == 4)
1575                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1576                         else if (cm->max_channels == 6)
1577                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1578                         else if (cm->max_channels == 8)
1579                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1580                 }
1581                 if (cm->chip_version == 68) {
1582                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1583                                              SNDRV_PCM_RATE_96000;
1584                         runtime->hw.rate_max = 96000;
1585                 }
1586                 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1587         }
1588         mutex_unlock(&cm->open_mutex);
1589         return 0;
1590 }
1591
1592 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1593 {
1594         struct cmipci *cm = snd_pcm_substream_chip(substream);
1595         struct snd_pcm_runtime *runtime = substream->runtime;
1596         int err;
1597
1598         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1599                 return err;
1600         if (cm->can_ac3_hw) {
1601                 runtime->hw = snd_cmipci_playback_spdif;
1602                 if (cm->chip_version >= 37)
1603                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1604                 if (cm->chip_version == 68) {
1605                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1606                                              SNDRV_PCM_RATE_96000;
1607                         runtime->hw.rate_max = 96000;
1608                 }
1609         } else {
1610                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1611         }
1612         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1613         cm->dig_pcm_status = cm->dig_status;
1614         return 0;
1615 }
1616
1617 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1618 {
1619         struct cmipci *cm = snd_pcm_substream_chip(substream);
1620         struct snd_pcm_runtime *runtime = substream->runtime;
1621         int err;
1622
1623         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1624                 return err;
1625         runtime->hw = snd_cmipci_capture_spdif;
1626         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1627         return 0;
1628 }
1629
1630
1631 /*
1632  */
1633
1634 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1635 {
1636         struct cmipci *cm = snd_pcm_substream_chip(substream);
1637         close_device_check(cm, CM_OPEN_PLAYBACK);
1638         return 0;
1639 }
1640
1641 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1642 {
1643         struct cmipci *cm = snd_pcm_substream_chip(substream);
1644         close_device_check(cm, CM_OPEN_CAPTURE);
1645         return 0;
1646 }
1647
1648 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1649 {
1650         struct cmipci *cm = snd_pcm_substream_chip(substream);
1651         close_device_check(cm, CM_OPEN_PLAYBACK2);
1652         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1653         return 0;
1654 }
1655
1656 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1657 {
1658         struct cmipci *cm = snd_pcm_substream_chip(substream);
1659         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1660         return 0;
1661 }
1662
1663 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1664 {
1665         struct cmipci *cm = snd_pcm_substream_chip(substream);
1666         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1667         return 0;
1668 }
1669
1670
1671 /*
1672  */
1673
1674 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1675         .open =         snd_cmipci_playback_open,
1676         .close =        snd_cmipci_playback_close,
1677         .ioctl =        snd_pcm_lib_ioctl,
1678         .hw_params =    snd_cmipci_hw_params,
1679         .hw_free =      snd_cmipci_playback_hw_free,
1680         .prepare =      snd_cmipci_playback_prepare,
1681         .trigger =      snd_cmipci_playback_trigger,
1682         .pointer =      snd_cmipci_playback_pointer,
1683 };
1684
1685 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1686         .open =         snd_cmipci_capture_open,
1687         .close =        snd_cmipci_capture_close,
1688         .ioctl =        snd_pcm_lib_ioctl,
1689         .hw_params =    snd_cmipci_hw_params,
1690         .hw_free =      snd_cmipci_hw_free,
1691         .prepare =      snd_cmipci_capture_prepare,
1692         .trigger =      snd_cmipci_capture_trigger,
1693         .pointer =      snd_cmipci_capture_pointer,
1694 };
1695
1696 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1697         .open =         snd_cmipci_playback2_open,
1698         .close =        snd_cmipci_playback2_close,
1699         .ioctl =        snd_pcm_lib_ioctl,
1700         .hw_params =    snd_cmipci_playback2_hw_params,
1701         .hw_free =      snd_cmipci_hw_free,
1702         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1703         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1704         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1705 };
1706
1707 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1708         .open =         snd_cmipci_playback_spdif_open,
1709         .close =        snd_cmipci_playback_spdif_close,
1710         .ioctl =        snd_pcm_lib_ioctl,
1711         .hw_params =    snd_cmipci_hw_params,
1712         .hw_free =      snd_cmipci_playback_hw_free,
1713         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1714         .trigger =      snd_cmipci_playback_trigger,
1715         .pointer =      snd_cmipci_playback_pointer,
1716 };
1717
1718 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1719         .open =         snd_cmipci_capture_spdif_open,
1720         .close =        snd_cmipci_capture_spdif_close,
1721         .ioctl =        snd_pcm_lib_ioctl,
1722         .hw_params =    snd_cmipci_hw_params,
1723         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1724         .prepare =      snd_cmipci_capture_spdif_prepare,
1725         .trigger =      snd_cmipci_capture_trigger,
1726         .pointer =      snd_cmipci_capture_pointer,
1727 };
1728
1729
1730 /*
1731  */
1732
1733 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1734 {
1735         struct snd_pcm *pcm;
1736         int err;
1737
1738         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1739         if (err < 0)
1740                 return err;
1741
1742         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1743         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1744
1745         pcm->private_data = cm;
1746         pcm->info_flags = 0;
1747         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1748         cm->pcm = pcm;
1749
1750         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1751                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1752
1753         return 0;
1754 }
1755
1756 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1757 {
1758         struct snd_pcm *pcm;
1759         int err;
1760
1761         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1762         if (err < 0)
1763                 return err;
1764
1765         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1766
1767         pcm->private_data = cm;
1768         pcm->info_flags = 0;
1769         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1770         cm->pcm2 = pcm;
1771
1772         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1773                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1774
1775         return 0;
1776 }
1777
1778 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1779 {
1780         struct snd_pcm *pcm;
1781         int err;
1782
1783         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1784         if (err < 0)
1785                 return err;
1786
1787         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1788         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1789
1790         pcm->private_data = cm;
1791         pcm->info_flags = 0;
1792         strcpy(pcm->name, "C-Media PCI IEC958");
1793         cm->pcm_spdif = pcm;
1794
1795         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1796                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1797
1798         return 0;
1799 }
1800
1801 /*
1802  * mixer interface:
1803  * - CM8338/8738 has a compatible mixer interface with SB16, but
1804  *   lack of some elements like tone control, i/o gain and AGC.
1805  * - Access to native registers:
1806  *   - A 3D switch
1807  *   - Output mute switches
1808  */
1809
1810 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1811 {
1812         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1813         outb(data, s->iobase + CM_REG_SB16_DATA);
1814 }
1815
1816 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1817 {
1818         unsigned char v;
1819
1820         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1821         v = inb(s->iobase + CM_REG_SB16_DATA);
1822         return v;
1823 }
1824
1825 /*
1826  * general mixer element
1827  */
1828 struct cmipci_sb_reg {
1829         unsigned int left_reg, right_reg;
1830         unsigned int left_shift, right_shift;
1831         unsigned int mask;
1832         unsigned int invert: 1;
1833         unsigned int stereo: 1;
1834 };
1835
1836 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1837  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1838
1839 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1840 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1841   .info = snd_cmipci_info_volume, \
1842   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1843   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1844 }
1845
1846 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1847 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1848 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1849 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1850
1851 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1852 {
1853         r->left_reg = val & 0xff;
1854         r->right_reg = (val >> 8) & 0xff;
1855         r->left_shift = (val >> 16) & 0x07;
1856         r->right_shift = (val >> 19) & 0x07;
1857         r->invert = (val >> 22) & 1;
1858         r->stereo = (val >> 23) & 1;
1859         r->mask = (val >> 24) & 0xff;
1860 }
1861
1862 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1863                                   struct snd_ctl_elem_info *uinfo)
1864 {
1865         struct cmipci_sb_reg reg;
1866
1867         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1868         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1869         uinfo->count = reg.stereo + 1;
1870         uinfo->value.integer.min = 0;
1871         uinfo->value.integer.max = reg.mask;
1872         return 0;
1873 }
1874
1875 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1876                                  struct snd_ctl_elem_value *ucontrol)
1877 {
1878         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1879         struct cmipci_sb_reg reg;
1880         int val;
1881
1882         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1883         spin_lock_irq(&cm->reg_lock);
1884         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1885         if (reg.invert)
1886                 val = reg.mask - val;
1887         ucontrol->value.integer.value[0] = val;
1888         if (reg.stereo) {
1889                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1890                 if (reg.invert)
1891                         val = reg.mask - val;
1892                  ucontrol->value.integer.value[1] = val;
1893         }
1894         spin_unlock_irq(&cm->reg_lock);
1895         return 0;
1896 }
1897
1898 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1899                                  struct snd_ctl_elem_value *ucontrol)
1900 {
1901         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1902         struct cmipci_sb_reg reg;
1903         int change;
1904         int left, right, oleft, oright;
1905
1906         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1907         left = ucontrol->value.integer.value[0] & reg.mask;
1908         if (reg.invert)
1909                 left = reg.mask - left;
1910         left <<= reg.left_shift;
1911         if (reg.stereo) {
1912                 right = ucontrol->value.integer.value[1] & reg.mask;
1913                 if (reg.invert)
1914                         right = reg.mask - right;
1915                 right <<= reg.right_shift;
1916         } else
1917                 right = 0;
1918         spin_lock_irq(&cm->reg_lock);
1919         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1920         left |= oleft & ~(reg.mask << reg.left_shift);
1921         change = left != oleft;
1922         if (reg.stereo) {
1923                 if (reg.left_reg != reg.right_reg) {
1924                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
1925                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1926                 } else
1927                         oright = left;
1928                 right |= oright & ~(reg.mask << reg.right_shift);
1929                 change |= right != oright;
1930                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1931         } else
1932                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1933         spin_unlock_irq(&cm->reg_lock);
1934         return change;
1935 }
1936
1937 /*
1938  * input route (left,right) -> (left,right)
1939  */
1940 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1941 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1942   .info = snd_cmipci_info_input_sw, \
1943   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1944   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1945 }
1946
1947 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1948                                     struct snd_ctl_elem_info *uinfo)
1949 {
1950         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1951         uinfo->count = 4;
1952         uinfo->value.integer.min = 0;
1953         uinfo->value.integer.max = 1;
1954         return 0;
1955 }
1956
1957 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1958                                    struct snd_ctl_elem_value *ucontrol)
1959 {
1960         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1961         struct cmipci_sb_reg reg;
1962         int val1, val2;
1963
1964         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1965         spin_lock_irq(&cm->reg_lock);
1966         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1967         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1968         spin_unlock_irq(&cm->reg_lock);
1969         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1970         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1971         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1972         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1973         return 0;
1974 }
1975
1976 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1977                                    struct snd_ctl_elem_value *ucontrol)
1978 {
1979         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1980         struct cmipci_sb_reg reg;
1981         int change;
1982         int val1, val2, oval1, oval2;
1983
1984         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1985         spin_lock_irq(&cm->reg_lock);
1986         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1987         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1988         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1989         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1990         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1991         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1992         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1993         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1994         change = val1 != oval1 || val2 != oval2;
1995         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1996         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1997         spin_unlock_irq(&cm->reg_lock);
1998         return change;
1999 }
2000
2001 /*
2002  * native mixer switches/volumes
2003  */
2004
2005 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2006 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2007   .info = snd_cmipci_info_native_mixer, \
2008   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2009   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2010 }
2011
2012 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2014   .info = snd_cmipci_info_native_mixer, \
2015   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2016   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2017 }
2018
2019 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2021   .info = snd_cmipci_info_native_mixer, \
2022   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2023   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2024 }
2025
2026 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2027 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2028   .info = snd_cmipci_info_native_mixer, \
2029   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2030   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2031 }
2032
2033 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2034                                         struct snd_ctl_elem_info *uinfo)
2035 {
2036         struct cmipci_sb_reg reg;
2037
2038         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2039         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2040         uinfo->count = reg.stereo + 1;
2041         uinfo->value.integer.min = 0;
2042         uinfo->value.integer.max = reg.mask;
2043         return 0;
2044
2045 }
2046
2047 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2048                                        struct snd_ctl_elem_value *ucontrol)
2049 {
2050         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2051         struct cmipci_sb_reg reg;
2052         unsigned char oreg, val;
2053
2054         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2055         spin_lock_irq(&cm->reg_lock);
2056         oreg = inb(cm->iobase + reg.left_reg);
2057         val = (oreg >> reg.left_shift) & reg.mask;
2058         if (reg.invert)
2059                 val = reg.mask - val;
2060         ucontrol->value.integer.value[0] = val;
2061         if (reg.stereo) {
2062                 val = (oreg >> reg.right_shift) & reg.mask;
2063                 if (reg.invert)
2064                         val = reg.mask - val;
2065                 ucontrol->value.integer.value[1] = val;
2066         }
2067         spin_unlock_irq(&cm->reg_lock);
2068         return 0;
2069 }
2070
2071 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2072                                        struct snd_ctl_elem_value *ucontrol)
2073 {
2074         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2075         struct cmipci_sb_reg reg;
2076         unsigned char oreg, nreg, val;
2077
2078         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2079         spin_lock_irq(&cm->reg_lock);
2080         oreg = inb(cm->iobase + reg.left_reg);
2081         val = ucontrol->value.integer.value[0] & reg.mask;
2082         if (reg.invert)
2083                 val = reg.mask - val;
2084         nreg = oreg & ~(reg.mask << reg.left_shift);
2085         nreg |= (val << reg.left_shift);
2086         if (reg.stereo) {
2087                 val = ucontrol->value.integer.value[1] & reg.mask;
2088                 if (reg.invert)
2089                         val = reg.mask - val;
2090                 nreg &= ~(reg.mask << reg.right_shift);
2091                 nreg |= (val << reg.right_shift);
2092         }
2093         outb(nreg, cm->iobase + reg.left_reg);
2094         spin_unlock_irq(&cm->reg_lock);
2095         return (nreg != oreg);
2096 }
2097
2098 /*
2099  * special case - check mixer sensitivity
2100  */
2101 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2102                                                  struct snd_ctl_elem_value *ucontrol)
2103 {
2104         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2105         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2106 }
2107
2108 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2109                                                  struct snd_ctl_elem_value *ucontrol)
2110 {
2111         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2112         if (cm->mixer_insensitive) {
2113                 /* ignored */
2114                 return 0;
2115         }
2116         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2117 }
2118
2119
2120 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2121         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2122         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2123         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2124         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2125         { /* switch with sensitivity */
2126                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2127                 .name = "PCM Playback Switch",
2128                 .info = snd_cmipci_info_native_mixer,
2129                 .get = snd_cmipci_get_native_mixer_sensitive,
2130                 .put = snd_cmipci_put_native_mixer_sensitive,
2131                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2132         },
2133         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2134         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2135         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2136         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2137         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2138         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2139         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2140         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2141         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2142         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2143         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2144         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2145         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2146         CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2147         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2148         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2149         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2150         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2151         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2152         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2153         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2154         CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2155         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2156 };
2157
2158 /*
2159  * other switches
2160  */
2161
2162 struct cmipci_switch_args {
2163         int reg;                /* register index */
2164         unsigned int mask;      /* mask bits */
2165         unsigned int mask_on;   /* mask bits to turn on */
2166         unsigned int is_byte: 1;                /* byte access? */
2167         unsigned int ac3_sensitive: 1;  /* access forbidden during
2168                                          * non-audio operation?
2169                                          */
2170 };
2171
2172 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2173
2174 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2175                                    struct snd_ctl_elem_value *ucontrol,
2176                                    struct cmipci_switch_args *args)
2177 {
2178         unsigned int val;
2179         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2180
2181         spin_lock_irq(&cm->reg_lock);
2182         if (args->ac3_sensitive && cm->mixer_insensitive) {
2183                 ucontrol->value.integer.value[0] = 0;
2184                 spin_unlock_irq(&cm->reg_lock);
2185                 return 0;
2186         }
2187         if (args->is_byte)
2188                 val = inb(cm->iobase + args->reg);
2189         else
2190                 val = snd_cmipci_read(cm, args->reg);
2191         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2192         spin_unlock_irq(&cm->reg_lock);
2193         return 0;
2194 }
2195
2196 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2197                                   struct snd_ctl_elem_value *ucontrol)
2198 {
2199         struct cmipci_switch_args *args;
2200         args = (struct cmipci_switch_args *)kcontrol->private_value;
2201         snd_assert(args != NULL, return -EINVAL);
2202         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2203 }
2204
2205 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2206                                    struct snd_ctl_elem_value *ucontrol,
2207                                    struct cmipci_switch_args *args)
2208 {
2209         unsigned int val;
2210         int change;
2211         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2212
2213         spin_lock_irq(&cm->reg_lock);
2214         if (args->ac3_sensitive && cm->mixer_insensitive) {
2215                 /* ignored */
2216                 spin_unlock_irq(&cm->reg_lock);
2217                 return 0;
2218         }
2219         if (args->is_byte)
2220                 val = inb(cm->iobase + args->reg);
2221         else
2222                 val = snd_cmipci_read(cm, args->reg);
2223         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2224                         args->mask_on : (args->mask & ~args->mask_on));
2225         if (change) {
2226                 val &= ~args->mask;
2227                 if (ucontrol->value.integer.value[0])
2228                         val |= args->mask_on;
2229                 else
2230                         val |= (args->mask & ~args->mask_on);
2231                 if (args->is_byte)
2232                         outb((unsigned char)val, cm->iobase + args->reg);
2233                 else
2234                         snd_cmipci_write(cm, args->reg, val);
2235         }
2236         spin_unlock_irq(&cm->reg_lock);
2237         return change;
2238 }
2239
2240 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2241                                   struct snd_ctl_elem_value *ucontrol)
2242 {
2243         struct cmipci_switch_args *args;
2244         args = (struct cmipci_switch_args *)kcontrol->private_value;
2245         snd_assert(args != NULL, return -EINVAL);
2246         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2247 }
2248
2249 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2250 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2251   .reg = xreg, \
2252   .mask = xmask, \
2253   .mask_on = xmask_on, \
2254   .is_byte = xis_byte, \
2255   .ac3_sensitive = xac3, \
2256 }
2257
2258 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2259         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2260
2261 #if 0 /* these will be controlled in pcm device */
2262 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2263 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2264 #endif
2265 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2266 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2267 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2268 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2269 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2270 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2271 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2272 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2273 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2274 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2275 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2276 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2277 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2278 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2279 #if CM_CH_PLAY == 1
2280 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2281 #else
2282 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2283 #endif
2284 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2285 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2286 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2287 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2288 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2289
2290 #define DEFINE_SWITCH(sname, stype, sarg) \
2291 { .name = sname, \
2292   .iface = stype, \
2293   .info = snd_cmipci_uswitch_info, \
2294   .get = snd_cmipci_uswitch_get, \
2295   .put = snd_cmipci_uswitch_put, \
2296   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2297 }
2298
2299 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2300 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2301
2302
2303 /*
2304  * callbacks for spdif output switch
2305  * needs toggle two registers..
2306  */
2307 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2308                                         struct snd_ctl_elem_value *ucontrol)
2309 {
2310         int changed;
2311         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2312         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2313         return changed;
2314 }
2315
2316 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2317                                         struct snd_ctl_elem_value *ucontrol)
2318 {
2319         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2320         int changed;
2321         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2322         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2323         if (changed) {
2324                 if (ucontrol->value.integer.value[0]) {
2325                         if (chip->spdif_playback_avail)
2326                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2327                 } else {
2328                         if (chip->spdif_playback_avail)
2329                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2330                 }
2331         }
2332         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2333         return changed;
2334 }
2335
2336
2337 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2338                                         struct snd_ctl_elem_info *uinfo)
2339 {
2340         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2341         static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2342         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2343         uinfo->count = 1;
2344         uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2345         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2346                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2347         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2348         return 0;
2349 }
2350
2351 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2352 {
2353         unsigned int val;
2354         if (cm->chip_version >= 39) {
2355                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2356                 if (val & CM_LINE_AS_BASS)
2357                         return 2;
2358         }
2359         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2360         if (val & CM_SPK4)
2361                 return 1;
2362         return 0;
2363 }
2364
2365 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2366                                        struct snd_ctl_elem_value *ucontrol)
2367 {
2368         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2369
2370         spin_lock_irq(&cm->reg_lock);
2371         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2372         spin_unlock_irq(&cm->reg_lock);
2373         return 0;
2374 }
2375
2376 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2377                                        struct snd_ctl_elem_value *ucontrol)
2378 {
2379         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2380         int change;
2381
2382         spin_lock_irq(&cm->reg_lock);
2383         if (ucontrol->value.enumerated.item[0] == 2)
2384                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2385         else
2386                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2387         if (ucontrol->value.enumerated.item[0] == 1)
2388                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2389         else
2390                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2391         spin_unlock_irq(&cm->reg_lock);
2392         return change;
2393 }
2394
2395 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2396                                        struct snd_ctl_elem_info *uinfo)
2397 {
2398         static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2399         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2400         uinfo->count = 1;
2401         uinfo->value.enumerated.items = 2;
2402         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2403                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2404         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2405         return 0;
2406 }
2407
2408 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2409                                       struct snd_ctl_elem_value *ucontrol)
2410 {
2411         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2412         /* same bit as spdi_phase */
2413         spin_lock_irq(&cm->reg_lock);
2414         ucontrol->value.enumerated.item[0] =
2415                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2416         spin_unlock_irq(&cm->reg_lock);
2417         return 0;
2418 }
2419
2420 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2421                                       struct snd_ctl_elem_value *ucontrol)
2422 {
2423         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2424         int change;
2425
2426         spin_lock_irq(&cm->reg_lock);
2427         if (ucontrol->value.enumerated.item[0])
2428                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2429         else
2430                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2431         spin_unlock_irq(&cm->reg_lock);
2432         return change;
2433 }
2434
2435 /* both for CM8338/8738 */
2436 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2437         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2438         {
2439                 .name = "Line-In Mode",
2440                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2441                 .info = snd_cmipci_line_in_mode_info,
2442                 .get = snd_cmipci_line_in_mode_get,
2443                 .put = snd_cmipci_line_in_mode_put,
2444         },
2445 };
2446
2447 /* for non-multichannel chips */
2448 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2449 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2450
2451 /* only for CM8738 */
2452 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2453 #if 0 /* controlled in pcm device */
2454         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2455         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2456         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2457 #endif
2458         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2459         { .name = "IEC958 Output Switch",
2460           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2461           .info = snd_cmipci_uswitch_info,
2462           .get = snd_cmipci_spdout_enable_get,
2463           .put = snd_cmipci_spdout_enable_put,
2464         },
2465         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2466         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2467         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2468 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2469         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2470         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2471 };
2472
2473 /* only for model 033/037 */
2474 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2475         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2476         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2477         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2478 };
2479
2480 /* only for model 039 or later */
2481 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2482         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2483         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2484         {
2485                 .name = "Mic-In Mode",
2486                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2487                 .info = snd_cmipci_mic_in_mode_info,
2488                 .get = snd_cmipci_mic_in_mode_get,
2489                 .put = snd_cmipci_mic_in_mode_put,
2490         }
2491 };
2492
2493 /* card control switches */
2494 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2495         // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2496         DEFINE_CARD_SWITCH("Modem", modem),
2497 };
2498
2499
2500 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2501 {
2502         struct snd_card *card;
2503         struct snd_kcontrol_new *sw;
2504         struct snd_kcontrol *kctl;
2505         unsigned int idx;
2506         int err;
2507
2508         snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2509
2510         card = cm->card;
2511
2512         strcpy(card->mixername, "CMedia PCI");
2513
2514         spin_lock_irq(&cm->reg_lock);
2515         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2516         spin_unlock_irq(&cm->reg_lock);
2517
2518         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2519                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2520                         if (!strcmp(snd_cmipci_mixers[idx].name,
2521                                 "PCM Playback Volume"))
2522                                 continue;
2523                 }
2524                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2525                         return err;
2526         }
2527
2528         /* mixer switches */
2529         sw = snd_cmipci_mixer_switches;
2530         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2531                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2532                 if (err < 0)
2533                         return err;
2534         }
2535         if (! cm->can_multi_ch) {
2536                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2537                 if (err < 0)
2538                         return err;
2539         }
2540         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2541             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2542                 sw = snd_cmipci_8738_mixer_switches;
2543                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2544                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2545                         if (err < 0)
2546                                 return err;
2547                 }
2548                 if (cm->can_ac3_hw) {
2549                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2550                                 return err;
2551                         kctl->id.device = pcm_spdif_device;
2552                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2553                                 return err;
2554                         kctl->id.device = pcm_spdif_device;
2555                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2556                                 return err;
2557                         kctl->id.device = pcm_spdif_device;
2558                 }
2559                 if (cm->chip_version <= 37) {
2560                         sw = snd_cmipci_old_mixer_switches;
2561                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2562                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2563                                 if (err < 0)
2564                                         return err;
2565                         }
2566                 }
2567         }
2568         if (cm->chip_version >= 39) {
2569                 sw = snd_cmipci_extra_mixer_switches;
2570                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2571                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2572                         if (err < 0)
2573                                 return err;
2574                 }
2575         }
2576
2577         /* card switches */
2578         sw = snd_cmipci_control_switches;
2579         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2580                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2581                 if (err < 0)
2582                         return err;
2583         }
2584
2585         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2586                 struct snd_ctl_elem_id id;
2587                 struct snd_kcontrol *ctl;
2588                 memset(&id, 0, sizeof(id));
2589                 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2590                 strcpy(id.name, cm_saved_mixer[idx].name);
2591                 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2592                         cm->mixer_res_ctl[idx] = ctl;
2593         }
2594
2595         return 0;
2596 }
2597
2598
2599 /*
2600  * proc interface
2601  */
2602
2603 #ifdef CONFIG_PROC_FS
2604 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2605                                  struct snd_info_buffer *buffer)
2606 {
2607         struct cmipci *cm = entry->private_data;
2608         int i;
2609
2610         snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2611         for (i = 0; i < 0x40; i++) {
2612                 int v = inb(cm->iobase + i);
2613                 if (i % 4 == 0)
2614                         snd_iprintf(buffer, "%02x: ", i);
2615                 snd_iprintf(buffer, "%02x", v);
2616                 if (i % 4 == 3)
2617                         snd_iprintf(buffer, "\n");
2618                 else
2619                         snd_iprintf(buffer, " ");
2620         }
2621 }
2622
2623 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2624 {
2625         struct snd_info_entry *entry;
2626
2627         if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2628                 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2629 }
2630 #else /* !CONFIG_PROC_FS */
2631 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2632 #endif
2633
2634
2635 static struct pci_device_id snd_cmipci_ids[] = {
2636         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2637         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2638         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2639         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2640         {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2641         {0,},
2642 };
2643
2644
2645 /*
2646  * check chip version and capabilities
2647  * driver name is modified according to the chip model
2648  */
2649 static void __devinit query_chip(struct cmipci *cm)
2650 {
2651         unsigned int detect;
2652
2653         /* check reg 0Ch, bit 24-31 */
2654         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2655         if (! detect) {
2656                 /* check reg 08h, bit 24-28 */
2657                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2658                 switch (detect) {
2659                 case 0:
2660                         cm->chip_version = 33;
2661                         if (cm->do_soft_ac3)
2662                                 cm->can_ac3_sw = 1;
2663                         else
2664                                 cm->can_ac3_hw = 1;
2665                         break;
2666                 case 1:
2667                         cm->chip_version = 37;
2668                         cm->can_ac3_hw = 1;
2669                         break;
2670                 default:
2671                         cm->chip_version = 39;
2672                         cm->can_ac3_hw = 1;
2673                         break;
2674                 }
2675                 cm->max_channels = 2;
2676         } else {
2677                 if (detect & CM_CHIP_039) {
2678                         cm->chip_version = 39;
2679                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2680                                 cm->max_channels = 6;
2681                         else
2682                                 cm->max_channels = 4;
2683                 } else if (detect & CM_CHIP_8768) {
2684                         cm->chip_version = 68;
2685                         cm->max_channels = 8;
2686                 } else {
2687                         cm->chip_version = 55;
2688                         cm->max_channels = 6;
2689                 }
2690                 cm->can_ac3_hw = 1;
2691                 cm->can_multi_ch = 1;
2692         }
2693 }
2694
2695 #ifdef SUPPORT_JOYSTICK
2696 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2697 {
2698         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2699         struct gameport *gp;
2700         struct resource *r = NULL;
2701         int i, io_port = 0;
2702
2703         if (joystick_port[dev] == 0)
2704                 return -ENODEV;
2705
2706         if (joystick_port[dev] == 1) { /* auto-detect */
2707                 for (i = 0; ports[i]; i++) {
2708                         io_port = ports[i];
2709                         r = request_region(io_port, 1, "CMIPCI gameport");
2710                         if (r)
2711                                 break;
2712                 }
2713         } else {
2714                 io_port = joystick_port[dev];
2715                 r = request_region(io_port, 1, "CMIPCI gameport");
2716         }
2717
2718         if (!r) {
2719                 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2720                 return -EBUSY;
2721         }
2722
2723         cm->gameport = gp = gameport_allocate_port();
2724         if (!gp) {
2725                 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2726                 release_and_free_resource(r);
2727                 return -ENOMEM;
2728         }
2729         gameport_set_name(gp, "C-Media Gameport");
2730         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2731         gameport_set_dev_parent(gp, &cm->pci->dev);
2732         gp->io = io_port;
2733         gameport_set_port_data(gp, r);
2734
2735         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2736
2737         gameport_register_port(cm->gameport);
2738
2739         return 0;
2740 }
2741
2742 static void snd_cmipci_free_gameport(struct cmipci *cm)
2743 {
2744         if (cm->gameport) {
2745                 struct resource *r = gameport_get_port_data(cm->gameport);
2746
2747                 gameport_unregister_port(cm->gameport);
2748                 cm->gameport = NULL;
2749
2750                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2751                 release_and_free_resource(r);
2752         }
2753 }
2754 #else
2755 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2756 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2757 #endif
2758
2759 static int snd_cmipci_free(struct cmipci *cm)
2760 {
2761         if (cm->irq >= 0) {
2762                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2763                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2764                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2765                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2766                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2767                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2768                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2769
2770                 /* reset mixer */
2771                 snd_cmipci_mixer_write(cm, 0, 0);
2772
2773                 synchronize_irq(cm->irq);
2774
2775                 free_irq(cm->irq, cm);
2776         }
2777
2778         snd_cmipci_free_gameport(cm);
2779         pci_release_regions(cm->pci);
2780         pci_disable_device(cm->pci);
2781         kfree(cm);
2782         return 0;
2783 }
2784
2785 static int snd_cmipci_dev_free(struct snd_device *device)
2786 {
2787         struct cmipci *cm = device->device_data;
2788         return snd_cmipci_free(cm);
2789 }
2790
2791 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2792 {
2793         long iosynth;
2794         unsigned int val;
2795         struct snd_opl3 *opl3;
2796         int err;
2797
2798         if (!fm_port)
2799                 goto disable_fm;
2800
2801         if (cm->chip_version >= 39) {
2802                 /* first try FM regs in PCI port range */
2803                 iosynth = cm->iobase + CM_REG_FM_PCI;
2804                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2805                                       OPL3_HW_OPL3, 1, &opl3);
2806         } else {
2807                 err = -EIO;
2808         }
2809         if (err < 0) {
2810                 /* then try legacy ports */
2811                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2812                 iosynth = fm_port;
2813                 switch (iosynth) {
2814                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2815                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2816                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2817                 case 0x388: val |= CM_FMSEL_388; break;
2818                 default:
2819                         goto disable_fm;
2820                 }
2821                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2822                 /* enable FM */
2823                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2824
2825                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2826                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2827                         printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2828                                "skipping...\n", iosynth);
2829                         goto disable_fm;
2830                 }
2831         }
2832         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2833                 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2834                 return err;
2835         }
2836         return 0;
2837
2838  disable_fm:
2839         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2840         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2841         return 0;
2842 }
2843
2844 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2845                                        int dev, struct cmipci **rcmipci)
2846 {
2847         struct cmipci *cm;
2848         int err;
2849         static struct snd_device_ops ops = {
2850                 .dev_free =     snd_cmipci_dev_free,
2851         };
2852         unsigned int val;
2853         long iomidi;
2854         int integrated_midi = 0;
2855         int pcm_index, pcm_spdif_index;
2856         static struct pci_device_id intel_82437vx[] = {
2857                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2858                 { },
2859         };
2860
2861         *rcmipci = NULL;
2862
2863         if ((err = pci_enable_device(pci)) < 0)
2864                 return err;
2865
2866         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2867         if (cm == NULL) {
2868                 pci_disable_device(pci);
2869                 return -ENOMEM;
2870         }
2871
2872         spin_lock_init(&cm->reg_lock);
2873         mutex_init(&cm->open_mutex);
2874         cm->device = pci->device;
2875         cm->card = card;
2876         cm->pci = pci;
2877         cm->irq = -1;
2878         cm->channel[0].ch = 0;
2879         cm->channel[1].ch = 1;
2880         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2881
2882         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2883                 kfree(cm);
2884                 pci_disable_device(pci);
2885                 return err;
2886         }
2887         cm->iobase = pci_resource_start(pci, 0);
2888
2889         if (request_irq(pci->irq, snd_cmipci_interrupt,
2890                         IRQF_SHARED, card->driver, cm)) {
2891                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2892                 snd_cmipci_free(cm);
2893                 return -EBUSY;
2894         }
2895         cm->irq = pci->irq;
2896
2897         pci_set_master(cm->pci);
2898
2899         /*
2900          * check chip version, max channels and capabilities
2901          */
2902
2903         cm->chip_version = 0;
2904         cm->max_channels = 2;
2905         cm->do_soft_ac3 = soft_ac3[dev];
2906
2907         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2908             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2909                 query_chip(cm);
2910         /* added -MCx suffix for chip supporting multi-channels */
2911         if (cm->can_multi_ch)
2912                 sprintf(cm->card->driver + strlen(cm->card->driver),
2913                         "-MC%d", cm->max_channels);
2914         else if (cm->can_ac3_sw)
2915                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2916
2917         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2918         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2919
2920 #if CM_CH_PLAY == 1
2921         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
2922 #else
2923         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
2924 #endif
2925
2926         /* initialize codec registers */
2927         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
2928         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2929         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2930         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
2931         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2932
2933         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2934         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2935 #if CM_CH_PLAY == 1
2936         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2937 #else
2938         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2939 #endif
2940         /* Set Bus Master Request */
2941         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2942
2943         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2944         switch (pci->device) {
2945         case PCI_DEVICE_ID_CMEDIA_CM8738:
2946         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2947                 if (!pci_dev_present(intel_82437vx))
2948                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2949                 break;
2950         default:
2951                 break;
2952         }
2953
2954         sprintf(card->shortname, "C-Media %s", card->driver);
2955         if (cm->chip_version < 68) {
2956                 val = pci->device < 0x110 ? 8338 : 8738;
2957                 sprintf(card->longname,
2958                         "C-Media CMI%d (model %d) at 0x%lx, irq %i",
2959                         val, cm->chip_version, cm->iobase, cm->irq);
2960         } else {
2961                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
2962                 case 0:
2963                         val = 8769;
2964                         break;
2965                 case 2:
2966                         val = 8762;
2967                         break;
2968                 default:
2969                         switch ((pci->subsystem_vendor << 16) |
2970                                 pci->subsystem_device) {
2971                         case 0x13f69761:
2972                         case 0x584d3741:
2973                         case 0x584d3751:
2974                         case 0x584d3761:
2975                         case 0x584d3771:
2976                         case 0x72848384:
2977                                 val = 8770;
2978                                 break;
2979                         default:
2980                                 val = 8768;
2981                                 break;
2982                         }
2983                 }
2984                 sprintf(card->longname, "C-Media CMI%d at 0x%lx, irq %i",
2985                         val, cm->iobase, cm->irq);
2986         }
2987
2988         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2989                 snd_cmipci_free(cm);
2990                 return err;
2991         }
2992
2993         if (cm->chip_version >= 39) {
2994                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
2995                 if (val != 0x00 && val != 0xff) {
2996                         iomidi = cm->iobase + CM_REG_MPU_PCI;
2997                         integrated_midi = 1;
2998                 }
2999         }
3000         if (!integrated_midi) {
3001                 val = 0;
3002                 iomidi = mpu_port[dev];
3003                 switch (iomidi) {
3004                 case 0x320: val = CM_VMPU_320; break;
3005                 case 0x310: val = CM_VMPU_310; break;
3006                 case 0x300: val = CM_VMPU_300; break;
3007                 case 0x330: val = CM_VMPU_330; break;
3008                 default:
3009                             iomidi = 0; break;
3010                 }
3011                 if (iomidi > 0) {
3012                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3013                         /* enable UART */
3014                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3015                         if (inb(iomidi + 1) == 0xff) {
3016                                 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3017                                            " at %#lx\n", iomidi);
3018                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3019                                                      CM_UART_EN);
3020                                 iomidi = 0;
3021                         }
3022                 }
3023         }
3024
3025         if (cm->chip_version < 68) {
3026                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3027                 if (err < 0)
3028                         return err;
3029         }
3030
3031         /* reset mixer */
3032         snd_cmipci_mixer_write(cm, 0, 0);
3033
3034         snd_cmipci_proc_init(cm);
3035
3036         /* create pcm devices */
3037         pcm_index = pcm_spdif_index = 0;
3038         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3039                 return err;
3040         pcm_index++;
3041         if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3042                 return err;
3043         pcm_index++;
3044         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3045                 pcm_spdif_index = pcm_index;
3046                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3047                         return err;
3048         }
3049
3050         /* create mixer interface & switches */
3051         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3052                 return err;
3053
3054         if (iomidi > 0) {
3055                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3056                                                iomidi,
3057                                                (integrated_midi ?
3058                                                 MPU401_INFO_INTEGRATED : 0),
3059                                                cm->irq, 0, &cm->rmidi)) < 0) {
3060                         printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3061                 }
3062         }
3063
3064 #ifdef USE_VAR48KRATE
3065         for (val = 0; val < ARRAY_SIZE(rates); val++)
3066                 snd_cmipci_set_pll(cm, rates[val], val);
3067
3068         /*
3069          * (Re-)Enable external switch spdo_48k
3070          */
3071         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3072 #endif /* USE_VAR48KRATE */
3073
3074         if (snd_cmipci_create_gameport(cm, dev) < 0)
3075                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3076
3077         snd_card_set_dev(card, &pci->dev);
3078
3079         *rcmipci = cm;
3080         return 0;
3081 }
3082
3083 /*
3084  */
3085
3086 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3087
3088 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3089                                       const struct pci_device_id *pci_id)
3090 {
3091         static int dev;
3092         struct snd_card *card;
3093         struct cmipci *cm;
3094         int err;
3095
3096         if (dev >= SNDRV_CARDS)
3097                 return -ENODEV;
3098         if (! enable[dev]) {
3099                 dev++;
3100                 return -ENOENT;
3101         }
3102
3103         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3104         if (card == NULL)
3105                 return -ENOMEM;
3106
3107         switch (pci->device) {
3108         case PCI_DEVICE_ID_CMEDIA_CM8738:
3109         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3110                 strcpy(card->driver, "CMI8738");
3111                 break;
3112         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3113         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3114                 strcpy(card->driver, "CMI8338");
3115                 break;
3116         default:
3117                 strcpy(card->driver, "CMIPCI");
3118                 break;
3119         }
3120
3121         if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3122                 snd_card_free(card);
3123                 return err;
3124         }
3125         card->private_data = cm;
3126
3127         if ((err = snd_card_register(card)) < 0) {
3128                 snd_card_free(card);
3129                 return err;
3130         }
3131         pci_set_drvdata(pci, card);
3132         dev++;
3133         return 0;
3134
3135 }
3136
3137 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3138 {
3139         snd_card_free(pci_get_drvdata(pci));
3140         pci_set_drvdata(pci, NULL);
3141 }
3142
3143
3144 #ifdef CONFIG_PM
3145 /*
3146  * power management
3147  */
3148 static unsigned char saved_regs[] = {
3149         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3150         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3151         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3152         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3153         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3154 };
3155
3156 static unsigned char saved_mixers[] = {
3157         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3158         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3159         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3160         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3161         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3162         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3163         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3164         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3165 };
3166
3167 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3168 {
3169         struct snd_card *card = pci_get_drvdata(pci);
3170         struct cmipci *cm = card->private_data;
3171         int i;
3172
3173         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3174
3175         snd_pcm_suspend_all(cm->pcm);
3176         snd_pcm_suspend_all(cm->pcm2);
3177         snd_pcm_suspend_all(cm->pcm_spdif);
3178
3179         /* save registers */
3180         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3181                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3182         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3183                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3184
3185         /* disable ints */
3186         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3187
3188         pci_disable_device(pci);
3189         pci_save_state(pci);
3190         pci_set_power_state(pci, pci_choose_state(pci, state));
3191         return 0;
3192 }
3193
3194 static int snd_cmipci_resume(struct pci_dev *pci)
3195 {
3196         struct snd_card *card = pci_get_drvdata(pci);
3197         struct cmipci *cm = card->private_data;
3198         int i;
3199
3200         pci_set_power_state(pci, PCI_D0);
3201         pci_restore_state(pci);
3202         if (pci_enable_device(pci) < 0) {
3203                 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3204                        "disabling device\n");
3205                 snd_card_disconnect(card);
3206                 return -EIO;
3207         }
3208         pci_set_master(pci);
3209
3210         /* reset / initialize to a sane state */
3211         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3212         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3213         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3214         snd_cmipci_mixer_write(cm, 0, 0);
3215
3216         /* restore registers */
3217         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3218                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3219         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3220                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3221
3222         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3223         return 0;
3224 }
3225 #endif /* CONFIG_PM */
3226
3227 static struct pci_driver driver = {
3228         .name = "C-Media PCI",
3229         .id_table = snd_cmipci_ids,
3230         .probe = snd_cmipci_probe,
3231         .remove = __devexit_p(snd_cmipci_remove),
3232 #ifdef CONFIG_PM
3233         .suspend = snd_cmipci_suspend,
3234         .resume = snd_cmipci_resume,
3235 #endif
3236 };
3237
3238 static int __init alsa_card_cmipci_init(void)
3239 {
3240         return pci_register_driver(&driver);
3241 }
3242
3243 static void __exit alsa_card_cmipci_exit(void)
3244 {
3245         pci_unregister_driver(&driver);
3246 }
3247
3248 module_init(alsa_card_cmipci_init)
3249 module_exit(alsa_card_cmipci_exit)