1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
31 #include "e1000_mac.h"
32 #include "e1000_phy.h"
34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
37 static s32 igb_wait_autoneg(struct e1000_hw *hw);
39 /* Cable length tables */
40 static const u16 e1000_m88_cable_length_table[] =
41 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
43 static const u16 e1000_igp_2_cable_length_table[] =
44 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51 104, 109, 114, 118, 121, 124};
52 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53 (sizeof(e1000_igp_2_cable_length_table) / \
54 sizeof(e1000_igp_2_cable_length_table[0]))
57 * igb_check_reset_block - Check if PHY reset is blocked
58 * @hw: pointer to the HW structure
60 * Read the PHY management control register and check whether a PHY reset
61 * is blocked. If a reset is not blocked return 0, otherwise
62 * return E1000_BLK_PHY_RESET (12).
64 s32 igb_check_reset_block(struct e1000_hw *hw)
68 manc = rd32(E1000_MANC);
70 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
71 E1000_BLK_PHY_RESET : 0;
75 * igb_get_phy_id - Retrieve the PHY ID and revision
76 * @hw: pointer to the HW structure
78 * Reads the PHY registers and stores the PHY ID and possibly the PHY
79 * revision in the hardware structure.
81 s32 igb_get_phy_id(struct e1000_hw *hw)
83 struct e1000_phy_info *phy = &hw->phy;
87 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
91 phy->id = (u32)(phy_id << 16);
93 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
97 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
98 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
105 * igb_phy_reset_dsp - Reset PHY DSP
106 * @hw: pointer to the HW structure
108 * Reset the digital signal processor.
110 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
118 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
125 * igb_read_phy_reg_mdic - Read MDI control register
126 * @hw: pointer to the HW structure
127 * @offset: register offset to be read
128 * @data: pointer to the read data
130 * Reads the MDI control regsiter in the PHY at offset and stores the
131 * information read to data.
133 static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
135 struct e1000_phy_info *phy = &hw->phy;
139 if (offset > MAX_PHY_REG_ADDRESS) {
140 hw_dbg("PHY Address %d is out of range\n", offset);
141 ret_val = -E1000_ERR_PARAM;
146 * Set up Op-code, Phy Address, and register offset in the MDI
147 * Control register. The MAC will take care of interfacing with the
148 * PHY to retrieve the desired data.
150 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ));
154 wr32(E1000_MDIC, mdic);
157 * Poll the ready bit to see if the MDI read completed
158 * Increasing the time out as testing showed failures with
161 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
163 mdic = rd32(E1000_MDIC);
164 if (mdic & E1000_MDIC_READY)
167 if (!(mdic & E1000_MDIC_READY)) {
168 hw_dbg("MDI Read did not complete\n");
169 ret_val = -E1000_ERR_PHY;
172 if (mdic & E1000_MDIC_ERROR) {
173 hw_dbg("MDI Error\n");
174 ret_val = -E1000_ERR_PHY;
184 * igb_write_phy_reg_mdic - Write MDI control register
185 * @hw: pointer to the HW structure
186 * @offset: register offset to write to
187 * @data: data to write to register at offset
189 * Writes data to MDI control register in the PHY at offset.
191 static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
193 struct e1000_phy_info *phy = &hw->phy;
197 if (offset > MAX_PHY_REG_ADDRESS) {
198 hw_dbg("PHY Address %d is out of range\n", offset);
199 ret_val = -E1000_ERR_PARAM;
204 * Set up Op-code, Phy Address, and register offset in the MDI
205 * Control register. The MAC will take care of interfacing with the
206 * PHY to retrieve the desired data.
208 mdic = (((u32)data) |
209 (offset << E1000_MDIC_REG_SHIFT) |
210 (phy->addr << E1000_MDIC_PHY_SHIFT) |
211 (E1000_MDIC_OP_WRITE));
213 wr32(E1000_MDIC, mdic);
216 * Poll the ready bit to see if the MDI read completed
217 * Increasing the time out as testing showed failures with
220 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
222 mdic = rd32(E1000_MDIC);
223 if (mdic & E1000_MDIC_READY)
226 if (!(mdic & E1000_MDIC_READY)) {
227 hw_dbg("MDI Write did not complete\n");
228 ret_val = -E1000_ERR_PHY;
231 if (mdic & E1000_MDIC_ERROR) {
232 hw_dbg("MDI Error\n");
233 ret_val = -E1000_ERR_PHY;
242 * igb_read_phy_reg_igp - Read igp PHY register
243 * @hw: pointer to the HW structure
244 * @offset: register offset to be read
245 * @data: pointer to the read data
247 * Acquires semaphore, if necessary, then reads the PHY register at offset
248 * and storing the retrieved information in data. Release any acquired
249 * semaphores before exiting.
251 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
255 if (!(hw->phy.ops.acquire))
258 ret_val = hw->phy.ops.acquire(hw);
262 if (offset > MAX_PHY_MULTI_PAGE_REG) {
263 ret_val = igb_write_phy_reg_mdic(hw,
264 IGP01E1000_PHY_PAGE_SELECT,
267 hw->phy.ops.release(hw);
272 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
275 hw->phy.ops.release(hw);
282 * igb_write_phy_reg_igp - Write igp PHY register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to write to
285 * @data: data to write at register offset
287 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semaphores before exiting.
290 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
294 if (!(hw->phy.ops.acquire))
297 ret_val = hw->phy.ops.acquire(hw);
301 if (offset > MAX_PHY_MULTI_PAGE_REG) {
302 ret_val = igb_write_phy_reg_mdic(hw,
303 IGP01E1000_PHY_PAGE_SELECT,
306 hw->phy.ops.release(hw);
311 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
314 hw->phy.ops.release(hw);
321 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
322 * @hw: pointer to the HW structure
324 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
325 * and downshift values are set also.
327 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
329 struct e1000_phy_info *phy = &hw->phy;
333 if (phy->reset_disable) {
338 /* Enable CRS on TX. This must be set for half-duplex operation. */
339 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
343 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
347 * MDI/MDI-X = 0 (default)
348 * 0 - Auto for all speeds
351 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
353 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
357 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
360 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
363 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
367 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
373 * disable_polarity_correction = 0 (default)
374 * Automatic Correction for Reversed Cable Polarity
378 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
379 if (phy->disable_polarity_correction == 1)
380 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
382 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
386 if (phy->revision < E1000_REVISION_4) {
388 * Force TX_CLK in the Extended PHY Specific Control Register
391 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
396 phy_data |= M88E1000_EPSCR_TX_CLK_25;
398 if ((phy->revision == E1000_REVISION_2) &&
399 (phy->id == M88E1111_I_PHY_ID)) {
400 /* 82573L PHY - set the downshift counter to 5x. */
401 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
402 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
404 /* Configure Master and Slave downshift values */
405 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
406 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
407 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
408 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
410 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
416 /* Commit the changes. */
417 ret_val = igb_phy_sw_reset(hw);
419 hw_dbg("Error committing the PHY changes\n");
428 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
429 * @hw: pointer to the HW structure
431 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
434 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
436 struct e1000_phy_info *phy = &hw->phy;
440 if (phy->reset_disable) {
445 ret_val = phy->ops.reset(hw);
447 hw_dbg("Error resetting the PHY.\n");
451 /* Wait 15ms for MAC to configure PHY from NVM settings. */
455 * The NVM settings will configure LPLU in D3 for
458 if (phy->type == e1000_phy_igp) {
459 /* disable lplu d3 during driver init */
460 if (phy->ops.set_d3_lplu_state)
461 ret_val = phy->ops.set_d3_lplu_state(hw, false);
463 hw_dbg("Error Disabling LPLU D3\n");
468 /* disable lplu d0 during driver init */
469 ret_val = phy->ops.set_d0_lplu_state(hw, false);
471 hw_dbg("Error Disabling LPLU D0\n");
474 /* Configure mdi-mdix settings */
475 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
479 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
483 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
486 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
490 data |= IGP01E1000_PSCR_AUTO_MDIX;
493 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
497 /* set auto-master slave resolution settings */
498 if (hw->mac.autoneg) {
500 * when autonegotiation advertisement is only 1000Mbps then we
501 * should disable SmartSpeed and enable Auto MasterSlave
502 * resolution as hardware default.
504 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
505 /* Disable SmartSpeed */
506 ret_val = phy->ops.read_reg(hw,
507 IGP01E1000_PHY_PORT_CONFIG,
512 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
513 ret_val = phy->ops.write_reg(hw,
514 IGP01E1000_PHY_PORT_CONFIG,
519 /* Set auto Master/Slave resolution process */
520 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
524 data &= ~CR_1000T_MS_ENABLE;
525 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
530 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
534 /* load defaults for future use */
535 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
536 ((data & CR_1000T_MS_VALUE) ?
537 e1000_ms_force_master :
538 e1000_ms_force_slave) :
541 switch (phy->ms_type) {
542 case e1000_ms_force_master:
543 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
545 case e1000_ms_force_slave:
546 data |= CR_1000T_MS_ENABLE;
547 data &= ~(CR_1000T_MS_VALUE);
550 data &= ~CR_1000T_MS_ENABLE;
554 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
564 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
565 * @hw: pointer to the HW structure
567 * Performs initial bounds checking on autoneg advertisement parameter, then
568 * configure to advertise the full capability. Setup the PHY to autoneg
569 * and restart the negotiation process between the link partner. If
570 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
572 s32 igb_copper_link_autoneg(struct e1000_hw *hw)
574 struct e1000_phy_info *phy = &hw->phy;
579 * Perform some bounds checking on the autoneg advertisement
582 phy->autoneg_advertised &= phy->autoneg_mask;
585 * If autoneg_advertised is zero, we assume it was not defaulted
586 * by the calling code so we set to advertise full capability.
588 if (phy->autoneg_advertised == 0)
589 phy->autoneg_advertised = phy->autoneg_mask;
591 hw_dbg("Reconfiguring auto-neg advertisement params\n");
592 ret_val = igb_phy_setup_autoneg(hw);
594 hw_dbg("Error Setting up Auto-Negotiation\n");
597 hw_dbg("Restarting Auto-Neg\n");
600 * Restart auto-negotiation by setting the Auto Neg Enable bit and
601 * the Auto Neg Restart bit in the PHY control register.
603 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
607 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
608 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
613 * Does the user want to wait for Auto-Neg to complete here, or
614 * check at a later time (for example, callback routine).
616 if (phy->autoneg_wait_to_complete) {
617 ret_val = igb_wait_autoneg(hw);
619 hw_dbg("Error while waiting for "
620 "autoneg to complete\n");
625 hw->mac.get_link_status = true;
632 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
633 * @hw: pointer to the HW structure
635 * Reads the MII auto-neg advertisement register and/or the 1000T control
636 * register and if the PHY is already setup for auto-negotiation, then
637 * return successful. Otherwise, setup advertisement and flow control to
638 * the appropriate values for the wanted auto-negotiation.
640 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
642 struct e1000_phy_info *phy = &hw->phy;
644 u16 mii_autoneg_adv_reg;
645 u16 mii_1000t_ctrl_reg = 0;
647 phy->autoneg_advertised &= phy->autoneg_mask;
649 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
650 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
654 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
655 /* Read the MII 1000Base-T Control Register (Address 9). */
656 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
657 &mii_1000t_ctrl_reg);
663 * Need to parse both autoneg_advertised and fc and set up
664 * the appropriate PHY registers. First we will parse for
665 * autoneg_advertised software override. Since we can advertise
666 * a plethora of combinations, we need to check each bit
671 * First we clear all the 10/100 mb speed bits in the Auto-Neg
672 * Advertisement Register (Address 4) and the 1000 mb speed bits in
673 * the 1000Base-T Control Register (Address 9).
675 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
676 NWAY_AR_100TX_HD_CAPS |
677 NWAY_AR_10T_FD_CAPS |
678 NWAY_AR_10T_HD_CAPS);
679 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
681 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
683 /* Do we want to advertise 10 Mb Half Duplex? */
684 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
685 hw_dbg("Advertise 10mb Half duplex\n");
686 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
689 /* Do we want to advertise 10 Mb Full Duplex? */
690 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
691 hw_dbg("Advertise 10mb Full duplex\n");
692 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
695 /* Do we want to advertise 100 Mb Half Duplex? */
696 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
697 hw_dbg("Advertise 100mb Half duplex\n");
698 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
701 /* Do we want to advertise 100 Mb Full Duplex? */
702 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
703 hw_dbg("Advertise 100mb Full duplex\n");
704 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
707 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
708 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
709 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
711 /* Do we want to advertise 1000 Mb Full Duplex? */
712 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
713 hw_dbg("Advertise 1000mb Full duplex\n");
714 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
718 * Check for a software override of the flow control settings, and
719 * setup the PHY advertisement registers accordingly. If
720 * auto-negotiation is enabled, then software will have to set the
721 * "PAUSE" bits to the correct value in the Auto-Negotiation
722 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
725 * The possible values of the "fc" parameter are:
726 * 0: Flow control is completely disabled
727 * 1: Rx flow control is enabled (we can receive pause frames
728 * but not send pause frames).
729 * 2: Tx flow control is enabled (we can send pause frames
730 * but we do not support receiving pause frames).
731 * 3: Both Rx and TX flow control (symmetric) are enabled.
732 * other: No software override. The flow control configuration
733 * in the EEPROM is used.
735 switch (hw->fc.type) {
738 * Flow control (RX & TX) is completely disabled by a
739 * software over-ride.
741 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
743 case e1000_fc_rx_pause:
745 * RX Flow control is enabled, and TX Flow control is
746 * disabled, by a software over-ride.
748 * Since there really isn't a way to advertise that we are
749 * capable of RX Pause ONLY, we will advertise that we
750 * support both symmetric and asymmetric RX PAUSE. Later
751 * (in e1000_config_fc_after_link_up) we will disable the
752 * hw's ability to send PAUSE frames.
754 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
756 case e1000_fc_tx_pause:
758 * TX Flow control is enabled, and RX Flow control is
759 * disabled, by a software over-ride.
761 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
762 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
766 * Flow control (both RX and TX) is enabled by a software
769 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
772 hw_dbg("Flow control param set incorrectly\n");
773 ret_val = -E1000_ERR_CONFIG;
777 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
781 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
783 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
784 ret_val = phy->ops.write_reg(hw,
796 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
797 * @hw: pointer to the HW structure
799 * Calls the PHY setup function to force speed and duplex. Clears the
800 * auto-crossover to force MDI manually. Waits for link and returns
801 * successful if link up is successful, else -E1000_ERR_PHY (-2).
803 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
805 struct e1000_phy_info *phy = &hw->phy;
810 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
814 igb_phy_force_speed_duplex_setup(hw, &phy_data);
816 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
821 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
822 * forced whenever speed and duplex are forced.
824 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
828 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
829 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
831 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
835 hw_dbg("IGP PSCR: %X\n", phy_data);
839 if (phy->autoneg_wait_to_complete) {
840 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
842 ret_val = igb_phy_has_link(hw,
850 hw_dbg("Link taking longer than expected.\n");
853 ret_val = igb_phy_has_link(hw,
866 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
867 * @hw: pointer to the HW structure
869 * Calls the PHY setup function to force speed and duplex. Clears the
870 * auto-crossover to force MDI manually. Resets the PHY to commit the
871 * changes. If time expires while waiting for link up, we reset the DSP.
872 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
873 * successful completion, else return corresponding error code.
875 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
877 struct e1000_phy_info *phy = &hw->phy;
883 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
884 * forced whenever speed and duplex are forced.
886 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
890 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
891 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
895 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
897 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
901 igb_phy_force_speed_duplex_setup(hw, &phy_data);
903 /* Reset the phy to commit changes. */
904 phy_data |= MII_CR_RESET;
906 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
912 if (phy->autoneg_wait_to_complete) {
913 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
915 ret_val = igb_phy_has_link(hw,
924 * We didn't get link.
925 * Reset the DSP and cross our fingers.
927 ret_val = phy->ops.write_reg(hw,
928 M88E1000_PHY_PAGE_SELECT,
932 ret_val = igb_phy_reset_dsp(hw);
938 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
944 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
949 * Resetting the phy means we need to re-force TX_CLK in the
950 * Extended PHY Specific Control Register to 25MHz clock from
951 * the reset value of 2.5MHz.
953 phy_data |= M88E1000_EPSCR_TX_CLK_25;
954 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
959 * In addition, we must re-enable CRS on Tx for both half and full
962 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
966 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
967 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
974 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
975 * @hw: pointer to the HW structure
976 * @phy_ctrl: pointer to current value of PHY_CONTROL
978 * Forces speed and duplex on the PHY by doing the following: disable flow
979 * control, force speed/duplex on the MAC, disable auto speed detection,
980 * disable auto-negotiation, configure duplex, configure speed, configure
981 * the collision distance, write configuration to CTRL register. The
982 * caller must write to the PHY_CONTROL register for these settings to
985 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
988 struct e1000_mac_info *mac = &hw->mac;
991 /* Turn off flow control when forcing speed/duplex */
992 hw->fc.type = e1000_fc_none;
994 /* Force speed/duplex on the mac */
995 ctrl = rd32(E1000_CTRL);
996 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
997 ctrl &= ~E1000_CTRL_SPD_SEL;
999 /* Disable Auto Speed Detection */
1000 ctrl &= ~E1000_CTRL_ASDE;
1002 /* Disable autoneg on the phy */
1003 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1005 /* Forcing Full or Half Duplex? */
1006 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1007 ctrl &= ~E1000_CTRL_FD;
1008 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1009 hw_dbg("Half Duplex\n");
1011 ctrl |= E1000_CTRL_FD;
1012 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1013 hw_dbg("Full Duplex\n");
1016 /* Forcing 10mb or 100mb? */
1017 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1018 ctrl |= E1000_CTRL_SPD_100;
1019 *phy_ctrl |= MII_CR_SPEED_100;
1020 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1021 hw_dbg("Forcing 100mb\n");
1023 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1024 *phy_ctrl |= MII_CR_SPEED_10;
1025 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1026 hw_dbg("Forcing 10mb\n");
1029 igb_config_collision_dist(hw);
1031 wr32(E1000_CTRL, ctrl);
1035 * igb_set_d3_lplu_state - Sets low power link up state for D3
1036 * @hw: pointer to the HW structure
1037 * @active: boolean used to enable/disable lplu
1039 * Success returns 0, Failure returns 1
1041 * The low power link up (lplu) state is set to the power management level D3
1042 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1043 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1044 * is used during Dx states where the power conservation is most important.
1045 * During driver activity, SmartSpeed should be enabled so performance is
1048 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1050 struct e1000_phy_info *phy = &hw->phy;
1054 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1059 data &= ~IGP02E1000_PM_D3_LPLU;
1060 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1065 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1066 * during Dx states where the power conservation is most
1067 * important. During driver activity we should enable
1068 * SmartSpeed, so performance is maintained.
1070 if (phy->smart_speed == e1000_smart_speed_on) {
1071 ret_val = phy->ops.read_reg(hw,
1072 IGP01E1000_PHY_PORT_CONFIG,
1077 data |= IGP01E1000_PSCFR_SMART_SPEED;
1078 ret_val = phy->ops.write_reg(hw,
1079 IGP01E1000_PHY_PORT_CONFIG,
1083 } else if (phy->smart_speed == e1000_smart_speed_off) {
1084 ret_val = phy->ops.read_reg(hw,
1085 IGP01E1000_PHY_PORT_CONFIG,
1090 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1091 ret_val = phy->ops.write_reg(hw,
1092 IGP01E1000_PHY_PORT_CONFIG,
1097 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1098 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1099 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1100 data |= IGP02E1000_PM_D3_LPLU;
1101 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1106 /* When LPLU is enabled, we should disable SmartSpeed */
1107 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1112 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1113 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1122 * igb_check_downshift - Checks whether a downshift in speed occured
1123 * @hw: pointer to the HW structure
1125 * Success returns 0, Failure returns 1
1127 * A downshift is detected by querying the PHY link health.
1129 s32 igb_check_downshift(struct e1000_hw *hw)
1131 struct e1000_phy_info *phy = &hw->phy;
1133 u16 phy_data, offset, mask;
1135 switch (phy->type) {
1137 case e1000_phy_gg82563:
1138 offset = M88E1000_PHY_SPEC_STATUS;
1139 mask = M88E1000_PSSR_DOWNSHIFT;
1141 case e1000_phy_igp_2:
1143 case e1000_phy_igp_3:
1144 offset = IGP01E1000_PHY_LINK_HEALTH;
1145 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1148 /* speed downshift not supported */
1149 phy->speed_downgraded = false;
1154 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1157 phy->speed_downgraded = (phy_data & mask) ? true : false;
1164 * igb_check_polarity_m88 - Checks the polarity.
1165 * @hw: pointer to the HW structure
1167 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1169 * Polarity is determined based on the PHY specific status register.
1171 static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1173 struct e1000_phy_info *phy = &hw->phy;
1177 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1180 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1181 ? e1000_rev_polarity_reversed
1182 : e1000_rev_polarity_normal;
1188 * igb_check_polarity_igp - Checks the polarity.
1189 * @hw: pointer to the HW structure
1191 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1193 * Polarity is determined based on the PHY port status register, and the
1194 * current speed (since there is no polarity at 100Mbps).
1196 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1198 struct e1000_phy_info *phy = &hw->phy;
1200 u16 data, offset, mask;
1203 * Polarity is determined based on the speed of
1206 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1210 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1211 IGP01E1000_PSSR_SPEED_1000MBPS) {
1212 offset = IGP01E1000_PHY_PCS_INIT_REG;
1213 mask = IGP01E1000_PHY_POLARITY_MASK;
1216 * This really only applies to 10Mbps since
1217 * there is no polarity for 100Mbps (always 0).
1219 offset = IGP01E1000_PHY_PORT_STATUS;
1220 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1223 ret_val = phy->ops.read_reg(hw, offset, &data);
1226 phy->cable_polarity = (data & mask)
1227 ? e1000_rev_polarity_reversed
1228 : e1000_rev_polarity_normal;
1235 * igb_wait_autoneg - Wait for auto-neg compeletion
1236 * @hw: pointer to the HW structure
1238 * Waits for auto-negotiation to complete or for the auto-negotiation time
1239 * limit to expire, which ever happens first.
1241 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1246 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1247 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1248 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1251 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1254 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1260 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1267 * igb_phy_has_link - Polls PHY for link
1268 * @hw: pointer to the HW structure
1269 * @iterations: number of times to poll for link
1270 * @usec_interval: delay between polling attempts
1271 * @success: pointer to whether polling was successful or not
1273 * Polls the PHY status register for link, 'iterations' number of times.
1275 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1276 u32 usec_interval, bool *success)
1281 for (i = 0; i < iterations; i++) {
1283 * Some PHYs require the PHY_STATUS register to be read
1284 * twice due to the link bit being sticky. No harm doing
1285 * it across the board.
1287 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1290 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1293 if (phy_status & MII_SR_LINK_STATUS)
1295 if (usec_interval >= 1000)
1296 mdelay(usec_interval/1000);
1298 udelay(usec_interval);
1301 *success = (i < iterations) ? true : false;
1307 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1308 * @hw: pointer to the HW structure
1310 * Reads the PHY specific status register to retrieve the cable length
1311 * information. The cable length is determined by averaging the minimum and
1312 * maximum values to get the "average" cable length. The m88 PHY has four
1313 * possible cable length values, which are:
1314 * Register Value Cable Length
1318 * 3 110 - 140 meters
1321 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1323 struct e1000_phy_info *phy = &hw->phy;
1325 u16 phy_data, index;
1327 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1331 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1332 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1333 phy->min_cable_length = e1000_m88_cable_length_table[index];
1334 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1336 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1343 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1344 * @hw: pointer to the HW structure
1346 * The automatic gain control (agc) normalizes the amplitude of the
1347 * received signal, adjusting for the attenuation produced by the
1348 * cable. By reading the AGC registers, which represent the
1349 * combination of coarse and fine gain value, the value can be put
1350 * into a lookup table to obtain the approximate cable length
1353 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1355 struct e1000_phy_info *phy = &hw->phy;
1357 u16 phy_data, i, agc_value = 0;
1358 u16 cur_agc_index, max_agc_index = 0;
1359 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1360 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1361 {IGP02E1000_PHY_AGC_A,
1362 IGP02E1000_PHY_AGC_B,
1363 IGP02E1000_PHY_AGC_C,
1364 IGP02E1000_PHY_AGC_D};
1366 /* Read the AGC registers for all channels */
1367 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1368 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1373 * Getting bits 15:9, which represent the combination of
1374 * coarse and fine gain values. The result is a number
1375 * that can be put into the lookup table to obtain the
1376 * approximate cable length.
1378 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1379 IGP02E1000_AGC_LENGTH_MASK;
1381 /* Array index bound check. */
1382 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1383 (cur_agc_index == 0)) {
1384 ret_val = -E1000_ERR_PHY;
1388 /* Remove min & max AGC values from calculation. */
1389 if (e1000_igp_2_cable_length_table[min_agc_index] >
1390 e1000_igp_2_cable_length_table[cur_agc_index])
1391 min_agc_index = cur_agc_index;
1392 if (e1000_igp_2_cable_length_table[max_agc_index] <
1393 e1000_igp_2_cable_length_table[cur_agc_index])
1394 max_agc_index = cur_agc_index;
1396 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1399 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1400 e1000_igp_2_cable_length_table[max_agc_index]);
1401 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1403 /* Calculate cable length with the error range of +/- 10 meters. */
1404 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1405 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1406 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1408 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1415 * igb_get_phy_info_m88 - Retrieve PHY information
1416 * @hw: pointer to the HW structure
1418 * Valid for only copper links. Read the PHY status register (sticky read)
1419 * to verify that link is up. Read the PHY special control register to
1420 * determine the polarity and 10base-T extended distance. Read the PHY
1421 * special status register to determine MDI/MDIx and current speed. If
1422 * speed is 1000, then determine cable length, local and remote receiver.
1424 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1426 struct e1000_phy_info *phy = &hw->phy;
1431 if (phy->media_type != e1000_media_type_copper) {
1432 hw_dbg("Phy info is only valid for copper media\n");
1433 ret_val = -E1000_ERR_CONFIG;
1437 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1442 hw_dbg("Phy info is only valid if link is up\n");
1443 ret_val = -E1000_ERR_CONFIG;
1447 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1451 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1454 ret_val = igb_check_polarity_m88(hw);
1458 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1462 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1464 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1465 ret_val = phy->ops.get_cable_length(hw);
1469 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1473 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1474 ? e1000_1000t_rx_status_ok
1475 : e1000_1000t_rx_status_not_ok;
1477 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1478 ? e1000_1000t_rx_status_ok
1479 : e1000_1000t_rx_status_not_ok;
1481 /* Set values to "undefined" */
1482 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1483 phy->local_rx = e1000_1000t_rx_status_undefined;
1484 phy->remote_rx = e1000_1000t_rx_status_undefined;
1492 * igb_get_phy_info_igp - Retrieve igp PHY information
1493 * @hw: pointer to the HW structure
1495 * Read PHY status to determine if link is up. If link is up, then
1496 * set/determine 10base-T extended distance and polarity correction. Read
1497 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1498 * determine on the cable length, local and remote receiver.
1500 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1502 struct e1000_phy_info *phy = &hw->phy;
1507 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1512 hw_dbg("Phy info is only valid if link is up\n");
1513 ret_val = -E1000_ERR_CONFIG;
1517 phy->polarity_correction = true;
1519 ret_val = igb_check_polarity_igp(hw);
1523 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1527 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1529 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1530 IGP01E1000_PSSR_SPEED_1000MBPS) {
1531 ret_val = phy->ops.get_cable_length(hw);
1535 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
1539 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1540 ? e1000_1000t_rx_status_ok
1541 : e1000_1000t_rx_status_not_ok;
1543 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1544 ? e1000_1000t_rx_status_ok
1545 : e1000_1000t_rx_status_not_ok;
1547 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1548 phy->local_rx = e1000_1000t_rx_status_undefined;
1549 phy->remote_rx = e1000_1000t_rx_status_undefined;
1557 * igb_phy_sw_reset - PHY software reset
1558 * @hw: pointer to the HW structure
1560 * Does a software reset of the PHY by reading the PHY control register and
1561 * setting/write the control register reset bit to the PHY.
1563 s32 igb_phy_sw_reset(struct e1000_hw *hw)
1568 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1572 phy_ctrl |= MII_CR_RESET;
1573 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1584 * igb_phy_hw_reset - PHY hardware reset
1585 * @hw: pointer to the HW structure
1587 * Verify the reset block is not blocking us from resetting. Acquire
1588 * semaphore (if necessary) and read/set/write the device control reset
1589 * bit in the PHY. Wait the appropriate delay time for the device to
1590 * reset and relase the semaphore (if necessary).
1592 s32 igb_phy_hw_reset(struct e1000_hw *hw)
1594 struct e1000_phy_info *phy = &hw->phy;
1598 ret_val = igb_check_reset_block(hw);
1604 ret_val = phy->ops.acquire(hw);
1608 ctrl = rd32(E1000_CTRL);
1609 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1612 udelay(phy->reset_delay_us);
1614 wr32(E1000_CTRL, ctrl);
1619 phy->ops.release(hw);
1621 ret_val = phy->ops.get_cfg_done(hw);
1628 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
1629 * @hw: pointer to the HW structure
1631 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1633 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1635 hw_dbg("Running IGP 3 PHY init script\n");
1637 /* PHY init IGP 3 */
1638 /* Enable rise/fall, 10-mode work in class-A */
1639 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
1640 /* Remove all caps from Replica path filter */
1641 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
1642 /* Bias trimming for ADC, AFE and Driver (Default) */
1643 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
1644 /* Increase Hybrid poly bias */
1645 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
1646 /* Add 4% to TX amplitude in Giga mode */
1647 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
1648 /* Disable trimming (TTT) */
1649 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
1650 /* Poly DC correction to 94.6% + 2% for all channels */
1651 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
1652 /* ABS DC correction to 95.9% */
1653 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
1654 /* BG temp curve trim */
1655 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
1656 /* Increasing ADC OPAMP stage 1 currents to max */
1657 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
1658 /* Force 1000 ( required for enabling PHY regs configuration) */
1659 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1660 /* Set upd_freq to 6 */
1661 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
1663 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
1664 /* Disable adaptive fixed FFE (Default) */
1665 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
1666 /* Enable FFE hysteresis */
1667 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
1668 /* Fixed FFE for short cable lengths */
1669 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
1670 /* Fixed FFE for medium cable lengths */
1671 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
1672 /* Fixed FFE for long cable lengths */
1673 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
1674 /* Enable Adaptive Clip Threshold */
1675 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
1676 /* AHT reset limit to 1 */
1677 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
1678 /* Set AHT master delay to 127 msec */
1679 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
1680 /* Set scan bits for AHT */
1681 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
1682 /* Set AHT Preset bits */
1683 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
1684 /* Change integ_factor of channel A to 3 */
1685 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
1686 /* Change prop_factor of channels BCD to 8 */
1687 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
1688 /* Change cg_icount + enable integbp for channels BCD */
1689 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
1691 * Change cg_icount + enable integbp + change prop_factor_master
1692 * to 8 for channel A
1694 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
1695 /* Disable AHT in Slave mode on channel A */
1696 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
1698 * Enable LPLU and disable AN to 1000 in non-D0a states,
1701 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
1702 /* Enable restart AN on an1000_dis change */
1703 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
1704 /* Enable wh_fifo read clock in 10/100 modes */
1705 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
1706 /* Restart AN, Speed selection is 1000 */
1707 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);