2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
63 return ath9k_hw_mac_usec(ah, clks);
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
84 return ath9k_hw_mac_clks(ah, usecs);
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
91 BUG_ON(timeout < AH_TIME_QUANTUM);
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94 if ((REG_READ(ah, reg) & mask) == val)
97 udelay(AH_TIME_QUANTUM);
100 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
123 struct ath9k_hw_capabilities *pCap = &ah->caps;
125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139 struct ath_rate_table *rates,
140 u32 frameLen, u16 rateix,
143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
146 kbps = rates->info[rateix].ratekbps;
151 switch (rates->info[rateix].phy) {
152 case WLAN_RC_PHY_CCK:
153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154 if (shortPreamble && rates->info[rateix].short_preamble)
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
159 case WLAN_RC_PHY_OFDM:
160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
184 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix);
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222 HT40_CHANNEL_CENTER_SHIFT : 15));
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
242 if (!AR_SREV_9100(ah))
243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
245 ah->hw_version.macRev = val & AR_SREV_REVISION;
247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248 ah->is_pciexpress = true;
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
264 return ath9k_hw_reverse_bits(val, 8);
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
273 if (AR_SREV_9100(ah))
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
293 u32 patternData[4] = { 0x55555555,
299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData);
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData);
328 REG_WRITE(ah, regAddr[i], regHold[i]);
335 static const char *ath9k_hw_devname(u16 devid)
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_clock_req = 0;
367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
369 ah->config.ht_enable = 1;
370 ah->config.ofdm_trig_low = 200;
371 ah->config.ofdm_trig_high = 500;
372 ah->config.cck_trig_high = 200;
373 ah->config.cck_trig_low = 100;
374 ah->config.enable_ani = 1;
375 ah->config.diversity_control = 0;
376 ah->config.antenna_switch_swap = 0;
378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
383 ah->config.intr_mitigation = true;
386 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
387 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
388 * This means we use it for all AR5416 devices, and the few
389 * minor PCI AR9280 devices out there.
391 * Serialization is required because these devices do not handle
392 * well the case of two concurrent reads/writes due to the latency
393 * involved. During one read/write another read/write can be issued
394 * on another CPU while the previous read/write may still be working
395 * on our hardware, if we hit this case the hardware poops in a loop.
396 * We prevent this by serializing reads and writes.
398 * This issue is not present on PCI-Express devices or pre-AR5416
399 * devices (legacy, 802.11abg).
401 if (num_possible_cpus() > 1)
402 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
405 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
410 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
412 DPRINTF(sc, ATH_DBG_FATAL,
413 "Cannot allocate memory for state block\n");
419 ah->hw_version.magic = AR5416_MAGIC;
420 ah->regulatory.country_code = CTRY_DEFAULT;
421 ah->hw_version.devid = devid;
422 ah->hw_version.subvendorid = 0;
425 if ((devid == AR5416_AR9100_DEVID))
426 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
427 if (!AR_SREV_9100(ah))
428 ah->ah_flags = AH_USE_EEPROM;
430 ah->regulatory.power_limit = MAX_RATE_POWER;
431 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
433 ah->diversity_control = ah->config.diversity_control;
434 ah->antenna_switch_swap =
435 ah->config.antenna_switch_swap;
436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
437 ah->beacon_interval = 100;
438 ah->enable_32kHz_clock = DONT_USE_32KHZ;
439 ah->slottime = (u32) -1;
440 ah->acktimeout = (u32) -1;
441 ah->ctstimeout = (u32) -1;
442 ah->globaltxtimeout = (u32) -1;
444 ah->gbeacon_rate = 0;
449 static int ath9k_hw_rfattach(struct ath_hw *ah)
451 bool rfStatus = false;
454 rfStatus = ath9k_hw_init_rf(ah, &ecode);
456 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
457 "RF setup failed, status: %u\n", ecode);
464 static int ath9k_hw_rf_claim(struct ath_hw *ah)
468 REG_WRITE(ah, AR_PHY(0), 0x00000007);
470 val = ath9k_hw_get_radiorev(ah);
471 switch (val & AR_RADIO_SREV_MAJOR) {
473 val = AR_RAD5133_SREV_MAJOR;
475 case AR_RAD5133_SREV_MAJOR:
476 case AR_RAD5122_SREV_MAJOR:
477 case AR_RAD2133_SREV_MAJOR:
478 case AR_RAD2122_SREV_MAJOR:
481 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
482 "Radio Chip Rev 0x%02X not supported\n",
483 val & AR_RADIO_SREV_MAJOR);
487 ah->hw_version.analog5GhzRev = val;
492 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
499 for (i = 0; i < 3; i++) {
500 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
502 ah->macaddr[2 * i] = eeval >> 8;
503 ah->macaddr[2 * i + 1] = eeval & 0xff;
505 if (sum == 0 || sum == 0xffff * 3)
506 return -EADDRNOTAVAIL;
511 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
515 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
516 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
518 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9280Modes_backoff_13db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
522 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
523 INIT_INI_ARRAY(&ah->iniModesRxGain,
524 ar9280Modes_backoff_23db_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
527 INIT_INI_ARRAY(&ah->iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
531 INIT_INI_ARRAY(&ah->iniModesRxGain,
532 ar9280Modes_original_rxgain_9280_2,
533 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
537 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
541 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
542 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
544 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
545 INIT_INI_ARRAY(&ah->iniModesTxGain,
546 ar9280Modes_high_power_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
549 INIT_INI_ARRAY(&ah->iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
553 INIT_INI_ARRAY(&ah->iniModesTxGain,
554 ar9280Modes_original_tx_gain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
559 static int ath9k_hw_post_attach(struct ath_hw *ah)
563 if (!ath9k_hw_chip_test(ah))
566 ecode = ath9k_hw_rf_claim(ah);
570 ecode = ath9k_hw_eeprom_attach(ah);
574 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
575 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
577 ecode = ath9k_hw_rfattach(ah);
581 if (!AR_SREV_9100(ah)) {
582 ath9k_hw_ani_setup(ah);
583 ath9k_hw_ani_attach(ah);
589 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
596 ah = ath9k_hw_newstate(devid, sc, status);
600 ath9k_hw_set_defaults(ah);
602 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
603 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
608 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
609 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
614 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
615 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
616 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
617 ah->config.serialize_regmode =
620 ah->config.serialize_regmode =
625 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
626 ah->config.serialize_regmode);
628 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
629 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
630 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
631 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
632 DPRINTF(sc, ATH_DBG_FATAL,
633 "Mac Chip Rev 0x%02x.%x is not supported by "
634 "this driver\n", ah->hw_version.macVersion,
635 ah->hw_version.macRev);
640 if (AR_SREV_9100(ah)) {
641 ah->iq_caldata.calData = &iq_cal_multi_sample;
642 ah->supp_cals = IQ_MISMATCH_CAL;
643 ah->is_pciexpress = false;
645 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
647 if (AR_SREV_9160_10_OR_LATER(ah)) {
648 if (AR_SREV_9280_10_OR_LATER(ah)) {
649 ah->iq_caldata.calData = &iq_cal_single_sample;
650 ah->adcgain_caldata.calData =
651 &adc_gain_cal_single_sample;
652 ah->adcdc_caldata.calData =
653 &adc_dc_cal_single_sample;
654 ah->adcdc_calinitdata.calData =
657 ah->iq_caldata.calData = &iq_cal_multi_sample;
658 ah->adcgain_caldata.calData =
659 &adc_gain_cal_multi_sample;
660 ah->adcdc_caldata.calData =
661 &adc_dc_cal_multi_sample;
662 ah->adcdc_calinitdata.calData =
665 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
668 ah->ani_function = ATH9K_ANI_ALL;
669 if (AR_SREV_9280_10_OR_LATER(ah))
670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
672 if (AR_SREV_9285_12_OR_LATER(ah)) {
674 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
675 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
676 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
677 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
679 if (ah->config.pcie_clock_req) {
680 INIT_INI_ARRAY(&ah->iniPcieSerdes,
681 ar9285PciePhy_clkreq_off_L1_9285_1_2,
682 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
684 INIT_INI_ARRAY(&ah->iniPcieSerdes,
685 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
686 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
689 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
690 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
691 ARRAY_SIZE(ar9285Modes_9285), 6);
692 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
693 ARRAY_SIZE(ar9285Common_9285), 2);
695 if (ah->config.pcie_clock_req) {
696 INIT_INI_ARRAY(&ah->iniPcieSerdes,
697 ar9285PciePhy_clkreq_off_L1_9285,
698 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
700 INIT_INI_ARRAY(&ah->iniPcieSerdes,
701 ar9285PciePhy_clkreq_always_on_L1_9285,
702 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
704 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
705 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
706 ARRAY_SIZE(ar9280Modes_9280_2), 6);
707 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
708 ARRAY_SIZE(ar9280Common_9280_2), 2);
710 if (ah->config.pcie_clock_req) {
711 INIT_INI_ARRAY(&ah->iniPcieSerdes,
712 ar9280PciePhy_clkreq_off_L1_9280,
713 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
715 INIT_INI_ARRAY(&ah->iniPcieSerdes,
716 ar9280PciePhy_clkreq_always_on_L1_9280,
717 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
719 INIT_INI_ARRAY(&ah->iniModesAdditional,
720 ar9280Modes_fast_clock_9280_2,
721 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
722 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
723 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
724 ARRAY_SIZE(ar9280Modes_9280), 6);
725 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
726 ARRAY_SIZE(ar9280Common_9280), 2);
727 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
729 ARRAY_SIZE(ar5416Modes_9160), 6);
730 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
731 ARRAY_SIZE(ar5416Common_9160), 2);
732 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
733 ARRAY_SIZE(ar5416Bank0_9160), 2);
734 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
735 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
736 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
737 ARRAY_SIZE(ar5416Bank1_9160), 2);
738 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
739 ARRAY_SIZE(ar5416Bank2_9160), 2);
740 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
741 ARRAY_SIZE(ar5416Bank3_9160), 3);
742 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
743 ARRAY_SIZE(ar5416Bank6_9160), 3);
744 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
745 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
746 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
747 ARRAY_SIZE(ar5416Bank7_9160), 2);
748 if (AR_SREV_9160_11(ah)) {
749 INIT_INI_ARRAY(&ah->iniAddac,
751 ARRAY_SIZE(ar5416Addac_91601_1), 2);
753 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
754 ARRAY_SIZE(ar5416Addac_9160), 2);
756 } else if (AR_SREV_9100_OR_LATER(ah)) {
757 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
758 ARRAY_SIZE(ar5416Modes_9100), 6);
759 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
760 ARRAY_SIZE(ar5416Common_9100), 2);
761 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
762 ARRAY_SIZE(ar5416Bank0_9100), 2);
763 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
764 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
765 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
766 ARRAY_SIZE(ar5416Bank1_9100), 2);
767 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
768 ARRAY_SIZE(ar5416Bank2_9100), 2);
769 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
770 ARRAY_SIZE(ar5416Bank3_9100), 3);
771 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
772 ARRAY_SIZE(ar5416Bank6_9100), 3);
773 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
774 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
775 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
776 ARRAY_SIZE(ar5416Bank7_9100), 2);
777 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
778 ARRAY_SIZE(ar5416Addac_9100), 2);
780 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
781 ARRAY_SIZE(ar5416Modes), 6);
782 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
783 ARRAY_SIZE(ar5416Common), 2);
784 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
785 ARRAY_SIZE(ar5416Bank0), 2);
786 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
787 ARRAY_SIZE(ar5416BB_RfGain), 3);
788 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
789 ARRAY_SIZE(ar5416Bank1), 2);
790 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
791 ARRAY_SIZE(ar5416Bank2), 2);
792 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
793 ARRAY_SIZE(ar5416Bank3), 3);
794 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
795 ARRAY_SIZE(ar5416Bank6), 3);
796 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
797 ARRAY_SIZE(ar5416Bank6TPC), 3);
798 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
799 ARRAY_SIZE(ar5416Bank7), 2);
800 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
801 ARRAY_SIZE(ar5416Addac), 2);
804 if (ah->is_pciexpress)
805 ath9k_hw_configpcipowersave(ah, 0);
807 ath9k_hw_disablepcie(ah);
809 ecode = ath9k_hw_post_attach(ah);
813 if (AR_SREV_9285_12_OR_LATER(ah)) {
814 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
817 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
818 INIT_INI_ARRAY(&ah->iniModesTxGain,
819 ar9285Modes_high_power_tx_gain_9285_1_2,
820 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
822 INIT_INI_ARRAY(&ah->iniModesTxGain,
823 ar9285Modes_original_tx_gain_9285_1_2,
824 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
830 if (AR_SREV_9280_20(ah))
831 ath9k_hw_init_rxgain_ini(ah);
834 if (AR_SREV_9280_20(ah))
835 ath9k_hw_init_txgain_ini(ah);
837 ath9k_hw_fill_cap_info(ah);
839 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
840 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
843 for (i = 0; i < ah->iniModes.ia_rows; i++) {
844 u32 reg = INI_RA(&ah->iniModes, i, 0);
846 for (j = 1; j < ah->iniModes.ia_columns; j++) {
847 u32 val = INI_RA(&ah->iniModes, i, j);
849 INI_RA(&ah->iniModes, i, j) =
850 ath9k_hw_ini_fixup(ah,
857 ecode = ath9k_hw_init_macaddr(ah);
859 DPRINTF(sc, ATH_DBG_FATAL,
860 "Failed to initialize MAC address\n");
864 if (AR_SREV_9285(ah))
865 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
867 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
869 ath9k_init_nfcal_hist_buffer(ah);
881 static void ath9k_hw_init_bb(struct ath_hw *ah,
882 struct ath9k_channel *chan)
886 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
888 synthDelay = (4 * synthDelay) / 22;
892 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
894 udelay(synthDelay + BASE_ACTIVATE_DELAY);
897 static void ath9k_hw_init_qos(struct ath_hw *ah)
899 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
900 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
902 REG_WRITE(ah, AR_QOS_NO_ACK,
903 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
904 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
905 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
907 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
908 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
909 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
910 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
911 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
914 static void ath9k_hw_init_pll(struct ath_hw *ah,
915 struct ath9k_channel *chan)
919 if (AR_SREV_9100(ah)) {
920 if (chan && IS_CHAN_5GHZ(chan))
925 if (AR_SREV_9280_10_OR_LATER(ah)) {
926 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
928 if (chan && IS_CHAN_HALF_RATE(chan))
929 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
930 else if (chan && IS_CHAN_QUARTER_RATE(chan))
931 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
933 if (chan && IS_CHAN_5GHZ(chan)) {
934 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
937 if (AR_SREV_9280_20(ah)) {
938 if (((chan->channel % 20) == 0)
939 || ((chan->channel % 10) == 0))
945 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
948 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
950 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
952 if (chan && IS_CHAN_HALF_RATE(chan))
953 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
954 else if (chan && IS_CHAN_QUARTER_RATE(chan))
955 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
957 if (chan && IS_CHAN_5GHZ(chan))
958 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
960 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
962 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
964 if (chan && IS_CHAN_HALF_RATE(chan))
965 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
966 else if (chan && IS_CHAN_QUARTER_RATE(chan))
967 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
969 if (chan && IS_CHAN_5GHZ(chan))
970 pll |= SM(0xa, AR_RTC_PLL_DIV);
972 pll |= SM(0xb, AR_RTC_PLL_DIV);
975 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
977 udelay(RTC_PLL_SETTLE_DELAY);
979 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
982 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
984 int rx_chainmask, tx_chainmask;
986 rx_chainmask = ah->rxchainmask;
987 tx_chainmask = ah->txchainmask;
989 switch (rx_chainmask) {
991 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
992 AR_PHY_SWAP_ALT_CHAIN);
994 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
995 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
996 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1002 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1003 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1009 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1010 if (tx_chainmask == 0x5) {
1011 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1012 AR_PHY_SWAP_ALT_CHAIN);
1014 if (AR_SREV_9100(ah))
1015 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1016 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1019 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1020 enum nl80211_iftype opmode)
1022 ah->mask_reg = AR_IMR_TXERR |
1028 if (ah->config.intr_mitigation)
1029 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1031 ah->mask_reg |= AR_IMR_RXOK;
1033 ah->mask_reg |= AR_IMR_TXOK;
1035 if (opmode == NL80211_IFTYPE_AP)
1036 ah->mask_reg |= AR_IMR_MIB;
1038 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1039 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1041 if (!AR_SREV_9100(ah)) {
1042 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1043 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1044 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1048 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1050 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1051 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1052 ah->acktimeout = (u32) -1;
1055 REG_RMW_FIELD(ah, AR_TIME_OUT,
1056 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1057 ah->acktimeout = us;
1062 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1064 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1065 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1066 ah->ctstimeout = (u32) -1;
1069 REG_RMW_FIELD(ah, AR_TIME_OUT,
1070 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1071 ah->ctstimeout = us;
1076 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1079 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1080 "bad global tx timeout %u\n", tu);
1081 ah->globaltxtimeout = (u32) -1;
1084 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1085 ah->globaltxtimeout = tu;
1090 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1092 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1095 if (ah->misc_mode != 0)
1096 REG_WRITE(ah, AR_PCU_MISC,
1097 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1098 if (ah->slottime != (u32) -1)
1099 ath9k_hw_setslottime(ah, ah->slottime);
1100 if (ah->acktimeout != (u32) -1)
1101 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1102 if (ah->ctstimeout != (u32) -1)
1103 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1104 if (ah->globaltxtimeout != (u32) -1)
1105 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1108 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1110 return vendorid == ATHEROS_VENDOR_ID ?
1111 ath9k_hw_devname(devid) : NULL;
1114 void ath9k_hw_detach(struct ath_hw *ah)
1116 if (!AR_SREV_9100(ah))
1117 ath9k_hw_ani_detach(ah);
1119 ath9k_hw_rfdetach(ah);
1120 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1124 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1126 struct ath_hw *ah = NULL;
1129 case AR5416_DEVID_PCI:
1130 case AR5416_DEVID_PCIE:
1131 case AR5416_AR9100_DEVID:
1132 case AR9160_DEVID_PCI:
1133 case AR9280_DEVID_PCI:
1134 case AR9280_DEVID_PCIE:
1135 case AR9285_DEVID_PCIE:
1136 ah = ath9k_hw_do_attach(devid, sc, error);
1150 static void ath9k_hw_override_ini(struct ath_hw *ah,
1151 struct ath9k_channel *chan)
1154 * Set the RX_ABORT and RX_DIS and clear if off only after
1155 * RXE is set for MAC. This prevents frames with corrupted
1156 * descriptor status.
1158 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1161 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1162 AR_SREV_9280_10_OR_LATER(ah))
1165 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1168 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1169 struct ar5416_eeprom_def *pEepData,
1172 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1174 switch (ah->hw_version.devid) {
1175 case AR9280_DEVID_PCI:
1176 if (reg == 0x7894) {
1177 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1178 "ini VAL: %x EEPROM: %x\n", value,
1179 (pBase->version & 0xff));
1181 if ((pBase->version & 0xff) > 0x0a) {
1182 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1185 value &= ~AR_AN_TOP2_PWDCLKIND;
1186 value |= AR_AN_TOP2_PWDCLKIND &
1187 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1189 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1190 "PWDCLKIND Earlier Rev\n");
1193 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1194 "final ini VAL: %x\n", value);
1202 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1203 struct ar5416_eeprom_def *pEepData,
1206 if (ah->eep_map == EEP_MAP_4KBITS)
1209 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1212 static void ath9k_olc_init(struct ath_hw *ah)
1216 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1217 ah->originalGain[i] =
1218 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1223 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1224 struct ath9k_channel *chan)
1226 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1228 if (IS_CHAN_B(chan))
1230 else if (IS_CHAN_G(chan))
1238 static int ath9k_hw_process_ini(struct ath_hw *ah,
1239 struct ath9k_channel *chan,
1240 enum ath9k_ht_macmode macmode)
1242 int i, regWrites = 0;
1243 struct ieee80211_channel *channel = chan->chan;
1244 u32 modesIndex, freqIndex;
1247 switch (chan->chanmode) {
1249 case CHANNEL_A_HT20:
1253 case CHANNEL_A_HT40PLUS:
1254 case CHANNEL_A_HT40MINUS:
1259 case CHANNEL_G_HT20:
1264 case CHANNEL_G_HT40PLUS:
1265 case CHANNEL_G_HT40MINUS:
1274 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1275 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1276 ah->eep_ops->set_addac(ah, chan);
1278 if (AR_SREV_5416_22_OR_LATER(ah)) {
1279 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1281 struct ar5416IniArray temp;
1283 sizeof(u32) * ah->iniAddac.ia_rows *
1284 ah->iniAddac.ia_columns;
1286 memcpy(ah->addac5416_21,
1287 ah->iniAddac.ia_array, addacSize);
1289 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1291 temp.ia_array = ah->addac5416_21;
1292 temp.ia_columns = ah->iniAddac.ia_columns;
1293 temp.ia_rows = ah->iniAddac.ia_rows;
1294 REG_WRITE_ARRAY(&temp, 1, regWrites);
1297 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1299 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1300 u32 reg = INI_RA(&ah->iniModes, i, 0);
1301 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1303 REG_WRITE(ah, reg, val);
1305 if (reg >= 0x7800 && reg < 0x78a0
1306 && ah->config.analog_shiftreg) {
1310 DO_DELAY(regWrites);
1313 if (AR_SREV_9280(ah))
1314 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1316 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1317 AR_SREV_9285_12_OR_LATER(ah)))
1318 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1320 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1321 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1322 u32 val = INI_RA(&ah->iniCommon, i, 1);
1324 REG_WRITE(ah, reg, val);
1326 if (reg >= 0x7800 && reg < 0x78a0
1327 && ah->config.analog_shiftreg) {
1331 DO_DELAY(regWrites);
1334 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1336 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1337 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1341 ath9k_hw_override_ini(ah, chan);
1342 ath9k_hw_set_regs(ah, chan, macmode);
1343 ath9k_hw_init_chain_masks(ah);
1345 if (OLC_FOR_AR9280_20_LATER)
1348 status = ah->eep_ops->set_txpower(ah, chan,
1349 ath9k_regd_get_ctl(&ah->regulatory, chan),
1350 channel->max_antenna_gain * 2,
1351 channel->max_power * 2,
1352 min((u32) MAX_RATE_POWER,
1353 (u32) ah->regulatory.power_limit));
1355 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1356 "Error initializing transmit power\n");
1360 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1361 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1362 "ar5416SetRfRegs failed\n");
1369 /****************************************/
1370 /* Reset and Channel Switching Routines */
1371 /****************************************/
1373 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1380 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1381 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1383 if (!AR_SREV_9280_10_OR_LATER(ah))
1384 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1385 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1387 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1388 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1390 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1393 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1395 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1398 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1402 regval = REG_READ(ah, AR_AHB_MODE);
1403 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1405 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1406 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1408 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1410 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1411 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1413 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1415 if (AR_SREV_9285(ah)) {
1416 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1417 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1419 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1420 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1424 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1428 val = REG_READ(ah, AR_STA_ID1);
1429 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1431 case NL80211_IFTYPE_AP:
1432 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1433 | AR_STA_ID1_KSRCH_MODE);
1434 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1436 case NL80211_IFTYPE_ADHOC:
1437 case NL80211_IFTYPE_MESH_POINT:
1438 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1439 | AR_STA_ID1_KSRCH_MODE);
1440 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1442 case NL80211_IFTYPE_STATION:
1443 case NL80211_IFTYPE_MONITOR:
1444 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1449 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1454 u32 coef_exp, coef_man;
1456 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1457 if ((coef_scaled >> coef_exp) & 0x1)
1460 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1462 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1464 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1465 *coef_exponent = coef_exp - 16;
1468 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1469 struct ath9k_channel *chan)
1471 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1472 u32 clockMhzScaled = 0x64000000;
1473 struct chan_centers centers;
1475 if (IS_CHAN_HALF_RATE(chan))
1476 clockMhzScaled = clockMhzScaled >> 1;
1477 else if (IS_CHAN_QUARTER_RATE(chan))
1478 clockMhzScaled = clockMhzScaled >> 2;
1480 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1481 coef_scaled = clockMhzScaled / centers.synth_center;
1483 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1486 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1487 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1488 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1489 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1491 coef_scaled = (9 * coef_scaled) / 10;
1493 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1496 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1497 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1498 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1499 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1502 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1507 if (AR_SREV_9100(ah)) {
1508 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1509 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1510 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1511 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1512 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1515 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1516 AR_RTC_FORCE_WAKE_ON_INT);
1518 if (AR_SREV_9100(ah)) {
1519 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1520 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1522 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1524 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1525 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1526 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1527 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1529 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1532 rst_flags = AR_RTC_RC_MAC_WARM;
1533 if (type == ATH9K_RESET_COLD)
1534 rst_flags |= AR_RTC_RC_MAC_COLD;
1537 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1540 REG_WRITE(ah, AR_RTC_RC, 0);
1541 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1542 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1543 "RTC stuck in MAC reset\n");
1547 if (!AR_SREV_9100(ah))
1548 REG_WRITE(ah, AR_RC, 0);
1550 ath9k_hw_init_pll(ah, NULL);
1552 if (AR_SREV_9100(ah))
1558 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1560 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561 AR_RTC_FORCE_WAKE_ON_INT);
1563 REG_WRITE(ah, AR_RTC_RESET, 0);
1565 REG_WRITE(ah, AR_RTC_RESET, 1);
1567 if (!ath9k_hw_wait(ah,
1572 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1576 ath9k_hw_read_revisions(ah);
1578 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1581 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1583 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1584 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1587 case ATH9K_RESET_POWER_ON:
1588 return ath9k_hw_set_reset_power_on(ah);
1590 case ATH9K_RESET_WARM:
1591 case ATH9K_RESET_COLD:
1592 return ath9k_hw_set_reset(ah, type);
1599 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1600 enum ath9k_ht_macmode macmode)
1603 u32 enableDacFifo = 0;
1605 if (AR_SREV_9285_10_OR_LATER(ah))
1606 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1607 AR_PHY_FC_ENABLE_DAC_FIFO);
1609 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1610 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1612 if (IS_CHAN_HT40(chan)) {
1613 phymode |= AR_PHY_FC_DYN2040_EN;
1615 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1616 (chan->chanmode == CHANNEL_G_HT40PLUS))
1617 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1619 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1620 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1622 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1624 ath9k_hw_set11nmac2040(ah, macmode);
1626 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1627 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1630 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1631 struct ath9k_channel *chan)
1633 if (OLC_FOR_AR9280_20_LATER) {
1634 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1636 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1639 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1642 ah->chip_fullsleep = false;
1643 ath9k_hw_init_pll(ah, chan);
1644 ath9k_hw_set_rfmode(ah, chan);
1649 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1650 struct ath9k_channel *chan,
1651 enum ath9k_ht_macmode macmode)
1653 struct ieee80211_channel *channel = chan->chan;
1654 u32 synthDelay, qnum;
1656 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1657 if (ath9k_hw_numtxpending(ah, qnum)) {
1658 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1659 "Transmit frames pending on queue %d\n", qnum);
1664 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1665 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1666 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1667 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1668 "Could not kill baseband RX\n");
1672 ath9k_hw_set_regs(ah, chan, macmode);
1674 if (AR_SREV_9280_10_OR_LATER(ah)) {
1675 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1676 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1677 "Failed to set channel\n");
1681 if (!(ath9k_hw_set_channel(ah, chan))) {
1682 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1683 "Failed to set channel\n");
1688 if (ah->eep_ops->set_txpower(ah, chan,
1689 ath9k_regd_get_ctl(&ah->regulatory, chan),
1690 channel->max_antenna_gain * 2,
1691 channel->max_power * 2,
1692 min((u32) MAX_RATE_POWER,
1693 (u32) ah->regulatory.power_limit)) != 0) {
1694 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1695 "Error initializing transmit power\n");
1699 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1700 if (IS_CHAN_B(chan))
1701 synthDelay = (4 * synthDelay) / 22;
1705 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1707 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1709 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1710 ath9k_hw_set_delta_slope(ah, chan);
1712 if (AR_SREV_9280_10_OR_LATER(ah))
1713 ath9k_hw_9280_spur_mitigate(ah, chan);
1715 ath9k_hw_spur_mitigate(ah, chan);
1717 if (!chan->oneTimeCalsDone)
1718 chan->oneTimeCalsDone = true;
1723 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1725 int bb_spur = AR_NO_SPUR;
1728 int bb_spur_off, spur_subchannel_sd;
1730 int spur_delta_phase;
1732 int upper, lower, cur_vit_mask;
1735 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1736 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1738 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1739 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1741 int inc[4] = { 0, 100, 0, 0 };
1742 struct chan_centers centers;
1749 bool is2GHz = IS_CHAN_2GHZ(chan);
1751 memset(&mask_m, 0, sizeof(int8_t) * 123);
1752 memset(&mask_p, 0, sizeof(int8_t) * 123);
1754 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1755 freq = centers.synth_center;
1757 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1758 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1759 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1762 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1764 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1766 if (AR_NO_SPUR == cur_bb_spur)
1768 cur_bb_spur = cur_bb_spur - freq;
1770 if (IS_CHAN_HT40(chan)) {
1771 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1772 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1773 bb_spur = cur_bb_spur;
1776 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1777 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1778 bb_spur = cur_bb_spur;
1783 if (AR_NO_SPUR == bb_spur) {
1784 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1785 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1788 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1789 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1792 bin = bb_spur * 320;
1794 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1796 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1797 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1798 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1799 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1800 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1802 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1803 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1804 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1805 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1806 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1807 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1809 if (IS_CHAN_HT40(chan)) {
1811 spur_subchannel_sd = 1;
1812 bb_spur_off = bb_spur + 10;
1814 spur_subchannel_sd = 0;
1815 bb_spur_off = bb_spur - 10;
1818 spur_subchannel_sd = 0;
1819 bb_spur_off = bb_spur;
1822 if (IS_CHAN_HT40(chan))
1824 ((bb_spur * 262144) /
1825 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1828 ((bb_spur * 524288) /
1829 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1831 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1832 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1834 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1835 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1836 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1837 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1839 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1840 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1846 for (i = 0; i < 4; i++) {
1850 for (bp = 0; bp < 30; bp++) {
1851 if ((cur_bin > lower) && (cur_bin < upper)) {
1852 pilot_mask = pilot_mask | 0x1 << bp;
1853 chan_mask = chan_mask | 0x1 << bp;
1858 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1859 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1862 cur_vit_mask = 6100;
1866 for (i = 0; i < 123; i++) {
1867 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1869 /* workaround for gcc bug #37014 */
1870 volatile int tmp_v = abs(cur_vit_mask - bin);
1876 if (cur_vit_mask < 0)
1877 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1879 mask_p[cur_vit_mask / 100] = mask_amt;
1881 cur_vit_mask -= 100;
1884 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1885 | (mask_m[48] << 26) | (mask_m[49] << 24)
1886 | (mask_m[50] << 22) | (mask_m[51] << 20)
1887 | (mask_m[52] << 18) | (mask_m[53] << 16)
1888 | (mask_m[54] << 14) | (mask_m[55] << 12)
1889 | (mask_m[56] << 10) | (mask_m[57] << 8)
1890 | (mask_m[58] << 6) | (mask_m[59] << 4)
1891 | (mask_m[60] << 2) | (mask_m[61] << 0);
1892 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1893 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1895 tmp_mask = (mask_m[31] << 28)
1896 | (mask_m[32] << 26) | (mask_m[33] << 24)
1897 | (mask_m[34] << 22) | (mask_m[35] << 20)
1898 | (mask_m[36] << 18) | (mask_m[37] << 16)
1899 | (mask_m[48] << 14) | (mask_m[39] << 12)
1900 | (mask_m[40] << 10) | (mask_m[41] << 8)
1901 | (mask_m[42] << 6) | (mask_m[43] << 4)
1902 | (mask_m[44] << 2) | (mask_m[45] << 0);
1903 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1906 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1907 | (mask_m[18] << 26) | (mask_m[18] << 24)
1908 | (mask_m[20] << 22) | (mask_m[20] << 20)
1909 | (mask_m[22] << 18) | (mask_m[22] << 16)
1910 | (mask_m[24] << 14) | (mask_m[24] << 12)
1911 | (mask_m[25] << 10) | (mask_m[26] << 8)
1912 | (mask_m[27] << 6) | (mask_m[28] << 4)
1913 | (mask_m[29] << 2) | (mask_m[30] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1917 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1918 | (mask_m[2] << 26) | (mask_m[3] << 24)
1919 | (mask_m[4] << 22) | (mask_m[5] << 20)
1920 | (mask_m[6] << 18) | (mask_m[7] << 16)
1921 | (mask_m[8] << 14) | (mask_m[9] << 12)
1922 | (mask_m[10] << 10) | (mask_m[11] << 8)
1923 | (mask_m[12] << 6) | (mask_m[13] << 4)
1924 | (mask_m[14] << 2) | (mask_m[15] << 0);
1925 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1928 tmp_mask = (mask_p[15] << 28)
1929 | (mask_p[14] << 26) | (mask_p[13] << 24)
1930 | (mask_p[12] << 22) | (mask_p[11] << 20)
1931 | (mask_p[10] << 18) | (mask_p[9] << 16)
1932 | (mask_p[8] << 14) | (mask_p[7] << 12)
1933 | (mask_p[6] << 10) | (mask_p[5] << 8)
1934 | (mask_p[4] << 6) | (mask_p[3] << 4)
1935 | (mask_p[2] << 2) | (mask_p[1] << 0);
1936 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1939 tmp_mask = (mask_p[30] << 28)
1940 | (mask_p[29] << 26) | (mask_p[28] << 24)
1941 | (mask_p[27] << 22) | (mask_p[26] << 20)
1942 | (mask_p[25] << 18) | (mask_p[24] << 16)
1943 | (mask_p[23] << 14) | (mask_p[22] << 12)
1944 | (mask_p[21] << 10) | (mask_p[20] << 8)
1945 | (mask_p[19] << 6) | (mask_p[18] << 4)
1946 | (mask_p[17] << 2) | (mask_p[16] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1950 tmp_mask = (mask_p[45] << 28)
1951 | (mask_p[44] << 26) | (mask_p[43] << 24)
1952 | (mask_p[42] << 22) | (mask_p[41] << 20)
1953 | (mask_p[40] << 18) | (mask_p[39] << 16)
1954 | (mask_p[38] << 14) | (mask_p[37] << 12)
1955 | (mask_p[36] << 10) | (mask_p[35] << 8)
1956 | (mask_p[34] << 6) | (mask_p[33] << 4)
1957 | (mask_p[32] << 2) | (mask_p[31] << 0);
1958 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1959 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1961 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1962 | (mask_p[59] << 26) | (mask_p[58] << 24)
1963 | (mask_p[57] << 22) | (mask_p[56] << 20)
1964 | (mask_p[55] << 18) | (mask_p[54] << 16)
1965 | (mask_p[53] << 14) | (mask_p[52] << 12)
1966 | (mask_p[51] << 10) | (mask_p[50] << 8)
1967 | (mask_p[49] << 6) | (mask_p[48] << 4)
1968 | (mask_p[47] << 2) | (mask_p[46] << 0);
1969 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1970 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1973 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1975 int bb_spur = AR_NO_SPUR;
1978 int spur_delta_phase;
1980 int upper, lower, cur_vit_mask;
1983 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1984 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1986 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1987 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1989 int inc[4] = { 0, 100, 0, 0 };
1996 bool is2GHz = IS_CHAN_2GHZ(chan);
1998 memset(&mask_m, 0, sizeof(int8_t) * 123);
1999 memset(&mask_p, 0, sizeof(int8_t) * 123);
2001 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2002 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2003 if (AR_NO_SPUR == cur_bb_spur)
2005 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2006 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2007 bb_spur = cur_bb_spur;
2012 if (AR_NO_SPUR == bb_spur)
2017 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2018 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2019 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2020 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2021 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2023 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2025 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2026 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2027 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2028 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2029 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2030 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2032 spur_delta_phase = ((bb_spur * 524288) / 100) &
2033 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2035 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2036 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2038 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2039 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2040 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2041 REG_WRITE(ah, AR_PHY_TIMING11, new);
2047 for (i = 0; i < 4; i++) {
2051 for (bp = 0; bp < 30; bp++) {
2052 if ((cur_bin > lower) && (cur_bin < upper)) {
2053 pilot_mask = pilot_mask | 0x1 << bp;
2054 chan_mask = chan_mask | 0x1 << bp;
2059 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2060 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2063 cur_vit_mask = 6100;
2067 for (i = 0; i < 123; i++) {
2068 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2070 /* workaround for gcc bug #37014 */
2071 volatile int tmp_v = abs(cur_vit_mask - bin);
2077 if (cur_vit_mask < 0)
2078 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2080 mask_p[cur_vit_mask / 100] = mask_amt;
2082 cur_vit_mask -= 100;
2085 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2086 | (mask_m[48] << 26) | (mask_m[49] << 24)
2087 | (mask_m[50] << 22) | (mask_m[51] << 20)
2088 | (mask_m[52] << 18) | (mask_m[53] << 16)
2089 | (mask_m[54] << 14) | (mask_m[55] << 12)
2090 | (mask_m[56] << 10) | (mask_m[57] << 8)
2091 | (mask_m[58] << 6) | (mask_m[59] << 4)
2092 | (mask_m[60] << 2) | (mask_m[61] << 0);
2093 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2094 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2096 tmp_mask = (mask_m[31] << 28)
2097 | (mask_m[32] << 26) | (mask_m[33] << 24)
2098 | (mask_m[34] << 22) | (mask_m[35] << 20)
2099 | (mask_m[36] << 18) | (mask_m[37] << 16)
2100 | (mask_m[48] << 14) | (mask_m[39] << 12)
2101 | (mask_m[40] << 10) | (mask_m[41] << 8)
2102 | (mask_m[42] << 6) | (mask_m[43] << 4)
2103 | (mask_m[44] << 2) | (mask_m[45] << 0);
2104 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2107 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2108 | (mask_m[18] << 26) | (mask_m[18] << 24)
2109 | (mask_m[20] << 22) | (mask_m[20] << 20)
2110 | (mask_m[22] << 18) | (mask_m[22] << 16)
2111 | (mask_m[24] << 14) | (mask_m[24] << 12)
2112 | (mask_m[25] << 10) | (mask_m[26] << 8)
2113 | (mask_m[27] << 6) | (mask_m[28] << 4)
2114 | (mask_m[29] << 2) | (mask_m[30] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2118 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2119 | (mask_m[2] << 26) | (mask_m[3] << 24)
2120 | (mask_m[4] << 22) | (mask_m[5] << 20)
2121 | (mask_m[6] << 18) | (mask_m[7] << 16)
2122 | (mask_m[8] << 14) | (mask_m[9] << 12)
2123 | (mask_m[10] << 10) | (mask_m[11] << 8)
2124 | (mask_m[12] << 6) | (mask_m[13] << 4)
2125 | (mask_m[14] << 2) | (mask_m[15] << 0);
2126 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2129 tmp_mask = (mask_p[15] << 28)
2130 | (mask_p[14] << 26) | (mask_p[13] << 24)
2131 | (mask_p[12] << 22) | (mask_p[11] << 20)
2132 | (mask_p[10] << 18) | (mask_p[9] << 16)
2133 | (mask_p[8] << 14) | (mask_p[7] << 12)
2134 | (mask_p[6] << 10) | (mask_p[5] << 8)
2135 | (mask_p[4] << 6) | (mask_p[3] << 4)
2136 | (mask_p[2] << 2) | (mask_p[1] << 0);
2137 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2140 tmp_mask = (mask_p[30] << 28)
2141 | (mask_p[29] << 26) | (mask_p[28] << 24)
2142 | (mask_p[27] << 22) | (mask_p[26] << 20)
2143 | (mask_p[25] << 18) | (mask_p[24] << 16)
2144 | (mask_p[23] << 14) | (mask_p[22] << 12)
2145 | (mask_p[21] << 10) | (mask_p[20] << 8)
2146 | (mask_p[19] << 6) | (mask_p[18] << 4)
2147 | (mask_p[17] << 2) | (mask_p[16] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2151 tmp_mask = (mask_p[45] << 28)
2152 | (mask_p[44] << 26) | (mask_p[43] << 24)
2153 | (mask_p[42] << 22) | (mask_p[41] << 20)
2154 | (mask_p[40] << 18) | (mask_p[39] << 16)
2155 | (mask_p[38] << 14) | (mask_p[37] << 12)
2156 | (mask_p[36] << 10) | (mask_p[35] << 8)
2157 | (mask_p[34] << 6) | (mask_p[33] << 4)
2158 | (mask_p[32] << 2) | (mask_p[31] << 0);
2159 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2160 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2162 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2163 | (mask_p[59] << 26) | (mask_p[58] << 24)
2164 | (mask_p[57] << 22) | (mask_p[56] << 20)
2165 | (mask_p[55] << 18) | (mask_p[54] << 16)
2166 | (mask_p[53] << 14) | (mask_p[52] << 12)
2167 | (mask_p[51] << 10) | (mask_p[50] << 8)
2168 | (mask_p[49] << 6) | (mask_p[48] << 4)
2169 | (mask_p[47] << 2) | (mask_p[46] << 0);
2170 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2171 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2174 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2175 bool bChannelChange)
2178 struct ath_softc *sc = ah->ah_sc;
2179 struct ath9k_channel *curchan = ah->curchan;
2182 int i, rx_chainmask, r;
2184 ah->extprotspacing = sc->ht_extprotspacing;
2185 ah->txchainmask = sc->tx_chainmask;
2186 ah->rxchainmask = sc->rx_chainmask;
2188 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2192 ath9k_hw_getnf(ah, curchan);
2194 if (bChannelChange &&
2195 (ah->chip_fullsleep != true) &&
2196 (ah->curchan != NULL) &&
2197 (chan->channel != ah->curchan->channel) &&
2198 ((chan->channelFlags & CHANNEL_ALL) ==
2199 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2200 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2201 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2203 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2204 ath9k_hw_loadnf(ah, ah->curchan);
2205 ath9k_hw_start_nfcal(ah);
2210 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2211 if (saveDefAntenna == 0)
2214 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2216 saveLedState = REG_READ(ah, AR_CFG_LED) &
2217 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2218 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2220 ath9k_hw_mark_phy_inactive(ah);
2222 if (!ath9k_hw_chip_reset(ah, chan)) {
2223 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2227 if (AR_SREV_9280_10_OR_LATER(ah))
2228 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2230 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2234 /* Setup MFP options for CCMP */
2235 if (AR_SREV_9280_20_OR_LATER(ah)) {
2236 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2237 * frames when constructing CCMP AAD. */
2238 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2240 ah->sw_mgmt_crypto = false;
2241 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2242 /* Disable hardware crypto for management frames */
2243 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2244 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2245 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2246 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2247 ah->sw_mgmt_crypto = true;
2249 ah->sw_mgmt_crypto = true;
2251 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2252 ath9k_hw_set_delta_slope(ah, chan);
2254 if (AR_SREV_9280_10_OR_LATER(ah))
2255 ath9k_hw_9280_spur_mitigate(ah, chan);
2257 ath9k_hw_spur_mitigate(ah, chan);
2259 ah->eep_ops->set_board_values(ah, chan);
2261 ath9k_hw_decrease_chain_power(ah, chan);
2263 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2264 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2266 | AR_STA_ID1_RTS_USE_DEF
2268 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2269 | ah->sta_id1_defaults);
2270 ath9k_hw_set_operating_mode(ah, ah->opmode);
2272 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2273 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2275 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2277 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2278 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2279 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2281 REG_WRITE(ah, AR_ISR, ~0);
2283 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2285 if (AR_SREV_9280_10_OR_LATER(ah)) {
2286 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2289 if (!(ath9k_hw_set_channel(ah, chan)))
2293 for (i = 0; i < AR_NUM_DCU; i++)
2294 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2297 for (i = 0; i < ah->caps.total_queues; i++)
2298 ath9k_hw_resettxqueue(ah, i);
2300 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2301 ath9k_hw_init_qos(ah);
2303 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2304 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2305 ath9k_enable_rfkill(ah);
2307 ath9k_hw_init_user_settings(ah);
2309 REG_WRITE(ah, AR_STA_ID1,
2310 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2312 ath9k_hw_set_dma(ah);
2314 REG_WRITE(ah, AR_OBS, 8);
2316 if (ah->config.intr_mitigation) {
2317 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2318 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2321 ath9k_hw_init_bb(ah, chan);
2323 if (!ath9k_hw_init_cal(ah, chan))
2326 rx_chainmask = ah->rxchainmask;
2327 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2328 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2329 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2332 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2334 if (AR_SREV_9100(ah)) {
2336 mask = REG_READ(ah, AR_CFG);
2337 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2338 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2339 "CFG Byte Swap Set 0x%x\n", mask);
2342 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2343 REG_WRITE(ah, AR_CFG, mask);
2344 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2345 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2349 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2356 /************************/
2357 /* Key Cache Management */
2358 /************************/
2360 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2364 if (entry >= ah->caps.keycache_size) {
2365 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2366 "keychache entry %u out of range\n", entry);
2370 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2372 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2373 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2374 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2375 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2377 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2378 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2379 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2381 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2382 u16 micentry = entry + 64;
2384 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2385 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2386 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2387 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2391 if (ah->curchan == NULL)
2397 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2401 if (entry >= ah->caps.keycache_size) {
2402 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2403 "keychache entry %u out of range\n", entry);
2408 macHi = (mac[5] << 8) | mac[4];
2409 macLo = (mac[3] << 24) |
2414 macLo |= (macHi & 1) << 31;
2419 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2420 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2425 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2426 const struct ath9k_keyval *k,
2429 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2430 u32 key0, key1, key2, key3, key4;
2433 if (entry >= pCap->keycache_size) {
2434 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2435 "keycache entry %u out of range\n", entry);
2439 switch (k->kv_type) {
2440 case ATH9K_CIPHER_AES_OCB:
2441 keyType = AR_KEYTABLE_TYPE_AES;
2443 case ATH9K_CIPHER_AES_CCM:
2444 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2445 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2446 "AES-CCM not supported by mac rev 0x%x\n",
2447 ah->hw_version.macRev);
2450 keyType = AR_KEYTABLE_TYPE_CCM;
2452 case ATH9K_CIPHER_TKIP:
2453 keyType = AR_KEYTABLE_TYPE_TKIP;
2454 if (ATH9K_IS_MIC_ENABLED(ah)
2455 && entry + 64 >= pCap->keycache_size) {
2456 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2457 "entry %u inappropriate for TKIP\n", entry);
2461 case ATH9K_CIPHER_WEP:
2462 if (k->kv_len < LEN_WEP40) {
2463 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2464 "WEP key length %u too small\n", k->kv_len);
2467 if (k->kv_len <= LEN_WEP40)
2468 keyType = AR_KEYTABLE_TYPE_40;
2469 else if (k->kv_len <= LEN_WEP104)
2470 keyType = AR_KEYTABLE_TYPE_104;
2472 keyType = AR_KEYTABLE_TYPE_128;
2474 case ATH9K_CIPHER_CLR:
2475 keyType = AR_KEYTABLE_TYPE_CLR;
2478 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2479 "cipher %u not supported\n", k->kv_type);
2483 key0 = get_unaligned_le32(k->kv_val + 0);
2484 key1 = get_unaligned_le16(k->kv_val + 4);
2485 key2 = get_unaligned_le32(k->kv_val + 6);
2486 key3 = get_unaligned_le16(k->kv_val + 10);
2487 key4 = get_unaligned_le32(k->kv_val + 12);
2488 if (k->kv_len <= LEN_WEP104)
2492 * Note: Key cache registers access special memory area that requires
2493 * two 32-bit writes to actually update the values in the internal
2494 * memory. Consequently, the exact order and pairs used here must be
2498 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2499 u16 micentry = entry + 64;
2502 * Write inverted key[47:0] first to avoid Michael MIC errors
2503 * on frames that could be sent or received at the same time.
2504 * The correct key will be written in the end once everything
2507 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2508 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2510 /* Write key[95:48] */
2511 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2512 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2514 /* Write key[127:96] and key type */
2515 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2516 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2518 /* Write MAC address for the entry */
2519 (void) ath9k_hw_keysetmac(ah, entry, mac);
2521 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2523 * TKIP uses two key cache entries:
2524 * Michael MIC TX/RX keys in the same key cache entry
2525 * (idx = main index + 64):
2526 * key0 [31:0] = RX key [31:0]
2527 * key1 [15:0] = TX key [31:16]
2528 * key1 [31:16] = reserved
2529 * key2 [31:0] = RX key [63:32]
2530 * key3 [15:0] = TX key [15:0]
2531 * key3 [31:16] = reserved
2532 * key4 [31:0] = TX key [63:32]
2534 u32 mic0, mic1, mic2, mic3, mic4;
2536 mic0 = get_unaligned_le32(k->kv_mic + 0);
2537 mic2 = get_unaligned_le32(k->kv_mic + 4);
2538 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2539 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2540 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2542 /* Write RX[31:0] and TX[31:16] */
2543 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2544 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2546 /* Write RX[63:32] and TX[15:0] */
2547 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2548 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2550 /* Write TX[63:32] and keyType(reserved) */
2551 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2552 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2553 AR_KEYTABLE_TYPE_CLR);
2557 * TKIP uses four key cache entries (two for group
2559 * Michael MIC TX/RX keys are in different key cache
2560 * entries (idx = main index + 64 for TX and
2561 * main index + 32 + 96 for RX):
2562 * key0 [31:0] = TX/RX MIC key [31:0]
2563 * key1 [31:0] = reserved
2564 * key2 [31:0] = TX/RX MIC key [63:32]
2565 * key3 [31:0] = reserved
2566 * key4 [31:0] = reserved
2568 * Upper layer code will call this function separately
2569 * for TX and RX keys when these registers offsets are
2574 mic0 = get_unaligned_le32(k->kv_mic + 0);
2575 mic2 = get_unaligned_le32(k->kv_mic + 4);
2577 /* Write MIC key[31:0] */
2578 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2579 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2581 /* Write MIC key[63:32] */
2582 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2585 /* Write TX[63:32] and keyType(reserved) */
2586 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2587 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2588 AR_KEYTABLE_TYPE_CLR);
2591 /* MAC address registers are reserved for the MIC entry */
2592 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2593 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2596 * Write the correct (un-inverted) key[47:0] last to enable
2597 * TKIP now that all other registers are set with correct
2600 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2601 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2603 /* Write key[47:0] */
2604 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2605 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2607 /* Write key[95:48] */
2608 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2609 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2611 /* Write key[127:96] and key type */
2612 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2613 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2615 /* Write MAC address for the entry */
2616 (void) ath9k_hw_keysetmac(ah, entry, mac);
2622 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2624 if (entry < ah->caps.keycache_size) {
2625 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2626 if (val & AR_KEYTABLE_VALID)
2632 /******************************/
2633 /* Power Management (Chipset) */
2634 /******************************/
2636 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2638 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2640 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2641 AR_RTC_FORCE_WAKE_EN);
2642 if (!AR_SREV_9100(ah))
2643 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2645 REG_CLR_BIT(ah, (AR_RTC_RESET),
2650 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2652 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2654 struct ath9k_hw_capabilities *pCap = &ah->caps;
2656 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2657 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2658 AR_RTC_FORCE_WAKE_ON_INT);
2660 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2661 AR_RTC_FORCE_WAKE_EN);
2666 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2672 if ((REG_READ(ah, AR_RTC_STATUS) &
2673 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2674 if (ath9k_hw_set_reset_reg(ah,
2675 ATH9K_RESET_POWER_ON) != true) {
2679 if (AR_SREV_9100(ah))
2680 REG_SET_BIT(ah, AR_RTC_RESET,
2683 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2684 AR_RTC_FORCE_WAKE_EN);
2687 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2688 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2689 if (val == AR_RTC_STATUS_ON)
2692 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2693 AR_RTC_FORCE_WAKE_EN);
2696 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2697 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2702 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2707 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2709 int status = true, setChip = true;
2710 static const char *modes[] = {
2717 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2718 modes[ah->power_mode], modes[mode]);
2721 case ATH9K_PM_AWAKE:
2722 status = ath9k_hw_set_power_awake(ah, setChip);
2724 case ATH9K_PM_FULL_SLEEP:
2725 ath9k_set_power_sleep(ah, setChip);
2726 ah->chip_fullsleep = true;
2728 case ATH9K_PM_NETWORK_SLEEP:
2729 ath9k_set_power_network_sleep(ah, setChip);
2732 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2733 "Unknown power mode %u\n", mode);
2736 ah->power_mode = mode;
2742 * Helper for ASPM support.
2744 * Disable PLL when in L0s as well as receiver clock when in L1.
2745 * This power saving option must be enabled through the SerDes.
2747 * Programming the SerDes must go through the same 288 bit serial shift
2748 * register as the other analog registers. Hence the 9 writes.
2750 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2754 if (ah->is_pciexpress != true)
2757 /* Do not touch SerDes registers */
2758 if (ah->config.pcie_powersave_enable == 2)
2761 /* Nothing to do on restore for 11N */
2765 if (AR_SREV_9280_20_OR_LATER(ah)) {
2767 * AR9280 2.0 or later chips use SerDes values from the
2768 * initvals.h initialized depending on chipset during
2769 * ath9k_hw_do_attach()
2771 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2772 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2773 INI_RA(&ah->iniPcieSerdes, i, 1));
2775 } else if (AR_SREV_9280(ah) &&
2776 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2777 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2778 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2780 /* RX shut off when elecidle is asserted */
2781 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2782 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2785 /* Shut off CLKREQ active in L1 */
2786 if (ah->config.pcie_clock_req)
2787 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2789 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2792 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2793 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2795 /* Load the new settings */
2796 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2799 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2800 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2802 /* RX shut off when elecidle is asserted */
2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2808 * Ignore ah->ah_config.pcie_clock_req setting for
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2813 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2814 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2815 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2817 /* Load the new settings */
2818 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2823 /* set bit 19 to allow forcing of pcie core into L1 state */
2824 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2826 /* Several PCIe massages to ensure proper behaviour */
2827 if (ah->config.pcie_waen) {
2828 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2830 if (AR_SREV_9285(ah))
2831 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2833 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2834 * otherwise card may disappear.
2836 else if (AR_SREV_9280(ah))
2837 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2839 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2843 /**********************/
2844 /* Interrupt Handling */
2845 /**********************/
2847 bool ath9k_hw_intrpend(struct ath_hw *ah)
2851 if (AR_SREV_9100(ah))
2854 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2855 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2858 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2859 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2860 && (host_isr != AR_INTR_SPURIOUS))
2866 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2870 struct ath9k_hw_capabilities *pCap = &ah->caps;
2872 bool fatal_int = false;
2874 if (!AR_SREV_9100(ah)) {
2875 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2876 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2877 == AR_RTC_STATUS_ON) {
2878 isr = REG_READ(ah, AR_ISR);
2882 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2883 AR_INTR_SYNC_DEFAULT;
2887 if (!isr && !sync_cause)
2891 isr = REG_READ(ah, AR_ISR);
2895 if (isr & AR_ISR_BCNMISC) {
2897 isr2 = REG_READ(ah, AR_ISR_S2);
2898 if (isr2 & AR_ISR_S2_TIM)
2899 mask2 |= ATH9K_INT_TIM;
2900 if (isr2 & AR_ISR_S2_DTIM)
2901 mask2 |= ATH9K_INT_DTIM;
2902 if (isr2 & AR_ISR_S2_DTIMSYNC)
2903 mask2 |= ATH9K_INT_DTIMSYNC;
2904 if (isr2 & (AR_ISR_S2_CABEND))
2905 mask2 |= ATH9K_INT_CABEND;
2906 if (isr2 & AR_ISR_S2_GTT)
2907 mask2 |= ATH9K_INT_GTT;
2908 if (isr2 & AR_ISR_S2_CST)
2909 mask2 |= ATH9K_INT_CST;
2910 if (isr2 & AR_ISR_S2_TSFOOR)
2911 mask2 |= ATH9K_INT_TSFOOR;
2914 isr = REG_READ(ah, AR_ISR_RAC);
2915 if (isr == 0xffffffff) {
2920 *masked = isr & ATH9K_INT_COMMON;
2922 if (ah->config.intr_mitigation) {
2923 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2924 *masked |= ATH9K_INT_RX;
2927 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2928 *masked |= ATH9K_INT_RX;
2930 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2934 *masked |= ATH9K_INT_TX;
2936 s0_s = REG_READ(ah, AR_ISR_S0_S);
2937 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2938 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2940 s1_s = REG_READ(ah, AR_ISR_S1_S);
2941 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2942 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2945 if (isr & AR_ISR_RXORN) {
2946 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2947 "receive FIFO overrun interrupt\n");
2950 if (!AR_SREV_9100(ah)) {
2951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2952 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2953 if (isr5 & AR_ISR_S5_TIM_TIMER)
2954 *masked |= ATH9K_INT_TIM_TIMER;
2961 if (AR_SREV_9100(ah))
2967 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2971 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2972 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2973 "received PCI FATAL interrupt\n");
2975 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2976 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2977 "received PCI PERR interrupt\n");
2979 *masked |= ATH9K_INT_FATAL;
2981 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2982 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2983 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2984 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2985 REG_WRITE(ah, AR_RC, 0);
2986 *masked |= ATH9K_INT_FATAL;
2988 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2989 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2990 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2993 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2994 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3000 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3002 return ah->mask_reg;
3005 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3007 u32 omask = ah->mask_reg;
3009 struct ath9k_hw_capabilities *pCap = &ah->caps;
3011 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3013 if (omask & ATH9K_INT_GLOBAL) {
3014 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3015 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3016 (void) REG_READ(ah, AR_IER);
3017 if (!AR_SREV_9100(ah)) {
3018 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3019 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3021 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3022 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3026 mask = ints & ATH9K_INT_COMMON;
3029 if (ints & ATH9K_INT_TX) {
3030 if (ah->txok_interrupt_mask)
3031 mask |= AR_IMR_TXOK;
3032 if (ah->txdesc_interrupt_mask)
3033 mask |= AR_IMR_TXDESC;
3034 if (ah->txerr_interrupt_mask)
3035 mask |= AR_IMR_TXERR;
3036 if (ah->txeol_interrupt_mask)
3037 mask |= AR_IMR_TXEOL;
3039 if (ints & ATH9K_INT_RX) {
3040 mask |= AR_IMR_RXERR;
3041 if (ah->config.intr_mitigation)
3042 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3044 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3045 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3046 mask |= AR_IMR_GENTMR;
3049 if (ints & (ATH9K_INT_BMISC)) {
3050 mask |= AR_IMR_BCNMISC;
3051 if (ints & ATH9K_INT_TIM)
3052 mask2 |= AR_IMR_S2_TIM;
3053 if (ints & ATH9K_INT_DTIM)
3054 mask2 |= AR_IMR_S2_DTIM;
3055 if (ints & ATH9K_INT_DTIMSYNC)
3056 mask2 |= AR_IMR_S2_DTIMSYNC;
3057 if (ints & ATH9K_INT_CABEND)
3058 mask2 |= AR_IMR_S2_CABEND;
3059 if (ints & ATH9K_INT_TSFOOR)
3060 mask2 |= AR_IMR_S2_TSFOOR;
3063 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3064 mask |= AR_IMR_BCNMISC;
3065 if (ints & ATH9K_INT_GTT)
3066 mask2 |= AR_IMR_S2_GTT;
3067 if (ints & ATH9K_INT_CST)
3068 mask2 |= AR_IMR_S2_CST;
3071 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3072 REG_WRITE(ah, AR_IMR, mask);
3073 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3075 AR_IMR_S2_DTIMSYNC |
3079 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3080 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3081 ah->mask_reg = ints;
3083 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3084 if (ints & ATH9K_INT_TIM_TIMER)
3085 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3087 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3090 if (ints & ATH9K_INT_GLOBAL) {
3091 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3092 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3093 if (!AR_SREV_9100(ah)) {
3094 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3096 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3099 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3100 AR_INTR_SYNC_DEFAULT);
3101 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3102 AR_INTR_SYNC_DEFAULT);
3104 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3105 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3111 /*******************/
3112 /* Beacon Handling */
3113 /*******************/
3115 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3119 ah->beacon_interval = beacon_period;
3121 switch (ah->opmode) {
3122 case NL80211_IFTYPE_STATION:
3123 case NL80211_IFTYPE_MONITOR:
3124 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3125 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3126 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3127 flags |= AR_TBTT_TIMER_EN;
3129 case NL80211_IFTYPE_ADHOC:
3130 case NL80211_IFTYPE_MESH_POINT:
3131 REG_SET_BIT(ah, AR_TXCFG,
3132 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3133 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3134 TU_TO_USEC(next_beacon +
3135 (ah->atim_window ? ah->
3137 flags |= AR_NDP_TIMER_EN;
3138 case NL80211_IFTYPE_AP:
3139 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3140 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3141 TU_TO_USEC(next_beacon -
3143 dma_beacon_response_time));
3144 REG_WRITE(ah, AR_NEXT_SWBA,
3145 TU_TO_USEC(next_beacon -
3147 sw_beacon_response_time));
3149 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3152 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3153 "%s: unsupported opmode: %d\n",
3154 __func__, ah->opmode);
3159 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3160 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3161 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3162 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3164 beacon_period &= ~ATH9K_BEACON_ENA;
3165 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3166 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3167 ath9k_hw_reset_tsf(ah);
3170 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3173 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3174 const struct ath9k_beacon_state *bs)
3176 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3177 struct ath9k_hw_capabilities *pCap = &ah->caps;
3179 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3181 REG_WRITE(ah, AR_BEACON_PERIOD,
3182 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3183 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3184 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3186 REG_RMW_FIELD(ah, AR_RSSI_THR,
3187 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3189 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3191 if (bs->bs_sleepduration > beaconintval)
3192 beaconintval = bs->bs_sleepduration;
3194 dtimperiod = bs->bs_dtimperiod;
3195 if (bs->bs_sleepduration > dtimperiod)
3196 dtimperiod = bs->bs_sleepduration;
3198 if (beaconintval == dtimperiod)
3199 nextTbtt = bs->bs_nextdtim;
3201 nextTbtt = bs->bs_nexttbtt;
3203 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3204 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3205 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3206 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3208 REG_WRITE(ah, AR_NEXT_DTIM,
3209 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3210 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3212 REG_WRITE(ah, AR_SLEEP1,
3213 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3214 | AR_SLEEP1_ASSUME_DTIM);
3216 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3217 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3219 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3221 REG_WRITE(ah, AR_SLEEP2,
3222 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3224 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3225 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3227 REG_SET_BIT(ah, AR_TIMER_MODE,
3228 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3231 /* TSF Out of Range Threshold */
3232 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3235 /*******************/
3236 /* HW Capabilities */
3237 /*******************/
3239 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3241 struct ath9k_hw_capabilities *pCap = &ah->caps;
3242 u16 capField = 0, eeval;
3244 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3245 ah->regulatory.current_rd = eeval;
3247 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3248 if (AR_SREV_9285_10_OR_LATER(ah))
3249 eeval |= AR9285_RDEXT_DEFAULT;
3250 ah->regulatory.current_rd_ext = eeval;
3252 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3254 if (ah->opmode != NL80211_IFTYPE_AP &&
3255 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3256 if (ah->regulatory.current_rd == 0x64 ||
3257 ah->regulatory.current_rd == 0x65)
3258 ah->regulatory.current_rd += 5;
3259 else if (ah->regulatory.current_rd == 0x41)
3260 ah->regulatory.current_rd = 0x43;
3261 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3262 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3265 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3266 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3268 if (eeval & AR5416_OPFLAGS_11A) {
3269 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3270 if (ah->config.ht_enable) {
3271 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3272 set_bit(ATH9K_MODE_11NA_HT20,
3273 pCap->wireless_modes);
3274 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3275 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3276 pCap->wireless_modes);
3277 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3278 pCap->wireless_modes);
3283 if (eeval & AR5416_OPFLAGS_11G) {
3284 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3285 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3286 if (ah->config.ht_enable) {
3287 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3288 set_bit(ATH9K_MODE_11NG_HT20,
3289 pCap->wireless_modes);
3290 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3291 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3292 pCap->wireless_modes);
3293 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3294 pCap->wireless_modes);
3299 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3300 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3301 !(eeval & AR5416_OPFLAGS_11A))
3302 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3304 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3306 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3307 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3309 pCap->low_2ghz_chan = 2312;
3310 pCap->high_2ghz_chan = 2732;
3312 pCap->low_5ghz_chan = 4920;
3313 pCap->high_5ghz_chan = 6100;
3315 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3316 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3317 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3319 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3320 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3321 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3323 if (ah->config.ht_enable)
3324 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3326 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3328 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3329 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3330 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3331 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3333 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3334 pCap->total_queues =
3335 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3337 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3339 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3340 pCap->keycache_size =
3341 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3343 pCap->keycache_size = AR_KEYTABLE_SIZE;
3345 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3346 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3348 if (AR_SREV_9285_10_OR_LATER(ah))
3349 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3350 else if (AR_SREV_9280_10_OR_LATER(ah))
3351 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3353 pCap->num_gpio_pins = AR_NUM_GPIO;
3355 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3356 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3357 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3359 pCap->rts_aggr_limit = (8 * 1024);
3362 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3364 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3365 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3366 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3368 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3369 ah->rfkill_polarity =
3370 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3372 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3376 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3377 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3378 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3379 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3380 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3381 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3382 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3384 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3386 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3387 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3389 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3391 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3393 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3394 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3395 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3396 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3399 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3400 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3403 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3405 pCap->num_antcfg_5ghz =
3406 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3407 pCap->num_antcfg_2ghz =
3408 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3410 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3411 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3412 ah->btactive_gpio = 6;
3413 ah->wlanactive_gpio = 5;
3417 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3418 u32 capability, u32 *result)
3421 case ATH9K_CAP_CIPHER:
3422 switch (capability) {
3423 case ATH9K_CIPHER_AES_CCM:
3424 case ATH9K_CIPHER_AES_OCB:
3425 case ATH9K_CIPHER_TKIP:
3426 case ATH9K_CIPHER_WEP:
3427 case ATH9K_CIPHER_MIC:
3428 case ATH9K_CIPHER_CLR:
3433 case ATH9K_CAP_TKIP_MIC:
3434 switch (capability) {
3438 return (ah->sta_id1_defaults &
3439 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3442 case ATH9K_CAP_TKIP_SPLIT:
3443 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3445 case ATH9K_CAP_DIVERSITY:
3446 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3447 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3449 case ATH9K_CAP_MCAST_KEYSRCH:
3450 switch (capability) {
3454 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3457 return (ah->sta_id1_defaults &
3458 AR_STA_ID1_MCAST_KSRCH) ? true :
3463 case ATH9K_CAP_TXPOW:
3464 switch (capability) {
3468 *result = ah->regulatory.power_limit;
3471 *result = ah->regulatory.max_power_level;
3474 *result = ah->regulatory.tp_scale;
3479 return (AR_SREV_9280_20_OR_LATER(ah) &&
3480 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3487 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3488 u32 capability, u32 setting, int *status)
3493 case ATH9K_CAP_TKIP_MIC:
3495 ah->sta_id1_defaults |=
3496 AR_STA_ID1_CRPT_MIC_ENABLE;
3498 ah->sta_id1_defaults &=
3499 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3501 case ATH9K_CAP_DIVERSITY:
3502 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3504 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3506 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3507 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3509 case ATH9K_CAP_MCAST_KEYSRCH:
3511 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3513 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3520 /****************************/
3521 /* GPIO / RFKILL / Antennae */
3522 /****************************/
3524 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3528 u32 gpio_shift, tmp;
3531 addr = AR_GPIO_OUTPUT_MUX3;
3533 addr = AR_GPIO_OUTPUT_MUX2;
3535 addr = AR_GPIO_OUTPUT_MUX1;
3537 gpio_shift = (gpio % 6) * 5;
3539 if (AR_SREV_9280_20_OR_LATER(ah)
3540 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3541 REG_RMW(ah, addr, (type << gpio_shift),
3542 (0x1f << gpio_shift));
3544 tmp = REG_READ(ah, addr);
3545 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3546 tmp &= ~(0x1f << gpio_shift);
3547 tmp |= (type << gpio_shift);
3548 REG_WRITE(ah, addr, tmp);
3552 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3556 ASSERT(gpio < ah->caps.num_gpio_pins);
3558 gpio_shift = gpio << 1;
3562 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3563 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3566 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3568 #define MS_REG_READ(x, y) \
3569 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3571 if (gpio >= ah->caps.num_gpio_pins)
3574 if (AR_SREV_9285_10_OR_LATER(ah))
3575 return MS_REG_READ(AR9285, gpio) != 0;
3576 else if (AR_SREV_9280_10_OR_LATER(ah))
3577 return MS_REG_READ(AR928X, gpio) != 0;
3579 return MS_REG_READ(AR, gpio) != 0;
3582 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3587 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3589 gpio_shift = 2 * gpio;
3593 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3594 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3597 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3599 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3603 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3604 void ath9k_enable_rfkill(struct ath_hw *ah)
3606 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3607 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3609 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3610 AR_GPIO_INPUT_MUX2_RFSILENT);
3612 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3613 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3617 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3619 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3622 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3624 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3627 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3628 enum ath9k_ant_setting settings,
3629 struct ath9k_channel *chan,
3634 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3636 if (AR_SREV_9280(ah)) {
3637 if (!tx_chainmask_cfg) {
3639 tx_chainmask_cfg = *tx_chainmask;
3640 rx_chainmask_cfg = *rx_chainmask;
3644 case ATH9K_ANT_FIXED_A:
3645 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3646 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3647 *antenna_cfgd = true;
3649 case ATH9K_ANT_FIXED_B:
3650 if (ah->caps.tx_chainmask >
3651 ATH9K_ANTENNA1_CHAINMASK) {
3652 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3654 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3655 *antenna_cfgd = true;
3657 case ATH9K_ANT_VARIABLE:
3658 *tx_chainmask = tx_chainmask_cfg;
3659 *rx_chainmask = rx_chainmask_cfg;
3660 *antenna_cfgd = true;
3666 ah->diversity_control = settings;
3672 /*********************/
3673 /* General Operation */
3674 /*********************/
3676 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3678 u32 bits = REG_READ(ah, AR_RX_FILTER);
3679 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3681 if (phybits & AR_PHY_ERR_RADAR)
3682 bits |= ATH9K_RX_FILTER_PHYRADAR;
3683 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3684 bits |= ATH9K_RX_FILTER_PHYERR;
3689 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3693 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3695 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3696 phybits |= AR_PHY_ERR_RADAR;
3697 if (bits & ATH9K_RX_FILTER_PHYERR)
3698 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3699 REG_WRITE(ah, AR_PHY_ERR, phybits);
3702 REG_WRITE(ah, AR_RXCFG,
3703 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3705 REG_WRITE(ah, AR_RXCFG,
3706 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3709 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3711 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3714 bool ath9k_hw_disable(struct ath_hw *ah)
3716 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3719 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3722 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3724 struct ath9k_channel *chan = ah->curchan;
3725 struct ieee80211_channel *channel = chan->chan;
3727 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3729 if (ah->eep_ops->set_txpower(ah, chan,
3730 ath9k_regd_get_ctl(&ah->regulatory, chan),
3731 channel->max_antenna_gain * 2,
3732 channel->max_power * 2,
3733 min((u32) MAX_RATE_POWER,
3734 (u32) ah->regulatory.power_limit)) != 0)
3740 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3742 memcpy(ah->macaddr, mac, ETH_ALEN);
3745 void ath9k_hw_setopmode(struct ath_hw *ah)
3747 ath9k_hw_set_operating_mode(ah, ah->opmode);
3750 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3752 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3753 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3756 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3758 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3759 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3762 void ath9k_hw_write_associd(struct ath_softc *sc)
3764 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3765 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3766 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3769 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3773 tsf = REG_READ(ah, AR_TSF_U32);
3774 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3779 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3781 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3782 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3785 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3790 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3793 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3794 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3799 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3802 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3805 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3807 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3812 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3814 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3815 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3816 ah->slottime = (u32) -1;
3819 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3825 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3829 if (mode == ATH9K_HT_MACMODE_2040 &&
3830 !ah->config.cwm_ignore_extcca)
3831 macmode = AR_2040_JOINED_RX_CLEAR;
3835 REG_WRITE(ah, AR_2040_MODE, macmode);
3838 /***************************/
3839 /* Bluetooth Coexistence */
3840 /***************************/
3842 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3844 /* connect bt_active to baseband */
3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3846 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3847 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3849 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3850 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3852 /* Set input mux for bt_active to gpio pin */
3853 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3854 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3857 /* Configure the desired gpio port for input */
3858 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3860 /* Configure the desired GPIO port for TX_FRAME output */
3861 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3862 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);