git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/sgiioc4.c

   1 /*
   2  * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it would be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11  *
  12  * You should have received a copy of the GNU General Public
  13  * License along with this program; if not, write the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  15  *
  16  * For further information regarding this notice, see:
  17  *
  18  * http://oss.sgi.com/projects/GenInfo/NoticeExplan
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/pci.h>
  24 #include <linux/delay.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/timer.h>
  29 #include <linux/mm.h>
  30 #include <linux/ioport.h>
  31 #include <linux/blkdev.h>
  32 #include <linux/ioc4.h>
  33 #include <asm/io.h>
  34
  35 #include <linux/ide.h>
  36
  37 #define DRV_NAME "SGIIOC4"
  38
  39 /* IOC4 Specific Definitions */
  40 #define IOC4_CMD_OFFSET         0x100
  41 #define IOC4_CTRL_OFFSET        0x120
  42 #define IOC4_DMA_OFFSET         0x140
  43 #define IOC4_INTR_OFFSET        0x0
  44
  45 #define IOC4_TIMING             0x00
  46 #define IOC4_DMA_PTR_L          0x01
  47 #define IOC4_DMA_PTR_H          0x02
  48 #define IOC4_DMA_ADDR_L         0x03
  49 #define IOC4_DMA_ADDR_H         0x04
  50 #define IOC4_BC_DEV             0x05
  51 #define IOC4_BC_MEM             0x06
  52 #define IOC4_DMA_CTRL           0x07
  53 #define IOC4_DMA_END_ADDR       0x08
  54
  55 /* Bits in the IOC4 Control/Status Register */
  56 #define IOC4_S_DMA_START        0x01
  57 #define IOC4_S_DMA_STOP         0x02
  58 #define IOC4_S_DMA_DIR          0x04
  59 #define IOC4_S_DMA_ACTIVE       0x08
  60 #define IOC4_S_DMA_ERROR        0x10
  61 #define IOC4_ATA_MEMERR         0x02
  62
  63 /* Read/Write Directions */
  64 #define IOC4_DMA_WRITE          0x04
  65 #define IOC4_DMA_READ           0x00
  66
  67 /* Interrupt Register Offsets */
  68 #define IOC4_INTR_REG           0x03
  69 #define IOC4_INTR_SET           0x05
  70 #define IOC4_INTR_CLEAR         0x07
  71
  72 #define IOC4_IDE_CACHELINE_SIZE 128
  73 #define IOC4_CMD_CTL_BLK_SIZE   0x20
  74 #define IOC4_SUPPORTED_FIRMWARE_REV 46
  75
  76 typedef struct {
  77         u32 timing_reg0;
  78         u32 timing_reg1;
  79         u32 low_mem_ptr;
  80         u32 high_mem_ptr;
  81         u32 low_mem_addr;
  82         u32 high_mem_addr;
  83         u32 dev_byte_count;
  84         u32 mem_byte_count;
  85         u32 status;
  86 } ioc4_dma_regs_t;
  87
  88 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
  89 /* IOC4 has only 1 IDE channel */
  90 #define IOC4_PRD_BYTES       16
  91 #define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
  92
  93
  94 static void
  95 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
  96                         unsigned long ctrl_port, unsigned long irq_port)
  97 {
  98         unsigned long reg = data_port;
  99         int i;
 100
 101         /* Registers are word (32 bit) aligned */
 102         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 103                 hw->io_ports[i] = reg + i * 4;
 104
 105         if (ctrl_port)
 106                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 107
 108         if (irq_port)
 109                 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
 110 }
 111
 112 static void
 113 sgiioc4_maskproc(ide_drive_t * drive, int mask)
 114 {
 115         writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 116                (void __iomem *)IDE_CONTROL_REG);
 117 }
 118
 119
 120 static int
 121 sgiioc4_checkirq(ide_hwif_t * hwif)
 122 {
 123         unsigned long intr_addr =
 124                 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
 125
 126         if ((u8)readl((void __iomem *)intr_addr) & 0x03)
 127                 return 1;
 128
 129         return 0;
 130 }
 131
 132 static u8 sgiioc4_INB(unsigned long);
 133
 134 static int
 135 sgiioc4_clearirq(ide_drive_t * drive)
 136 {
 137         u32 intr_reg;
 138         ide_hwif_t *hwif = HWIF(drive);
 139         unsigned long other_ir =
 140             hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
 141
 142         /* Code to check for PCI error conditions */
 143         intr_reg = readl((void __iomem *)other_ir);
 144         if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
 145                 /*
 146                  * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
 147                  * of clearing the interrupt.  The first read should clear it
 148                  * if it is set.  The second read should return a "clear" status
 149                  * if it got cleared.  If not, then spin for a bit trying to
 150                  * clear it.
 151                  */
 152                 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
 153                 int count = 0;
 154                 stat = sgiioc4_INB(IDE_STATUS_REG);
 155                 while ((stat & 0x80) && (count++ < 100)) {
 156                         udelay(1);
 157                         stat = sgiioc4_INB(IDE_STATUS_REG);
 158                 }
 159
 160                 if (intr_reg & 0x02) {
 161                         /* Error when transferring DMA data on PCI bus */
 162                         u32 pci_err_addr_low, pci_err_addr_high,
 163                             pci_stat_cmd_reg;
 164
 165                         pci_err_addr_low =
 166                                 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
 167                         pci_err_addr_high =
 168                                 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
 169                         pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
 170                                               &pci_stat_cmd_reg);
 171                         printk(KERN_ERR
 172                                "%s(%s) : PCI Bus Error when doing DMA:"
 173                                    " status-cmd reg is 0x%x\n",
 174                                __FUNCTION__, drive->name, pci_stat_cmd_reg);
 175                         printk(KERN_ERR
 176                                "%s(%s) : PCI Error Address is 0x%x%x\n",
 177                                __FUNCTION__, drive->name,
 178                                pci_err_addr_high, pci_err_addr_low);
 179                         /* Clear the PCI Error indicator */
 180                         pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
 181                                                0x00000146);
 182                 }
 183
 184                 /* Clear the Interrupt, Error bits on the IOC4 */
 185                 writel(0x03, (void __iomem *)other_ir);
 186
 187                 intr_reg = readl((void __iomem *)other_ir);
 188         }
 189
 190         return intr_reg & 3;
 191 }
 192
 193 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
 194 {
 195         ide_hwif_t *hwif = HWIF(drive);
 196         unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
 197         unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
 198         unsigned int temp_reg = reg | IOC4_S_DMA_START;
 199
 200         writel(temp_reg, (void __iomem *)ioc4_dma_addr);
 201 }
 202
 203 static u32
 204 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
 205 {
 206         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 207         u32     ioc4_dma;
 208         int     count;
 209
 210         count = 0;
 211         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 212         while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
 213                 udelay(1);
 214                 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 215         }
 216         return ioc4_dma;
 217 }
 218
 219 /* Stops the IOC4 DMA Engine */
 220 static int
 221 sgiioc4_ide_dma_end(ide_drive_t * drive)
 222 {
 223         u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
 224         ide_hwif_t *hwif = HWIF(drive);
 225         unsigned long dma_base = hwif->dma_base;
 226         int dma_stat = 0;
 227         unsigned long *ending_dma = ide_get_hwifdata(hwif);
 228
 229         writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
 230
 231         ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 232
 233         if (ioc4_dma & IOC4_S_DMA_STOP) {
 234                 printk(KERN_ERR
 235                        "%s(%s): IOC4 DMA STOP bit is still 1 :"
 236                        "ioc4_dma_reg 0x%x\n",
 237                        __FUNCTION__, drive->name, ioc4_dma);
 238                 dma_stat = 1;
 239         }
 240
 241         /*
 242          * The IOC4 will DMA 1's to the ending dma area to indicate that
 243          * previous data DMA is complete.  This is necessary because of relaxed
 244          * ordering between register reads and DMA writes on the Altix.
 245          */
 246         while ((cnt++ < 200) && (!valid)) {
 247                 for (num = 0; num < 16; num++) {
 248                         if (ending_dma[num]) {
 249                                 valid = 1;
 250                                 break;
 251                         }
 252                 }
 253                 udelay(1);
 254         }
 255         if (!valid) {
 256                 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
 257                        drive->name);
 258                 dma_stat = 1;
 259         }
 260
 261         bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
 262         bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
 263
 264         if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
 265                 if (bc_dev > bc_mem + 8) {
 266                         printk(KERN_ERR
 267                                "%s(%s): WARNING!! byte_count_dev %d "
 268                                "!= byte_count_mem %d\n",
 269                                __FUNCTION__, drive->name, bc_dev, bc_mem);
 270                 }
 271         }
 272
 273         drive->waiting_for_dma = 0;
 274         ide_destroy_dmatable(drive);
 275
 276         return dma_stat;
 277 }
 278
 279 static int
 280 sgiioc4_ide_dma_on(ide_drive_t * drive)
 281 {
 282         drive->using_dma = 1;
 283
 284         return 0;
 285 }
 286
 287 static void sgiioc4_dma_off_quietly(ide_drive_t *drive)
 288 {
 289         drive->using_dma = 0;
 290
 291         drive->hwif->dma_host_off(drive);
 292 }
 293
 294 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
 295 {
 296 }
 297
 298 static int sgiioc4_ide_dma_check(ide_drive_t *drive)
 299 {
 300         if (ide_tune_dma(drive))
 301                 return 0;
 302
 303         /*
 304          * ->set_pio_mode is not implemented currently
 305          * so this is just for the completness
 306          */
 307         ide_set_max_pio(drive);
 308
 309         return -1;
 310 }
 311
 312 /* returns 1 if dma irq issued, 0 otherwise */
 313 static int
 314 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
 315 {
 316         return sgiioc4_checkirq(HWIF(drive));
 317 }
 318
 319 static void sgiioc4_dma_host_on(ide_drive_t * drive)
 320 {
 321 }
 322
 323 static void sgiioc4_dma_host_off(ide_drive_t * drive)
 324 {
 325         sgiioc4_clearirq(drive);
 326 }
 327
 328 static void
 329 sgiioc4_resetproc(ide_drive_t * drive)
 330 {
 331         sgiioc4_ide_dma_end(drive);
 332         sgiioc4_clearirq(drive);
 333 }
 334
 335 static void
 336 sgiioc4_dma_lost_irq(ide_drive_t * drive)
 337 {
 338         sgiioc4_resetproc(drive);
 339
 340         ide_dma_lost_irq(drive);
 341 }
 342
 343 static u8
 344 sgiioc4_INB(unsigned long port)
 345 {
 346         u8 reg = (u8) readb((void __iomem *) port);
 347
 348         if ((port & 0xFFF) == 0x11C) {  /* Status register of IOC4 */
 349                 if (reg & 0x51) {       /* Not busy...check for interrupt */
 350                         unsigned long other_ir = port - 0x110;
 351                         unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
 352
 353                         /* Clear the Interrupt, Error bits on the IOC4 */
 354                         if (intr_reg & 0x03) {
 355                                 writel(0x03, (void __iomem *) other_ir);
 356                                 intr_reg = (u32) readl((void __iomem *) other_ir);
 357                         }
 358                 }
 359         }
 360
 361         return reg;
 362 }
 363
 364 /* Creates a dma map for the scatter-gather list entries */
 365 static int __devinit
 366 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
 367 {
 368         void __iomem *virt_dma_base;
 369         int num_ports = sizeof (ioc4_dma_regs_t);
 370         void *pad;
 371
 372         printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
 373                dma_base, dma_base + num_ports - 1);
 374
 375         if (!request_mem_region(dma_base, num_ports, hwif->name)) {
 376                 printk(KERN_ERR
 377                        "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
 378                        "ALREADY in use\n",
 379                        __FUNCTION__, hwif->name, (void *) dma_base,
 380                        (void *) dma_base + num_ports - 1);
 381                 return -1;
 382         }
 383
 384         virt_dma_base = ioremap(dma_base, num_ports);
 385         if (virt_dma_base == NULL) {
 386                 printk(KERN_ERR
 387                        "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
 388                        __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
 389                 goto dma_remap_failure;
 390         }
 391         hwif->dma_base = (unsigned long) virt_dma_base;
 392
 393         hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
 394                                           IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 395                                           &hwif->dmatable_dma);
 396
 397         if (!hwif->dmatable_cpu)
 398                 goto dma_pci_alloc_failure;
 399
 400         hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 401
 402         pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
 403                                    (dma_addr_t *) &(hwif->dma_status));
 404
 405         if (pad) {
 406                 ide_set_hwifdata(hwif, pad);
 407                 return 0;
 408         }
 409
 410         pci_free_consistent(hwif->pci_dev,
 411                             IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 412                             hwif->dmatable_cpu, hwif->dmatable_dma);
 413         printk(KERN_INFO
 414                "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
 415                __FUNCTION__, hwif->name);
 416         printk(KERN_INFO
 417                "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
 418
 419 dma_pci_alloc_failure:
 420         iounmap(virt_dma_base);
 421
 422 dma_remap_failure:
 423         release_mem_region(dma_base, num_ports);
 424
 425         return -1;
 426 }
 427
 428 /* Initializes the IOC4 DMA Engine */
 429 static void
 430 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
 431 {
 432         u32 ioc4_dma;
 433         ide_hwif_t *hwif = HWIF(drive);
 434         unsigned long dma_base = hwif->dma_base;
 435         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 436         u32 dma_addr, ending_dma_addr;
 437
 438         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 439
 440         if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
 441                 printk(KERN_WARNING
 442                         "%s(%s):Warning!! DMA from previous transfer was still active\n",
 443                        __FUNCTION__, drive->name);
 444                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 445                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 446
 447                 if (ioc4_dma & IOC4_S_DMA_STOP)
 448                         printk(KERN_ERR
 449                                "%s(%s) : IOC4 Dma STOP bit is still 1\n",
 450                                __FUNCTION__, drive->name);
 451         }
 452
 453         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 454         if (ioc4_dma & IOC4_S_DMA_ERROR) {
 455                 printk(KERN_WARNING
 456                        "%s(%s) : Warning!! - DMA Error during Previous"
 457                        " transfer | status 0x%x\n",
 458                        __FUNCTION__, drive->name, ioc4_dma);
 459                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 460                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 461
 462                 if (ioc4_dma & IOC4_S_DMA_STOP)
 463                         printk(KERN_ERR
 464                                "%s(%s) : IOC4 DMA STOP bit is still 1\n",
 465                                __FUNCTION__, drive->name);
 466         }
 467
 468         /* Address of the Scatter Gather List */
 469         dma_addr = cpu_to_le32(hwif->dmatable_dma);
 470         writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
 471
 472         /* Address of the Ending DMA */
 473         memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
 474         ending_dma_addr = cpu_to_le32(hwif->dma_status);
 475         writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
 476
 477         writel(dma_direction, (void __iomem *)ioc4_dma_addr);
 478         drive->waiting_for_dma = 1;
 479 }
 480
 481 /* IOC4 Scatter Gather list Format                                       */
 482 /* 128 Bit entries to support 64 bit addresses in the future             */
 483 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
 484 /* --------------------------------------------------------------------- */
 485 /* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
 486 /* --------------------------------------------------------------------- */
 487 /* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
 488 /* --------------------------------------------------------------------- */
 489 /* Creates the scatter gather list, DMA Table */
 490 static unsigned int
 491 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
 492 {
 493         ide_hwif_t *hwif = HWIF(drive);
 494         unsigned int *table = hwif->dmatable_cpu;
 495         unsigned int count = 0, i = 1;
 496         struct scatterlist *sg;
 497
 498         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 499
 500         if (!i)
 501                 return 0;       /* sglist of length Zero */
 502
 503         sg = hwif->sg_table;
 504         while (i && sg_dma_len(sg)) {
 505                 dma_addr_t cur_addr;
 506                 int cur_len;
 507                 cur_addr = sg_dma_address(sg);
 508                 cur_len = sg_dma_len(sg);
 509
 510                 while (cur_len) {
 511                         if (count++ >= IOC4_PRD_ENTRIES) {
 512                                 printk(KERN_WARNING
 513                                        "%s: DMA table too small\n",
 514                                        drive->name);
 515                                 goto use_pio_instead;
 516                         } else {
 517                                 u32 bcount =
 518                                     0x10000 - (cur_addr & 0xffff);
 519
 520                                 if (bcount > cur_len)
 521                                         bcount = cur_len;
 522
 523                                 /* put the addr, length in
 524                                  * the IOC4 dma-table format */
 525                                 *table = 0x0;
 526                                 table++;
 527                                 *table = cpu_to_be32(cur_addr);
 528                                 table++;
 529                                 *table = 0x0;
 530                                 table++;
 531
 532                                 *table = cpu_to_be32(bcount);
 533                                 table++;
 534
 535                                 cur_addr += bcount;
 536                                 cur_len -= bcount;
 537                         }
 538                 }
 539
 540                 sg++;
 541                 i--;
 542         }
 543
 544         if (count) {
 545                 table--;
 546                 *table |= cpu_to_be32(0x80000000);
 547                 return count;
 548         }
 549
 550 use_pio_instead:
 551         pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
 552                      hwif->sg_dma_direction);
 553
 554         return 0;               /* revert to PIO for this request */
 555 }
 556
 557 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
 558 {
 559         struct request *rq = HWGROUP(drive)->rq;
 560         unsigned int count = 0;
 561         int ddir;
 562
 563         if (rq_data_dir(rq))
 564                 ddir = PCI_DMA_TODEVICE;
 565         else
 566                 ddir = PCI_DMA_FROMDEVICE;
 567
 568         if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
 569                 /* try PIO instead of DMA */
 570                 ide_map_sg(drive, rq);
 571                 return 1;
 572         }
 573
 574         if (rq_data_dir(rq))
 575                 /* Writes TO the IOC4 FROM Main Memory */
 576                 ddir = IOC4_DMA_READ;
 577         else
 578                 /* Writes FROM the IOC4 TO Main Memory */
 579                 ddir = IOC4_DMA_WRITE;
 580
 581         sgiioc4_configure_for_dma(ddir, drive);
 582
 583         return 0;
 584 }
 585
 586 static void __devinit
 587 ide_init_sgiioc4(ide_hwif_t * hwif)
 588 {
 589         hwif->mmio = 1;
 590         hwif->atapi_dma = 1;
 591         hwif->mwdma_mask = 0x04;
 592         hwif->pio_mask = 0x00;
 593         hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */
 594         hwif->set_dma_mode = &sgiioc4_set_dma_mode;
 595         hwif->selectproc = NULL;/* Use the default routine to select drive */
 596         hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
 597         hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
 598         hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
 599                                                 clear interrupts */
 600         hwif->intrproc = NULL;  /* Enable or Disable interrupt from drive */
 601         hwif->maskproc = &sgiioc4_maskproc;     /* Mask on/off NIEN register */
 602         hwif->quirkproc = NULL;
 603         hwif->busproc = NULL;
 604
 605         hwif->dma_setup = &sgiioc4_ide_dma_setup;
 606         hwif->dma_start = &sgiioc4_ide_dma_start;
 607         hwif->ide_dma_end = &sgiioc4_ide_dma_end;
 608         hwif->ide_dma_check = &sgiioc4_ide_dma_check;
 609         hwif->ide_dma_on = &sgiioc4_ide_dma_on;
 610         hwif->dma_off_quietly = &sgiioc4_dma_off_quietly;
 611         hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
 612         hwif->dma_host_on = &sgiioc4_dma_host_on;
 613         hwif->dma_host_off = &sgiioc4_dma_host_off;
 614         hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
 615         hwif->dma_timeout = &ide_dma_timeout;
 616
 617         hwif->INB = &sgiioc4_INB;
 618 }
 619
 620 static int __devinit
 621 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
 622 {
 623         unsigned long cmd_base, dma_base, irqport;
 624         unsigned long bar0, cmd_phys_base, ctl;
 625         void __iomem *virt_base;
 626         ide_hwif_t *hwif;
 627         int h;
 628
 629         /*
 630          * Find an empty HWIF; if none available, return -ENOMEM.
 631          */
 632         for (h = 0; h < MAX_HWIFS; ++h) {
 633                 hwif = &ide_hwifs[h];
 634                 if (hwif->chipset == ide_unknown)
 635                         break;
 636         }
 637         if (h == MAX_HWIFS) {
 638                 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
 639                                 DRV_NAME);
 640                 return -ENOMEM;
 641         }
 642
 643         /*  Get the CmdBlk and CtrlBlk Base Registers */
 644         bar0 = pci_resource_start(dev, 0);
 645         virt_base = ioremap(bar0, pci_resource_len(dev, 0));
 646         if (virt_base == NULL) {
 647                 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
 648                                 DRV_NAME, bar0);
 649                 return -ENOMEM;
 650         }
 651         cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
 652         ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
 653         irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
 654         dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
 655
 656         cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
 657         if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
 658             hwif->name)) {
 659                 printk(KERN_ERR
 660                         "%s : %s -- ERROR, Addresses "
 661                         "0x%p to 0x%p ALREADY in use\n",
 662                        __FUNCTION__, hwif->name, (void *) cmd_phys_base,
 663                        (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
 664                 return -ENOMEM;
 665         }
 666
 667         if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
 668                 /* Initialize the IO registers */
 669                 sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport);
 670                 memcpy(hwif->io_ports, hwif->hw.io_ports,
 671                        sizeof (hwif->io_ports));
 672                 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
 673         }
 674
 675         hwif->irq = dev->irq;
 676         hwif->chipset = ide_pci;
 677         hwif->pci_dev = dev;
 678         hwif->channel = 0;      /* Single Channel chip */
 679         hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
 680
 681         /* The IOC4 uses MMIO rather than Port IO. */
 682         default_hwif_mmiops(hwif);
 683
 684         /* Initializing chipset IRQ Registers */
 685         writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
 686
 687         ide_init_sgiioc4(hwif);
 688
 689         hwif->autodma = 0;
 690
 691         if (dma_base && ide_dma_sgiioc4(hwif, dma_base) == 0) {
 692                 hwif->autodma = 1;
 693                 hwif->drives[1].autodma = hwif->drives[0].autodma = 1;
 694         } else
 695                 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
 696                                  hwif->name, DRV_NAME);
 697
 698         if (probe_hwif_init(hwif))
 699                 return -EIO;
 700
 701         /* Create /proc/ide entries */
 702         ide_proc_register_port(hwif);
 703
 704         return 0;
 705 }
 706
 707 static unsigned int __devinit
 708 pci_init_sgiioc4(struct pci_dev *dev)
 709 {
 710         unsigned int class_rev;
 711         int ret;
 712
 713         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 714         class_rev &= 0xff;
 715         printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
 716                          DRV_NAME, pci_name(dev), class_rev);
 717         if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
 718                 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
 719                                 "firmware is obsolete - please upgrade to "
 720                                 "revision46 or higher\n",
 721                                 DRV_NAME, pci_name(dev));
 722                 ret = -EAGAIN;
 723                 goto out;
 724         }
 725         ret = sgiioc4_ide_setup_pci_device(dev);
 726 out:
 727         return ret;
 728 }
 729
 730 int
 731 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
 732 {
 733         /* PCI-RT does not bring out IDE connection.
 734          * Do not attach to this particular IOC4.
 735          */
 736         if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
 737                 return 0;
 738
 739         return pci_init_sgiioc4(idd->idd_pdev);
 740 }
 741
 742 static struct ioc4_submodule ioc4_ide_submodule = {
 743         .is_name = "IOC4_ide",
 744         .is_owner = THIS_MODULE,
 745         .is_probe = ioc4_ide_attach_one,
 746 /*      .is_remove = ioc4_ide_remove_one,       */
 747 };
 748
 749 static int __init ioc4_ide_init(void)
 750 {
 751         return ioc4_register_submodule(&ioc4_ide_submodule);
 752 }
 753
 754 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
 755
 756 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
 757 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
 758 MODULE_LICENSE("GPL");