git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/log2.h>
  34
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_pack.h>
  37
  38 #include <linux/mlx4/qp.h>
  39
  40 #include "mlx4_ib.h"
  41 #include "user.h"
  42
  43 enum {
  44         MLX4_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  50 };
  51
  52 enum {
  53         /*
  54          * Largest possible UD header: send with GRH and immediate data.
  55          */
  56         MLX4_IB_UD_HEADER_SIZE          = 72
  57 };
  58
  59 struct mlx4_ib_sqp {
  60         struct mlx4_ib_qp       qp;
  61         int                     pkey_index;
  62         u32                     qkey;
  63         u32                     send_psn;
  64         struct ib_ud_header     ud_header;
  65         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  66 };
  67
  68 enum {
  69         MLX4_IB_MIN_SQ_STRIDE = 6
  70 };
  71
  72 static const __be32 mlx4_ib_opcode[] = {
  73         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  74         [IB_WR_LSO]                     = __constant_cpu_to_be32(MLX4_OPCODE_LSO),
  75         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  76         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  77         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  78         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  79         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  80         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  81         [IB_WR_SEND_WITH_INV]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
  82         [IB_WR_LOCAL_INV]               = __constant_cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
  83         [IB_WR_FAST_REG_MR]             = __constant_cpu_to_be32(MLX4_OPCODE_FMR),
  84 };
  85
  86 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  87 {
  88         return container_of(mqp, struct mlx4_ib_sqp, qp);
  89 }
  90
  91 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  92 {
  93         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  94                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  95 }
  96
  97 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  98 {
  99         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 100                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
 101 }
 102
 103 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 104 {
 105         return mlx4_buf_offset(&qp->buf, offset);
 106 }
 107
 108 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 111 }
 112
 113 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 114 {
 115         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 116 }
 117
 118 /*
 119  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 120  * first four bytes of every 64 byte chunk with
 121  *     0x7FFFFFF | (invalid_ownership_value << 31).
 122  *
 123  * When the max work request size is less than or equal to the WQE
 124  * basic block size, as an optimization, we can stamp all WQEs with
 125  * 0xffffffff, and skip the very first chunk of each WQE.
 126  */
 127 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 128 {
 129         __be32 *wqe;
 130         int i;
 131         int s;
 132         int ind;
 133         void *buf;
 134         __be32 stamp;
 135         struct mlx4_wqe_ctrl_seg *ctrl;
 136
 137         if (qp->sq_max_wqes_per_wr > 1) {
 138                 s = roundup(size, 1U << qp->sq.wqe_shift);
 139                 for (i = 0; i < s; i += 64) {
 140                         ind = (i >> qp->sq.wqe_shift) + n;
 141                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 142                                                        cpu_to_be32(0xffffffff);
 143                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 144                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 145                         *wqe = stamp;
 146                 }
 147         } else {
 148                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 149                 s = (ctrl->fence_size & 0x3f) << 4;
 150                 for (i = 64; i < s; i += 64) {
 151                         wqe = buf + i;
 152                         *wqe = cpu_to_be32(0xffffffff);
 153                 }
 154         }
 155 }
 156
 157 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 158 {
 159         struct mlx4_wqe_ctrl_seg *ctrl;
 160         struct mlx4_wqe_inline_seg *inl;
 161         void *wqe;
 162         int s;
 163
 164         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 165         s = sizeof(struct mlx4_wqe_ctrl_seg);
 166
 167         if (qp->ibqp.qp_type == IB_QPT_UD) {
 168                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 169                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 170                 memset(dgram, 0, sizeof *dgram);
 171                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 172                 s += sizeof(struct mlx4_wqe_datagram_seg);
 173         }
 174
 175         /* Pad the remainder of the WQE with an inline data segment. */
 176         if (size > s) {
 177                 inl = wqe + s;
 178                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 179         }
 180         ctrl->srcrb_flags = 0;
 181         ctrl->fence_size = size / 16;
 182         /*
 183          * Make sure descriptor is fully written before setting ownership bit
 184          * (because HW can start executing as soon as we do).
 185          */
 186         wmb();
 187
 188         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 189                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 190
 191         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 192 }
 193
 194 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 195 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 196 {
 197         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 198         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 199                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 200                 ind += s;
 201         }
 202         return ind;
 203 }
 204
 205 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 206 {
 207         struct ib_event event;
 208         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 209
 210         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 211                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 212
 213         if (ibqp->event_handler) {
 214                 event.device     = ibqp->device;
 215                 event.element.qp = ibqp;
 216                 switch (type) {
 217                 case MLX4_EVENT_TYPE_PATH_MIG:
 218                         event.event = IB_EVENT_PATH_MIG;
 219                         break;
 220                 case MLX4_EVENT_TYPE_COMM_EST:
 221                         event.event = IB_EVENT_COMM_EST;
 222                         break;
 223                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 224                         event.event = IB_EVENT_SQ_DRAINED;
 225                         break;
 226                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 227                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 228                         break;
 229                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 230                         event.event = IB_EVENT_QP_FATAL;
 231                         break;
 232                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 233                         event.event = IB_EVENT_PATH_MIG_ERR;
 234                         break;
 235                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 236                         event.event = IB_EVENT_QP_REQ_ERR;
 237                         break;
 238                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 239                         event.event = IB_EVENT_QP_ACCESS_ERR;
 240                         break;
 241                 default:
 242                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 243                                "on QP %06x\n", type, qp->qpn);
 244                         return;
 245                 }
 246
 247                 ibqp->event_handler(&event, ibqp->qp_context);
 248         }
 249 }
 250
 251 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
 252 {
 253         /*
 254          * UD WQEs must have a datagram segment.
 255          * RC and UC WQEs might have a remote address segment.
 256          * MLX WQEs need two extra inline data segments (for the UD
 257          * header and space for the ICRC).
 258          */
 259         switch (type) {
 260         case IB_QPT_UD:
 261                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 262                         sizeof (struct mlx4_wqe_datagram_seg) +
 263                         ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
 264         case IB_QPT_UC:
 265                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 266                         sizeof (struct mlx4_wqe_raddr_seg);
 267         case IB_QPT_RC:
 268                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 269                         sizeof (struct mlx4_wqe_atomic_seg) +
 270                         sizeof (struct mlx4_wqe_raddr_seg);
 271         case IB_QPT_SMI:
 272         case IB_QPT_GSI:
 273                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 274                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 275                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 276                                            MLX4_INLINE_ALIGN) *
 277                               sizeof (struct mlx4_wqe_inline_seg),
 278                               sizeof (struct mlx4_wqe_data_seg)) +
 279                         ALIGN(4 +
 280                               sizeof (struct mlx4_wqe_inline_seg),
 281                               sizeof (struct mlx4_wqe_data_seg));
 282         default:
 283                 return sizeof (struct mlx4_wqe_ctrl_seg);
 284         }
 285 }
 286
 287 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 288                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 289 {
 290         /* Sanity check RQ size before proceeding */
 291         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 292             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 293                 return -EINVAL;
 294
 295         if (has_srq) {
 296                 /* QPs attached to an SRQ should have no RQ */
 297                 if (cap->max_recv_wr)
 298                         return -EINVAL;
 299
 300                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 301         } else {
 302                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 303                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 304                         return -EINVAL;
 305
 306                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 307                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 308                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 309         }
 310
 311         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 312         cap->max_recv_sge = qp->rq.max_gs;
 313
 314         return 0;
 315 }
 316
 317 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 318                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 319 {
 320         int s;
 321
 322         /* Sanity check SQ size before proceeding */
 323         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 324             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 325             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 326             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 327                 return -EINVAL;
 328
 329         /*
 330          * For MLX transport we need 2 extra S/G entries:
 331          * one for the header and one for the checksum at the end
 332          */
 333         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 334             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 335                 return -EINVAL;
 336
 337         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 338                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 339                 send_wqe_overhead(type, qp->flags);
 340
 341         if (s > dev->dev->caps.max_sq_desc_sz)
 342                 return -EINVAL;
 343
 344         /*
 345          * Hermon supports shrinking WQEs, such that a single work
 346          * request can include multiple units of 1 << wqe_shift.  This
 347          * way, work requests can differ in size, and do not have to
 348          * be a power of 2 in size, saving memory and speeding up send
 349          * WR posting.  Unfortunately, if we do this then the
 350          * wqe_index field in CQEs can't be used to look up the WR ID
 351          * anymore, so we do this only if selective signaling is off.
 352          *
 353          * Further, on 32-bit platforms, we can't use vmap() to make
 354          * the QP buffer virtually contigious.  Thus we have to use
 355          * constant-sized WRs to make sure a WR is always fully within
 356          * a single page-sized chunk.
 357          *
 358          * Finally, we use NOP work requests to pad the end of the
 359          * work queue, to avoid wrap-around in the middle of WR.  We
 360          * set NEC bit to avoid getting completions with error for
 361          * these NOP WRs, but since NEC is only supported starting
 362          * with firmware 2.2.232, we use constant-sized WRs for older
 363          * firmware.
 364          *
 365          * And, since MLX QPs only support SEND, we use constant-sized
 366          * WRs in this case.
 367          *
 368          * We look for the smallest value of wqe_shift such that the
 369          * resulting number of wqes does not exceed device
 370          * capabilities.
 371          *
 372          * We set WQE size to at least 64 bytes, this way stamping
 373          * invalidates each WQE.
 374          */
 375         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 376             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 377             type != IB_QPT_SMI && type != IB_QPT_GSI)
 378                 qp->sq.wqe_shift = ilog2(64);
 379         else
 380                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 381
 382         for (;;) {
 383                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 384
 385                 /*
 386                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 387                  * allow HW to prefetch.
 388                  */
 389                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 390                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 391                                                     qp->sq_max_wqes_per_wr +
 392                                                     qp->sq_spare_wqes);
 393
 394                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 395                         break;
 396
 397                 if (qp->sq_max_wqes_per_wr <= 1)
 398                         return -EINVAL;
 399
 400                 ++qp->sq.wqe_shift;
 401         }
 402
 403         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 404                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 405                          send_wqe_overhead(type, qp->flags)) /
 406                 sizeof (struct mlx4_wqe_data_seg);
 407
 408         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 409                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 410         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 411                 qp->rq.offset = 0;
 412                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 413         } else {
 414                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 415                 qp->sq.offset = 0;
 416         }
 417
 418         cap->max_send_wr  = qp->sq.max_post =
 419                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 420         cap->max_send_sge = min(qp->sq.max_gs,
 421                                 min(dev->dev->caps.max_sq_sg,
 422                                     dev->dev->caps.max_rq_sg));
 423         /* We don't support inline sends for kernel QPs (yet) */
 424         cap->max_inline_data = 0;
 425
 426         return 0;
 427 }
 428
 429 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 430                             struct mlx4_ib_qp *qp,
 431                             struct mlx4_ib_create_qp *ucmd)
 432 {
 433         /* Sanity check SQ size before proceeding */
 434         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 435             ucmd->log_sq_stride >
 436                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 437             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 438                 return -EINVAL;
 439
 440         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 441         qp->sq.wqe_shift = ucmd->log_sq_stride;
 442
 443         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 444                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 445
 446         return 0;
 447 }
 448
 449 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 450                             struct ib_qp_init_attr *init_attr,
 451                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 452 {
 453         int err;
 454
 455         mutex_init(&qp->mutex);
 456         spin_lock_init(&qp->sq.lock);
 457         spin_lock_init(&qp->rq.lock);
 458
 459         qp->state        = IB_QPS_RESET;
 460         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 461                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 462
 463         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 464         if (err)
 465                 goto err;
 466
 467         if (pd->uobject) {
 468                 struct mlx4_ib_create_qp ucmd;
 469
 470                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 471                         err = -EFAULT;
 472                         goto err;
 473                 }
 474
 475                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 476
 477                 err = set_user_sq_size(dev, qp, &ucmd);
 478                 if (err)
 479                         goto err;
 480
 481                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 482                                        qp->buf_size, 0, 0);
 483                 if (IS_ERR(qp->umem)) {
 484                         err = PTR_ERR(qp->umem);
 485                         goto err;
 486                 }
 487
 488                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 489                                     ilog2(qp->umem->page_size), &qp->mtt);
 490                 if (err)
 491                         goto err_buf;
 492
 493                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 494                 if (err)
 495                         goto err_mtt;
 496
 497                 if (!init_attr->srq) {
 498                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 499                                                   ucmd.db_addr, &qp->db);
 500                         if (err)
 501                                 goto err_mtt;
 502                 }
 503         } else {
 504                 qp->sq_no_prefetch = 0;
 505
 506                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 507                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 508
 509                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 510                         qp->flags |= MLX4_IB_QP_LSO;
 511
 512                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 513                 if (err)
 514                         goto err;
 515
 516                 if (!init_attr->srq) {
 517                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 518                         if (err)
 519                                 goto err;
 520
 521                         *qp->db.db = 0;
 522                 }
 523
 524                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 525                         err = -ENOMEM;
 526                         goto err_db;
 527                 }
 528
 529                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 530                                     &qp->mtt);
 531                 if (err)
 532                         goto err_buf;
 533
 534                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 535                 if (err)
 536                         goto err_mtt;
 537
 538                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 539                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 540
 541                 if (!qp->sq.wrid || !qp->rq.wrid) {
 542                         err = -ENOMEM;
 543                         goto err_wrid;
 544                 }
 545         }
 546
 547         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 548         if (err)
 549                 goto err_wrid;
 550
 551         /*
 552          * Hardware wants QPN written in big-endian order (after
 553          * shifting) for send doorbell.  Precompute this value to save
 554          * a little bit when posting sends.
 555          */
 556         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 557
 558         qp->mqp.event = mlx4_ib_qp_event;
 559
 560         return 0;
 561
 562 err_wrid:
 563         if (pd->uobject) {
 564                 if (!init_attr->srq)
 565                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 566                                               &qp->db);
 567         } else {
 568                 kfree(qp->sq.wrid);
 569                 kfree(qp->rq.wrid);
 570         }
 571
 572 err_mtt:
 573         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 574
 575 err_buf:
 576         if (pd->uobject)
 577                 ib_umem_release(qp->umem);
 578         else
 579                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 580
 581 err_db:
 582         if (!pd->uobject && !init_attr->srq)
 583                 mlx4_db_free(dev->dev, &qp->db);
 584
 585 err:
 586         return err;
 587 }
 588
 589 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 590 {
 591         switch (state) {
 592         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 593         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 594         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 595         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 596         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 597         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 598         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 599         default:                return -1;
 600         }
 601 }
 602
 603 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 604 {
 605         if (send_cq == recv_cq)
 606                 spin_lock_irq(&send_cq->lock);
 607         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 608                 spin_lock_irq(&send_cq->lock);
 609                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 610         } else {
 611                 spin_lock_irq(&recv_cq->lock);
 612                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 613         }
 614 }
 615
 616 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 617 {
 618         if (send_cq == recv_cq)
 619                 spin_unlock_irq(&send_cq->lock);
 620         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 621                 spin_unlock(&recv_cq->lock);
 622                 spin_unlock_irq(&send_cq->lock);
 623         } else {
 624                 spin_unlock(&send_cq->lock);
 625                 spin_unlock_irq(&recv_cq->lock);
 626         }
 627 }
 628
 629 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 630                               int is_user)
 631 {
 632         struct mlx4_ib_cq *send_cq, *recv_cq;
 633
 634         if (qp->state != IB_QPS_RESET)
 635                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 636                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 637                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 638                                qp->mqp.qpn);
 639
 640         send_cq = to_mcq(qp->ibqp.send_cq);
 641         recv_cq = to_mcq(qp->ibqp.recv_cq);
 642
 643         mlx4_ib_lock_cqs(send_cq, recv_cq);
 644
 645         if (!is_user) {
 646                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 647                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 648                 if (send_cq != recv_cq)
 649                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 650         }
 651
 652         mlx4_qp_remove(dev->dev, &qp->mqp);
 653
 654         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 655
 656         mlx4_qp_free(dev->dev, &qp->mqp);
 657         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 658
 659         if (is_user) {
 660                 if (!qp->ibqp.srq)
 661                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 662                                               &qp->db);
 663                 ib_umem_release(qp->umem);
 664         } else {
 665                 kfree(qp->sq.wrid);
 666                 kfree(qp->rq.wrid);
 667                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 668                 if (!qp->ibqp.srq)
 669                         mlx4_db_free(dev->dev, &qp->db);
 670         }
 671 }
 672
 673 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 674                                 struct ib_qp_init_attr *init_attr,
 675                                 struct ib_udata *udata)
 676 {
 677         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 678         struct mlx4_ib_sqp *sqp;
 679         struct mlx4_ib_qp *qp;
 680         int err;
 681
 682         /*
 683          * We only support LSO and multicast loopback blocking, and
 684          * only for kernel UD QPs.
 685          */
 686         if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
 687                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 688                 return ERR_PTR(-EINVAL);
 689
 690         if (init_attr->create_flags &&
 691             (pd->uobject || init_attr->qp_type != IB_QPT_UD))
 692                 return ERR_PTR(-EINVAL);
 693
 694         switch (init_attr->qp_type) {
 695         case IB_QPT_RC:
 696         case IB_QPT_UC:
 697         case IB_QPT_UD:
 698         {
 699                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
 700                 if (!qp)
 701                         return ERR_PTR(-ENOMEM);
 702
 703                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 704                 if (err) {
 705                         kfree(qp);
 706                         return ERR_PTR(err);
 707                 }
 708
 709                 qp->ibqp.qp_num = qp->mqp.qpn;
 710
 711                 break;
 712         }
 713         case IB_QPT_SMI:
 714         case IB_QPT_GSI:
 715         {
 716                 /* Userspace is not allowed to create special QPs: */
 717                 if (pd->uobject)
 718                         return ERR_PTR(-EINVAL);
 719
 720                 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
 721                 if (!sqp)
 722                         return ERR_PTR(-ENOMEM);
 723
 724                 qp = &sqp->qp;
 725
 726                 err = create_qp_common(dev, pd, init_attr, udata,
 727                                        dev->dev->caps.sqp_start +
 728                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 729                                        init_attr->port_num - 1,
 730                                        qp);
 731                 if (err) {
 732                         kfree(sqp);
 733                         return ERR_PTR(err);
 734                 }
 735
 736                 qp->port        = init_attr->port_num;
 737                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 738
 739                 break;
 740         }
 741         default:
 742                 /* Don't support raw QPs */
 743                 return ERR_PTR(-EINVAL);
 744         }
 745
 746         return &qp->ibqp;
 747 }
 748
 749 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 750 {
 751         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 752         struct mlx4_ib_qp *mqp = to_mqp(qp);
 753
 754         if (is_qp0(dev, mqp))
 755                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 756
 757         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 758
 759         if (is_sqp(dev, mqp))
 760                 kfree(to_msqp(mqp));
 761         else
 762                 kfree(mqp);
 763
 764         return 0;
 765 }
 766
 767 static int to_mlx4_st(enum ib_qp_type type)
 768 {
 769         switch (type) {
 770         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 771         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 772         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 773         case IB_QPT_SMI:
 774         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 775         default:                return -1;
 776         }
 777 }
 778
 779 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 780                                    int attr_mask)
 781 {
 782         u8 dest_rd_atomic;
 783         u32 access_flags;
 784         u32 hw_access_flags = 0;
 785
 786         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 787                 dest_rd_atomic = attr->max_dest_rd_atomic;
 788         else
 789                 dest_rd_atomic = qp->resp_depth;
 790
 791         if (attr_mask & IB_QP_ACCESS_FLAGS)
 792                 access_flags = attr->qp_access_flags;
 793         else
 794                 access_flags = qp->atomic_rd_en;
 795
 796         if (!dest_rd_atomic)
 797                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 798
 799         if (access_flags & IB_ACCESS_REMOTE_READ)
 800                 hw_access_flags |= MLX4_QP_BIT_RRE;
 801         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 802                 hw_access_flags |= MLX4_QP_BIT_RAE;
 803         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 804                 hw_access_flags |= MLX4_QP_BIT_RWE;
 805
 806         return cpu_to_be32(hw_access_flags);
 807 }
 808
 809 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 810                             int attr_mask)
 811 {
 812         if (attr_mask & IB_QP_PKEY_INDEX)
 813                 sqp->pkey_index = attr->pkey_index;
 814         if (attr_mask & IB_QP_QKEY)
 815                 sqp->qkey = attr->qkey;
 816         if (attr_mask & IB_QP_SQ_PSN)
 817                 sqp->send_psn = attr->sq_psn;
 818 }
 819
 820 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 821 {
 822         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 823 }
 824
 825 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 826                          struct mlx4_qp_path *path, u8 port)
 827 {
 828         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 829         path->rlid          = cpu_to_be16(ah->dlid);
 830         if (ah->static_rate) {
 831                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 832                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 833                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 834                         --path->static_rate;
 835         } else
 836                 path->static_rate = 0;
 837         path->counter_index = 0xff;
 838
 839         if (ah->ah_flags & IB_AH_GRH) {
 840                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 841                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 842                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 843                         return -1;
 844                 }
 845
 846                 path->grh_mylmc |= 1 << 7;
 847                 path->mgid_index = ah->grh.sgid_index;
 848                 path->hop_limit  = ah->grh.hop_limit;
 849                 path->tclass_flowlabel =
 850                         cpu_to_be32((ah->grh.traffic_class << 20) |
 851                                     (ah->grh.flow_label));
 852                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 853         }
 854
 855         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 856                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 857
 858         return 0;
 859 }
 860
 861 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 862                                const struct ib_qp_attr *attr, int attr_mask,
 863                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 864 {
 865         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 866         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 867         struct mlx4_qp_context *context;
 868         enum mlx4_qp_optpar optpar = 0;
 869         int sqd_event;
 870         int err = -EINVAL;
 871
 872         context = kzalloc(sizeof *context, GFP_KERNEL);
 873         if (!context)
 874                 return -ENOMEM;
 875
 876         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 877                                      (to_mlx4_st(ibqp->qp_type) << 16));
 878         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 879
 880         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 881                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 882         else {
 883                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 884                 switch (attr->path_mig_state) {
 885                 case IB_MIG_MIGRATED:
 886                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 887                         break;
 888                 case IB_MIG_REARM:
 889                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 890                         break;
 891                 case IB_MIG_ARMED:
 892                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 893                         break;
 894                 }
 895         }
 896
 897         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
 898                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 899         else if (ibqp->qp_type == IB_QPT_UD) {
 900                 if (qp->flags & MLX4_IB_QP_LSO)
 901                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
 902                                               ilog2(dev->dev->caps.max_gso_sz);
 903                 else
 904                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 905         } else if (attr_mask & IB_QP_PATH_MTU) {
 906                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 907                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 908                                attr->path_mtu);
 909                         goto out;
 910                 }
 911                 context->mtu_msgmax = (attr->path_mtu << 5) |
 912                         ilog2(dev->dev->caps.max_msg_sz);
 913         }
 914
 915         if (qp->rq.wqe_cnt)
 916                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 917         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 918
 919         if (qp->sq.wqe_cnt)
 920                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 921         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 922
 923         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 924                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 925
 926         if (qp->ibqp.uobject)
 927                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 928         else
 929                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 930
 931         if (attr_mask & IB_QP_DEST_QPN)
 932                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 933
 934         if (attr_mask & IB_QP_PORT) {
 935                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 936                     !(attr_mask & IB_QP_AV)) {
 937                         mlx4_set_sched(&context->pri_path, attr->port_num);
 938                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 939                 }
 940         }
 941
 942         if (attr_mask & IB_QP_PKEY_INDEX) {
 943                 context->pri_path.pkey_index = attr->pkey_index;
 944                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 945         }
 946
 947         if (attr_mask & IB_QP_AV) {
 948                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 949                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 950                         goto out;
 951
 952                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 953                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 954         }
 955
 956         if (attr_mask & IB_QP_TIMEOUT) {
 957                 context->pri_path.ackto = attr->timeout << 3;
 958                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 959         }
 960
 961         if (attr_mask & IB_QP_ALT_PATH) {
 962                 if (attr->alt_port_num == 0 ||
 963                     attr->alt_port_num > dev->dev->caps.num_ports)
 964                         goto out;
 965
 966                 if (attr->alt_pkey_index >=
 967                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
 968                         goto out;
 969
 970                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 971                                   attr->alt_port_num))
 972                         goto out;
 973
 974                 context->alt_path.pkey_index = attr->alt_pkey_index;
 975                 context->alt_path.ackto = attr->alt_timeout << 3;
 976                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 977         }
 978
 979         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 980         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 981
 982         /* Set "fast registration enabled" for all kernel QPs */
 983         if (!qp->ibqp.uobject)
 984                 context->params1 |= cpu_to_be32(1 << 11);
 985
 986         if (attr_mask & IB_QP_RNR_RETRY) {
 987                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 988                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 989         }
 990
 991         if (attr_mask & IB_QP_RETRY_CNT) {
 992                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 993                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 994         }
 995
 996         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 997                 if (attr->max_rd_atomic)
 998                         context->params1 |=
 999                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1000                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1001         }
1002
1003         if (attr_mask & IB_QP_SQ_PSN)
1004                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1005
1006         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1007
1008         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1009                 if (attr->max_dest_rd_atomic)
1010                         context->params2 |=
1011                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1012                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1013         }
1014
1015         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1016                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1017                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1018         }
1019
1020         if (ibqp->srq)
1021                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1022
1023         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1024                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1025                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1026         }
1027         if (attr_mask & IB_QP_RQ_PSN)
1028                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1029
1030         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1031
1032         if (attr_mask & IB_QP_QKEY) {
1033                 context->qkey = cpu_to_be32(attr->qkey);
1034                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1035         }
1036
1037         if (ibqp->srq)
1038                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1039
1040         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1041                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1042
1043         if (cur_state == IB_QPS_INIT &&
1044             new_state == IB_QPS_RTR  &&
1045             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1046              ibqp->qp_type == IB_QPT_UD)) {
1047                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1048                 if (is_qp0(dev, qp))
1049                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1050                 else
1051                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1052         }
1053
1054         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1055             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1056                 sqd_event = 1;
1057         else
1058                 sqd_event = 0;
1059
1060         /*
1061          * Before passing a kernel QP to the HW, make sure that the
1062          * ownership bits of the send queue are set and the SQ
1063          * headroom is stamped so that the hardware doesn't start
1064          * processing stale work requests.
1065          */
1066         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1067                 struct mlx4_wqe_ctrl_seg *ctrl;
1068                 int i;
1069
1070                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1071                         ctrl = get_send_wqe(qp, i);
1072                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1073                         if (qp->sq_max_wqes_per_wr == 1)
1074                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1075
1076                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1077                 }
1078         }
1079
1080         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1081                              to_mlx4_state(new_state), context, optpar,
1082                              sqd_event, &qp->mqp);
1083         if (err)
1084                 goto out;
1085
1086         qp->state = new_state;
1087
1088         if (attr_mask & IB_QP_ACCESS_FLAGS)
1089                 qp->atomic_rd_en = attr->qp_access_flags;
1090         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1091                 qp->resp_depth = attr->max_dest_rd_atomic;
1092         if (attr_mask & IB_QP_PORT)
1093                 qp->port = attr->port_num;
1094         if (attr_mask & IB_QP_ALT_PATH)
1095                 qp->alt_port = attr->alt_port_num;
1096
1097         if (is_sqp(dev, qp))
1098                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1099
1100         /*
1101          * If we moved QP0 to RTR, bring the IB link up; if we moved
1102          * QP0 to RESET or ERROR, bring the link back down.
1103          */
1104         if (is_qp0(dev, qp)) {
1105                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1106                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1107                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1108                                        qp->port);
1109
1110                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1111                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1112                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1113         }
1114
1115         /*
1116          * If we moved a kernel QP to RESET, clean up all old CQ
1117          * entries and reinitialize the QP.
1118          */
1119         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1120                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1121                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1122                 if (ibqp->send_cq != ibqp->recv_cq)
1123                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1124
1125                 qp->rq.head = 0;
1126                 qp->rq.tail = 0;
1127                 qp->sq.head = 0;
1128                 qp->sq.tail = 0;
1129                 qp->sq_next_wqe = 0;
1130                 if (!ibqp->srq)
1131                         *qp->db.db  = 0;
1132         }
1133
1134 out:
1135         kfree(context);
1136         return err;
1137 }
1138
1139 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1140                       int attr_mask, struct ib_udata *udata)
1141 {
1142         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1143         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1144         enum ib_qp_state cur_state, new_state;
1145         int err = -EINVAL;
1146
1147         mutex_lock(&qp->mutex);
1148
1149         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1150         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1151
1152         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1153                 goto out;
1154
1155         if ((attr_mask & IB_QP_PORT) &&
1156             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1157                 goto out;
1158         }
1159
1160         if (attr_mask & IB_QP_PKEY_INDEX) {
1161                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1162                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1163                         goto out;
1164         }
1165
1166         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1167             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1168                 goto out;
1169         }
1170
1171         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1172             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1173                 goto out;
1174         }
1175
1176         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1177                 err = 0;
1178                 goto out;
1179         }
1180
1181         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1182
1183 out:
1184         mutex_unlock(&qp->mutex);
1185         return err;
1186 }
1187
1188 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1189                             void *wqe, unsigned *mlx_seg_len)
1190 {
1191         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1192         struct mlx4_wqe_mlx_seg *mlx = wqe;
1193         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1194         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1195         u16 pkey;
1196         int send_size;
1197         int header_size;
1198         int spc;
1199         int i;
1200
1201         send_size = 0;
1202         for (i = 0; i < wr->num_sge; ++i)
1203                 send_size += wr->sg_list[i].length;
1204
1205         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1206
1207         sqp->ud_header.lrh.service_level   =
1208                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1209         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1210         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1211         if (mlx4_ib_ah_grh_present(ah)) {
1212                 sqp->ud_header.grh.traffic_class =
1213                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1214                 sqp->ud_header.grh.flow_label    =
1215                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1216                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1217                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1218                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1219                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1220                        ah->av.dgid, 16);
1221         }
1222
1223         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1224         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1225                                   (sqp->ud_header.lrh.destination_lid ==
1226                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1227                                   (sqp->ud_header.lrh.service_level << 8));
1228         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1229
1230         switch (wr->opcode) {
1231         case IB_WR_SEND:
1232                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1233                 sqp->ud_header.immediate_present = 0;
1234                 break;
1235         case IB_WR_SEND_WITH_IMM:
1236                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1237                 sqp->ud_header.immediate_present = 1;
1238                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1239                 break;
1240         default:
1241                 return -EINVAL;
1242         }
1243
1244         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1245         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1246                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1247         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1248         if (!sqp->qp.ibqp.qp_num)
1249                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1250         else
1251                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1252         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1253         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1254         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1255         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1256                                                sqp->qkey : wr->wr.ud.remote_qkey);
1257         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1258
1259         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1260
1261         if (0) {
1262                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1263                 for (i = 0; i < header_size / 4; ++i) {
1264                         if (i % 8 == 0)
1265                                 printk("  [%02x] ", i * 4);
1266                         printk(" %08x",
1267                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1268                         if ((i + 1) % 8 == 0)
1269                                 printk("\n");
1270                 }
1271                 printk("\n");
1272         }
1273
1274         /*
1275          * Inline data segments may not cross a 64 byte boundary.  If
1276          * our UD header is bigger than the space available up to the
1277          * next 64 byte boundary in the WQE, use two inline data
1278          * segments to hold the UD header.
1279          */
1280         spc = MLX4_INLINE_ALIGN -
1281                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1282         if (header_size <= spc) {
1283                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1284                 memcpy(inl + 1, sqp->header_buf, header_size);
1285                 i = 1;
1286         } else {
1287                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1288                 memcpy(inl + 1, sqp->header_buf, spc);
1289
1290                 inl = (void *) (inl + 1) + spc;
1291                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1292                 /*
1293                  * Need a barrier here to make sure all the data is
1294                  * visible before the byte_count field is set.
1295                  * Otherwise the HCA prefetcher could grab the 64-byte
1296                  * chunk with this inline segment and get a valid (!=
1297                  * 0xffffffff) byte count but stale data, and end up
1298                  * generating a packet with bad headers.
1299                  *
1300                  * The first inline segment's byte_count field doesn't
1301                  * need a barrier, because it comes after a
1302                  * control/MLX segment and therefore is at an offset
1303                  * of 16 mod 64.
1304                  */
1305                 wmb();
1306                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1307                 i = 2;
1308         }
1309
1310         *mlx_seg_len =
1311                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1312         return 0;
1313 }
1314
1315 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1316 {
1317         unsigned cur;
1318         struct mlx4_ib_cq *cq;
1319
1320         cur = wq->head - wq->tail;
1321         if (likely(cur + nreq < wq->max_post))
1322                 return 0;
1323
1324         cq = to_mcq(ib_cq);
1325         spin_lock(&cq->lock);
1326         cur = wq->head - wq->tail;
1327         spin_unlock(&cq->lock);
1328
1329         return cur + nreq >= wq->max_post;
1330 }
1331
1332 static __be32 convert_access(int acc)
1333 {
1334         return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC)       : 0) |
1335                (acc & IB_ACCESS_REMOTE_WRITE  ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1336                (acc & IB_ACCESS_REMOTE_READ   ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ)  : 0) |
1337                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
1338                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1339 }
1340
1341 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1342 {
1343         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1344
1345         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
1346         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
1347         fseg->buf_list          = cpu_to_be64(mfrpl->map);
1348         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
1349         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
1350         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
1351         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
1352         fseg->reserved[0]       = 0;
1353         fseg->reserved[1]       = 0;
1354 }
1355
1356 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1357 {
1358         iseg->flags     = 0;
1359         iseg->mem_key   = cpu_to_be32(rkey);
1360         iseg->guest_id  = 0;
1361         iseg->pa        = 0;
1362 }
1363
1364 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1365                                           u64 remote_addr, u32 rkey)
1366 {
1367         rseg->raddr    = cpu_to_be64(remote_addr);
1368         rseg->rkey     = cpu_to_be32(rkey);
1369         rseg->reserved = 0;
1370 }
1371
1372 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1373 {
1374         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1375                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1376                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1377         } else {
1378                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1379                 aseg->compare  = 0;
1380         }
1381
1382 }
1383
1384 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1385                              struct ib_send_wr *wr)
1386 {
1387         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1388         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1389         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1390 }
1391
1392 static void set_mlx_icrc_seg(void *dseg)
1393 {
1394         u32 *t = dseg;
1395         struct mlx4_wqe_inline_seg *iseg = dseg;
1396
1397         t[1] = 0;
1398
1399         /*
1400          * Need a barrier here before writing the byte_count field to
1401          * make sure that all the data is visible before the
1402          * byte_count field is set.  Otherwise, if the segment begins
1403          * a new cacheline, the HCA prefetcher could grab the 64-byte
1404          * chunk and get a valid (!= * 0xffffffff) byte count but
1405          * stale data, and end up sending the wrong data.
1406          */
1407         wmb();
1408
1409         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1410 }
1411
1412 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1413 {
1414         dseg->lkey       = cpu_to_be32(sg->lkey);
1415         dseg->addr       = cpu_to_be64(sg->addr);
1416
1417         /*
1418          * Need a barrier here before writing the byte_count field to
1419          * make sure that all the data is visible before the
1420          * byte_count field is set.  Otherwise, if the segment begins
1421          * a new cacheline, the HCA prefetcher could grab the 64-byte
1422          * chunk and get a valid (!= * 0xffffffff) byte count but
1423          * stale data, and end up sending the wrong data.
1424          */
1425         wmb();
1426
1427         dseg->byte_count = cpu_to_be32(sg->length);
1428 }
1429
1430 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1431 {
1432         dseg->byte_count = cpu_to_be32(sg->length);
1433         dseg->lkey       = cpu_to_be32(sg->lkey);
1434         dseg->addr       = cpu_to_be64(sg->addr);
1435 }
1436
1437 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
1438                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len)
1439 {
1440         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1441
1442         /*
1443          * This is a temporary limitation and will be removed in
1444          * a forthcoming FW release:
1445          */
1446         if (unlikely(halign > 64))
1447                 return -EINVAL;
1448
1449         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1450                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1451                 return -EINVAL;
1452
1453         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1454
1455         /* make sure LSO header is written before overwriting stamping */
1456         wmb();
1457
1458         wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1459                                         wr->wr.ud.hlen);
1460
1461         *lso_seg_len = halign;
1462         return 0;
1463 }
1464
1465 static __be32 send_ieth(struct ib_send_wr *wr)
1466 {
1467         switch (wr->opcode) {
1468         case IB_WR_SEND_WITH_IMM:
1469         case IB_WR_RDMA_WRITE_WITH_IMM:
1470                 return wr->ex.imm_data;
1471
1472         case IB_WR_SEND_WITH_INV:
1473                 return cpu_to_be32(wr->ex.invalidate_rkey);
1474
1475         default:
1476                 return 0;
1477         }
1478 }
1479
1480 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1481                       struct ib_send_wr **bad_wr)
1482 {
1483         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1484         void *wqe;
1485         struct mlx4_wqe_ctrl_seg *ctrl;
1486         struct mlx4_wqe_data_seg *dseg;
1487         unsigned long flags;
1488         int nreq;
1489         int err = 0;
1490         unsigned ind;
1491         int uninitialized_var(stamp);
1492         int uninitialized_var(size);
1493         unsigned uninitialized_var(seglen);
1494         int i;
1495
1496         spin_lock_irqsave(&qp->sq.lock, flags);
1497
1498         ind = qp->sq_next_wqe;
1499
1500         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1501                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1502                         err = -ENOMEM;
1503                         *bad_wr = wr;
1504                         goto out;
1505                 }
1506
1507                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1508                         err = -EINVAL;
1509                         *bad_wr = wr;
1510                         goto out;
1511                 }
1512
1513                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1514                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1515
1516                 ctrl->srcrb_flags =
1517                         (wr->send_flags & IB_SEND_SIGNALED ?
1518                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1519                         (wr->send_flags & IB_SEND_SOLICITED ?
1520                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1521                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1522                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1523                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1524                         qp->sq_signal_bits;
1525
1526                 ctrl->imm = send_ieth(wr);
1527
1528                 wqe += sizeof *ctrl;
1529                 size = sizeof *ctrl / 16;
1530
1531                 switch (ibqp->qp_type) {
1532                 case IB_QPT_RC:
1533                 case IB_QPT_UC:
1534                         switch (wr->opcode) {
1535                         case IB_WR_ATOMIC_CMP_AND_SWP:
1536                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1537                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1538                                               wr->wr.atomic.rkey);
1539                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1540
1541                                 set_atomic_seg(wqe, wr);
1542                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1543
1544                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1545                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1546
1547                                 break;
1548
1549                         case IB_WR_RDMA_READ:
1550                         case IB_WR_RDMA_WRITE:
1551                         case IB_WR_RDMA_WRITE_WITH_IMM:
1552                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1553                                               wr->wr.rdma.rkey);
1554                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1555                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1556                                 break;
1557
1558                         case IB_WR_LOCAL_INV:
1559                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1560                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
1561                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1562                                 break;
1563
1564                         case IB_WR_FAST_REG_MR:
1565                                 set_fmr_seg(wqe, wr);
1566                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
1567                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1568                                 break;
1569
1570                         default:
1571                                 /* No extra segments required for sends */
1572                                 break;
1573                         }
1574                         break;
1575
1576                 case IB_QPT_UD:
1577                         set_datagram_seg(wqe, wr);
1578                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1579                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1580
1581                         if (wr->opcode == IB_WR_LSO) {
1582                                 err = build_lso_seg(wqe, wr, qp, &seglen);
1583                                 if (unlikely(err)) {
1584                                         *bad_wr = wr;
1585                                         goto out;
1586                                 }
1587                                 wqe  += seglen;
1588                                 size += seglen / 16;
1589                         }
1590                         break;
1591
1592                 case IB_QPT_SMI:
1593                 case IB_QPT_GSI:
1594                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1595                         if (unlikely(err)) {
1596                                 *bad_wr = wr;
1597                                 goto out;
1598                         }
1599                         wqe  += seglen;
1600                         size += seglen / 16;
1601                         break;
1602
1603                 default:
1604                         break;
1605                 }
1606
1607                 /*
1608                  * Write data segments in reverse order, so as to
1609                  * overwrite cacheline stamp last within each
1610                  * cacheline.  This avoids issues with WQE
1611                  * prefetching.
1612                  */
1613
1614                 dseg = wqe;
1615                 dseg += wr->num_sge - 1;
1616                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1617
1618                 /* Add one more inline data segment for ICRC for MLX sends */
1619                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1620                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1621                         set_mlx_icrc_seg(dseg + 1);
1622                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1623                 }
1624
1625                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1626                         set_data_seg(dseg, wr->sg_list + i);
1627
1628                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1629                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1630
1631                 /*
1632                  * Make sure descriptor is fully written before
1633                  * setting ownership bit (because HW can start
1634                  * executing as soon as we do).
1635                  */
1636                 wmb();
1637
1638                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1639                         err = -EINVAL;
1640                         goto out;
1641                 }
1642
1643                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1644                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1645
1646                 stamp = ind + qp->sq_spare_wqes;
1647                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1648
1649                 /*
1650                  * We can improve latency by not stamping the last
1651                  * send queue WQE until after ringing the doorbell, so
1652                  * only stamp here if there are still more WQEs to post.
1653                  *
1654                  * Same optimization applies to padding with NOP wqe
1655                  * in case of WQE shrinking (used to prevent wrap-around
1656                  * in the middle of WR).
1657                  */
1658                 if (wr->next) {
1659                         stamp_send_wqe(qp, stamp, size * 16);
1660                         ind = pad_wraparound(qp, ind);
1661                 }
1662
1663         }
1664
1665 out:
1666         if (likely(nreq)) {
1667                 qp->sq.head += nreq;
1668
1669                 /*
1670                  * Make sure that descriptors are written before
1671                  * doorbell record.
1672                  */
1673                 wmb();
1674
1675                 writel(qp->doorbell_qpn,
1676                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1677
1678                 /*
1679                  * Make sure doorbells don't leak out of SQ spinlock
1680                  * and reach the HCA out of order.
1681                  */
1682                 mmiowb();
1683
1684                 stamp_send_wqe(qp, stamp, size * 16);
1685
1686                 ind = pad_wraparound(qp, ind);
1687                 qp->sq_next_wqe = ind;
1688         }
1689
1690         spin_unlock_irqrestore(&qp->sq.lock, flags);
1691
1692         return err;
1693 }
1694
1695 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1696                       struct ib_recv_wr **bad_wr)
1697 {
1698         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1699         struct mlx4_wqe_data_seg *scat;
1700         unsigned long flags;
1701         int err = 0;
1702         int nreq;
1703         int ind;
1704         int i;
1705
1706         spin_lock_irqsave(&qp->rq.lock, flags);
1707
1708         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1709
1710         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1711                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1712                         err = -ENOMEM;
1713                         *bad_wr = wr;
1714                         goto out;
1715                 }
1716
1717                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1718                         err = -EINVAL;
1719                         *bad_wr = wr;
1720                         goto out;
1721                 }
1722
1723                 scat = get_recv_wqe(qp, ind);
1724
1725                 for (i = 0; i < wr->num_sge; ++i)
1726                         __set_data_seg(scat + i, wr->sg_list + i);
1727
1728                 if (i < qp->rq.max_gs) {
1729                         scat[i].byte_count = 0;
1730                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1731                         scat[i].addr       = 0;
1732                 }
1733
1734                 qp->rq.wrid[ind] = wr->wr_id;
1735
1736                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1737         }
1738
1739 out:
1740         if (likely(nreq)) {
1741                 qp->rq.head += nreq;
1742
1743                 /*
1744                  * Make sure that descriptors are written before
1745                  * doorbell record.
1746                  */
1747                 wmb();
1748
1749                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1750         }
1751
1752         spin_unlock_irqrestore(&qp->rq.lock, flags);
1753
1754         return err;
1755 }
1756
1757 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1758 {
1759         switch (mlx4_state) {
1760         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1761         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1762         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1763         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1764         case MLX4_QP_STATE_SQ_DRAINING:
1765         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1766         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1767         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1768         default:                     return -1;
1769         }
1770 }
1771
1772 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1773 {
1774         switch (mlx4_mig_state) {
1775         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1776         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1777         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1778         default: return -1;
1779         }
1780 }
1781
1782 static int to_ib_qp_access_flags(int mlx4_flags)
1783 {
1784         int ib_flags = 0;
1785
1786         if (mlx4_flags & MLX4_QP_BIT_RRE)
1787                 ib_flags |= IB_ACCESS_REMOTE_READ;
1788         if (mlx4_flags & MLX4_QP_BIT_RWE)
1789                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1790         if (mlx4_flags & MLX4_QP_BIT_RAE)
1791                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1792
1793         return ib_flags;
1794 }
1795
1796 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1797                                 struct mlx4_qp_path *path)
1798 {
1799         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1800         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1801
1802         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1803                 return;
1804
1805         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1806         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1807         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1808         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1809         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1810         if (ib_ah_attr->ah_flags) {
1811                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1812                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1813                 ib_ah_attr->grh.traffic_class =
1814                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1815                 ib_ah_attr->grh.flow_label =
1816                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1817                 memcpy(ib_ah_attr->grh.dgid.raw,
1818                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1819         }
1820 }
1821
1822 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1823                      struct ib_qp_init_attr *qp_init_attr)
1824 {
1825         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1826         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1827         struct mlx4_qp_context context;
1828         int mlx4_state;
1829         int err = 0;
1830
1831         mutex_lock(&qp->mutex);
1832
1833         if (qp->state == IB_QPS_RESET) {
1834                 qp_attr->qp_state = IB_QPS_RESET;
1835                 goto done;
1836         }
1837
1838         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1839         if (err) {
1840                 err = -EINVAL;
1841                 goto out;
1842         }
1843
1844         mlx4_state = be32_to_cpu(context.flags) >> 28;
1845
1846         qp->state                    = to_ib_qp_state(mlx4_state);
1847         qp_attr->qp_state            = qp->state;
1848         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1849         qp_attr->path_mig_state      =
1850                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1851         qp_attr->qkey                = be32_to_cpu(context.qkey);
1852         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1853         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1854         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1855         qp_attr->qp_access_flags     =
1856                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1857
1858         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1859                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1860                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1861                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1862                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1863         }
1864
1865         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1866         if (qp_attr->qp_state == IB_QPS_INIT)
1867                 qp_attr->port_num = qp->port;
1868         else
1869                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1870
1871         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1872         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1873
1874         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1875
1876         qp_attr->max_dest_rd_atomic =
1877                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1878         qp_attr->min_rnr_timer      =
1879                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1880         qp_attr->timeout            = context.pri_path.ackto >> 3;
1881         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
1882         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
1883         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1884
1885 done:
1886         qp_attr->cur_qp_state        = qp_attr->qp_state;
1887         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1888         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1889
1890         if (!ibqp->uobject) {
1891                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1892                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1893         } else {
1894                 qp_attr->cap.max_send_wr  = 0;
1895                 qp_attr->cap.max_send_sge = 0;
1896         }
1897
1898         /*
1899          * We don't support inline sends for kernel QPs (yet), and we
1900          * don't know what userspace's value should be.
1901          */
1902         qp_attr->cap.max_inline_data = 0;
1903
1904         qp_init_attr->cap            = qp_attr->cap;
1905
1906         qp_init_attr->create_flags = 0;
1907         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1908                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
1909
1910         if (qp->flags & MLX4_IB_QP_LSO)
1911                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
1912
1913 out:
1914         mutex_unlock(&qp->mutex);
1915         return err;
1916 }
1917