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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.34-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  92          board_82599 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  94          board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  96          board_82599 },
  97
  98         /* required last entry */
  99         {0, }
 100 };
 101 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 102
 103 #ifdef CONFIG_IXGBE_DCA
 104 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 105                             void *p);
 106 static struct notifier_block dca_notifier = {
 107         .notifier_call = ixgbe_notify_dca,
 108         .next          = NULL,
 109         .priority      = 0
 110 };
 111 #endif
 112
 113 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 114 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 115 MODULE_LICENSE("GPL");
 116 MODULE_VERSION(DRV_VERSION);
 117
 118 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 119
 120 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 121 {
 122         u32 ctrl_ext;
 123
 124         /* Let firmware take over control of h/w */
 125         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 126         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 127                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 128 }
 129
 130 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 131 {
 132         u32 ctrl_ext;
 133
 134         /* Let firmware know the driver has taken over */
 135         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 136         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 137                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 138 }
 139
 140 /*
 141  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 142  * @adapter: pointer to adapter struct
 143  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 144  * @queue: queue to map the corresponding interrupt to
 145  * @msix_vector: the vector to map to the corresponding queue
 146  *
 147  */
 148 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 149                            u8 queue, u8 msix_vector)
 150 {
 151         u32 ivar, index;
 152         struct ixgbe_hw *hw = &adapter->hw;
 153         switch (hw->mac.type) {
 154         case ixgbe_mac_82598EB:
 155                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 156                 if (direction == -1)
 157                         direction = 0;
 158                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 159                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 160                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 161                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 162                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 163                 break;
 164         case ixgbe_mac_82599EB:
 165                 if (direction == -1) {
 166                         /* other causes */
 167                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                         index = ((queue & 1) * 8);
 169                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 170                         ivar &= ~(0xFF << index);
 171                         ivar |= (msix_vector << index);
 172                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 173                         break;
 174                 } else {
 175                         /* tx or rx causes */
 176                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 177                         index = ((16 * (queue & 1)) + (8 * direction));
 178                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 179                         ivar &= ~(0xFF << index);
 180                         ivar |= (msix_vector << index);
 181                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 182                         break;
 183                 }
 184         default:
 185                 break;
 186         }
 187 }
 188
 189 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 190                                           u64 qmask)
 191 {
 192         u32 mask;
 193
 194         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 195                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 196                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 197         } else {
 198                 mask = (qmask & 0xFFFFFFFF);
 199                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 200                 mask = (qmask >> 32);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 202         }
 203 }
 204
 205 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 206                                              struct ixgbe_tx_buffer
 207                                              *tx_buffer_info)
 208 {
 209         tx_buffer_info->dma = 0;
 210         if (tx_buffer_info->skb) {
 211                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 212                               DMA_TO_DEVICE);
 213                 dev_kfree_skb_any(tx_buffer_info->skb);
 214                 tx_buffer_info->skb = NULL;
 215         }
 216         tx_buffer_info->time_stamp = 0;
 217         /* tx_buffer_info must be completely set up in the transmit path */
 218 }
 219
 220 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 221                                        struct ixgbe_ring *tx_ring,
 222                                        unsigned int eop)
 223 {
 224         struct ixgbe_hw *hw = &adapter->hw;
 225
 226         /* Detect a transmit hang in hardware, this serializes the
 227          * check with the clearing of time_stamp and movement of eop */
 228         adapter->detect_tx_hung = false;
 229         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 230             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 231             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 232                 /* detected Tx unit hang */
 233                 union ixgbe_adv_tx_desc *tx_desc;
 234                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 235                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 236                         "  Tx Queue             <%d>\n"
 237                         "  TDH, TDT             <%x>, <%x>\n"
 238                         "  next_to_use          <%x>\n"
 239                         "  next_to_clean        <%x>\n"
 240                         "tx_buffer_info[next_to_clean]\n"
 241                         "  time_stamp           <%lx>\n"
 242                         "  jiffies              <%lx>\n",
 243                         tx_ring->queue_index,
 244                         IXGBE_READ_REG(hw, tx_ring->head),
 245                         IXGBE_READ_REG(hw, tx_ring->tail),
 246                         tx_ring->next_to_use, eop,
 247                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 248                 return true;
 249         }
 250
 251         return false;
 252 }
 253
 254 #define IXGBE_MAX_TXD_PWR       14
 255 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 256
 257 /* Tx Descriptors needed, worst case */
 258 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 259                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 260 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 261         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 262
 263 static void ixgbe_tx_timeout(struct net_device *netdev);
 264
 265 /**
 266  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 267  * @q_vector: structure containing interrupt and ring information
 268  * @tx_ring: tx ring to clean
 269  **/
 270 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 271                                struct ixgbe_ring *tx_ring)
 272 {
 273         struct ixgbe_adapter *adapter = q_vector->adapter;
 274         struct net_device *netdev = adapter->netdev;
 275         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 276         struct ixgbe_tx_buffer *tx_buffer_info;
 277         unsigned int i, eop, count = 0;
 278         unsigned int total_bytes = 0, total_packets = 0;
 279
 280         i = tx_ring->next_to_clean;
 281         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 282         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 283
 284         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 285                (count < tx_ring->work_limit)) {
 286                 bool cleaned = false;
 287                 for ( ; !cleaned; count++) {
 288                         struct sk_buff *skb;
 289                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 290                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 291                         cleaned = (i == eop);
 292                         skb = tx_buffer_info->skb;
 293
 294                         if (cleaned && skb) {
 295                                 unsigned int segs, bytecount;
 296                                 unsigned int hlen = skb_headlen(skb);
 297
 298                                 /* gso_segs is currently only valid for tcp */
 299                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 300 #ifdef IXGBE_FCOE
 301                                 /* adjust for FCoE Sequence Offload */
 302                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 303                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 304                                     skb_is_gso(skb)) {
 305                                         hlen = skb_transport_offset(skb) +
 306                                                 sizeof(struct fc_frame_header) +
 307                                                 sizeof(struct fcoe_crc_eof);
 308                                         segs = DIV_ROUND_UP(skb->len - hlen,
 309                                                 skb_shinfo(skb)->gso_size);
 310                                 }
 311 #endif /* IXGBE_FCOE */
 312                                 /* multiply data chunks by size of headers */
 313                                 bytecount = ((segs - 1) * hlen) + skb->len;
 314                                 total_packets += segs;
 315                                 total_bytes += bytecount;
 316                         }
 317
 318                         ixgbe_unmap_and_free_tx_resource(adapter,
 319                                                          tx_buffer_info);
 320
 321                         tx_desc->wb.status = 0;
 322
 323                         i++;
 324                         if (i == tx_ring->count)
 325                                 i = 0;
 326                 }
 327
 328                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 329                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 330         }
 331
 332         tx_ring->next_to_clean = i;
 333
 334 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 335         if (unlikely(count && netif_carrier_ok(netdev) &&
 336                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 337                 /* Make sure that anybody stopping the queue after this
 338                  * sees the new next_to_clean.
 339                  */
 340                 smp_mb();
 341                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 342                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 343                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 344                         ++adapter->restart_queue;
 345                 }
 346         }
 347
 348         if (adapter->detect_tx_hung) {
 349                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 350                         /* schedule immediate reset if we believe we hung */
 351                         DPRINTK(PROBE, INFO,
 352                                 "tx hang %d detected, resetting adapter\n",
 353                                 adapter->tx_timeout_count + 1);
 354                         ixgbe_tx_timeout(adapter->netdev);
 355                 }
 356         }
 357
 358         /* re-arm the interrupt */
 359         if (count >= tx_ring->work_limit)
 360                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 361
 362         tx_ring->total_bytes += total_bytes;
 363         tx_ring->total_packets += total_packets;
 364         tx_ring->stats.packets += total_packets;
 365         tx_ring->stats.bytes += total_bytes;
 366         adapter->net_stats.tx_bytes += total_bytes;
 367         adapter->net_stats.tx_packets += total_packets;
 368         return (count < tx_ring->work_limit);
 369 }
 370
 371 #ifdef CONFIG_IXGBE_DCA
 372 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 373                                 struct ixgbe_ring *rx_ring)
 374 {
 375         u32 rxctrl;
 376         int cpu = get_cpu();
 377         int q = rx_ring - adapter->rx_ring;
 378
 379         if (rx_ring->cpu != cpu) {
 380                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 381                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 382                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 383                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 384                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 385                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 386                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 387                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 388                 }
 389                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 390                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 391                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 392                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 393                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 394                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 395                 rx_ring->cpu = cpu;
 396         }
 397         put_cpu();
 398 }
 399
 400 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 401                                 struct ixgbe_ring *tx_ring)
 402 {
 403         u32 txctrl;
 404         int cpu = get_cpu();
 405         int q = tx_ring - adapter->tx_ring;
 406
 407         if (tx_ring->cpu != cpu) {
 408                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 409                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 410                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 411                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 412                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 413                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 414                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 415                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 416                 }
 417                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 418                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 419                 tx_ring->cpu = cpu;
 420         }
 421         put_cpu();
 422 }
 423
 424 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 425 {
 426         int i;
 427
 428         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 429                 return;
 430
 431         /* always use CB2 mode, difference is masked in the CB driver */
 432         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 433
 434         for (i = 0; i < adapter->num_tx_queues; i++) {
 435                 adapter->tx_ring[i].cpu = -1;
 436                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 437         }
 438         for (i = 0; i < adapter->num_rx_queues; i++) {
 439                 adapter->rx_ring[i].cpu = -1;
 440                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 441         }
 442 }
 443
 444 static int __ixgbe_notify_dca(struct device *dev, void *data)
 445 {
 446         struct net_device *netdev = dev_get_drvdata(dev);
 447         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 448         unsigned long event = *(unsigned long *)data;
 449
 450         switch (event) {
 451         case DCA_PROVIDER_ADD:
 452                 /* if we're already enabled, don't do it again */
 453                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 454                         break;
 455                 if (dca_add_requester(dev) == 0) {
 456                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 457                         ixgbe_setup_dca(adapter);
 458                         break;
 459                 }
 460                 /* Fall Through since DCA is disabled. */
 461         case DCA_PROVIDER_REMOVE:
 462                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 463                         dca_remove_requester(dev);
 464                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 465                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 466                 }
 467                 break;
 468         }
 469
 470         return 0;
 471 }
 472
 473 #endif /* CONFIG_IXGBE_DCA */
 474 /**
 475  * ixgbe_receive_skb - Send a completed packet up the stack
 476  * @adapter: board private structure
 477  * @skb: packet to send up
 478  * @status: hardware indication of status of receive
 479  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 480  * @rx_desc: rx descriptor
 481  **/
 482 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 483                               struct sk_buff *skb, u8 status,
 484                               struct ixgbe_ring *ring,
 485                               union ixgbe_adv_rx_desc *rx_desc)
 486 {
 487         struct ixgbe_adapter *adapter = q_vector->adapter;
 488         struct napi_struct *napi = &q_vector->napi;
 489         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 490         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 491
 492         skb_record_rx_queue(skb, ring->queue_index);
 493         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 494                 if (adapter->vlgrp && is_vlan && (tag != 0))
 495                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 496                 else
 497                         napi_gro_receive(napi, skb);
 498         } else {
 499                 if (adapter->vlgrp && is_vlan && (tag != 0))
 500                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 501                 else
 502                         netif_rx(skb);
 503         }
 504 }
 505
 506 /**
 507  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 508  * @adapter: address of board private structure
 509  * @status_err: hardware indication of status of receive
 510  * @skb: skb currently being received and modified
 511  **/
 512 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 513                                      u32 status_err, struct sk_buff *skb)
 514 {
 515         skb->ip_summed = CHECKSUM_NONE;
 516
 517         /* Rx csum disabled */
 518         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 519                 return;
 520
 521         /* if IP and error */
 522         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 523             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 524                 adapter->hw_csum_rx_error++;
 525                 return;
 526         }
 527
 528         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 529                 return;
 530
 531         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 532                 adapter->hw_csum_rx_error++;
 533                 return;
 534         }
 535
 536         /* It must be a TCP or UDP packet with a valid checksum */
 537         skb->ip_summed = CHECKSUM_UNNECESSARY;
 538         adapter->hw_csum_rx_good++;
 539 }
 540
 541 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 542                                          struct ixgbe_ring *rx_ring, u32 val)
 543 {
 544         /*
 545          * Force memory writes to complete before letting h/w
 546          * know there are new descriptors to fetch.  (Only
 547          * applicable for weak-ordered memory model archs,
 548          * such as IA-64).
 549          */
 550         wmb();
 551         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 552 }
 553
 554 /**
 555  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 556  * @adapter: address of board private structure
 557  **/
 558 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 559                                    struct ixgbe_ring *rx_ring,
 560                                    int cleaned_count)
 561 {
 562         struct pci_dev *pdev = adapter->pdev;
 563         union ixgbe_adv_rx_desc *rx_desc;
 564         struct ixgbe_rx_buffer *bi;
 565         unsigned int i;
 566         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 567
 568         i = rx_ring->next_to_use;
 569         bi = &rx_ring->rx_buffer_info[i];
 570
 571         while (cleaned_count--) {
 572                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 573
 574                 if (!bi->page_dma &&
 575                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 576                         if (!bi->page) {
 577                                 bi->page = alloc_page(GFP_ATOMIC);
 578                                 if (!bi->page) {
 579                                         adapter->alloc_rx_page_failed++;
 580                                         goto no_buffers;
 581                                 }
 582                                 bi->page_offset = 0;
 583                         } else {
 584                                 /* use a half page if we're re-using */
 585                                 bi->page_offset ^= (PAGE_SIZE / 2);
 586                         }
 587
 588                         bi->page_dma = pci_map_page(pdev, bi->page,
 589                                                     bi->page_offset,
 590                                                     (PAGE_SIZE / 2),
 591                                                     PCI_DMA_FROMDEVICE);
 592                 }
 593
 594                 if (!bi->skb) {
 595                         struct sk_buff *skb;
 596                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 597
 598                         if (!skb) {
 599                                 adapter->alloc_rx_buff_failed++;
 600                                 goto no_buffers;
 601                         }
 602
 603                         /*
 604                          * Make buffer alignment 2 beyond a 16 byte boundary
 605                          * this will result in a 16 byte aligned IP header after
 606                          * the 14 byte MAC header is removed
 607                          */
 608                         skb_reserve(skb, NET_IP_ALIGN);
 609
 610                         bi->skb = skb;
 611                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 612                                                  PCI_DMA_FROMDEVICE);
 613                 }
 614                 /* Refresh the desc even if buffer_addrs didn't change because
 615                  * each write-back erases this info. */
 616                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 617                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 618                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 619                 } else {
 620                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 621                 }
 622
 623                 i++;
 624                 if (i == rx_ring->count)
 625                         i = 0;
 626                 bi = &rx_ring->rx_buffer_info[i];
 627         }
 628
 629 no_buffers:
 630         if (rx_ring->next_to_use != i) {
 631                 rx_ring->next_to_use = i;
 632                 if (i-- == 0)
 633                         i = (rx_ring->count - 1);
 634
 635                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 636         }
 637 }
 638
 639 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 640 {
 641         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 642 }
 643
 644 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 645 {
 646         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 647 }
 648
 649 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 650 {
 651         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 652                 IXGBE_RXDADV_RSCCNT_MASK) >>
 653                 IXGBE_RXDADV_RSCCNT_SHIFT;
 654 }
 655
 656 /**
 657  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 658  * @skb: pointer to the last skb in the rsc queue
 659  *
 660  * This function changes a queue full of hw rsc buffers into a completed
 661  * packet.  It uses the ->prev pointers to find the first packet and then
 662  * turns it into the frag list owner.
 663  **/
 664 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 665 {
 666         unsigned int frag_list_size = 0;
 667
 668         while (skb->prev) {
 669                 struct sk_buff *prev = skb->prev;
 670                 frag_list_size += skb->len;
 671                 skb->prev = NULL;
 672                 skb = prev;
 673         }
 674
 675         skb_shinfo(skb)->frag_list = skb->next;
 676         skb->next = NULL;
 677         skb->len += frag_list_size;
 678         skb->data_len += frag_list_size;
 679         skb->truesize += frag_list_size;
 680         return skb;
 681 }
 682
 683 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 684                                struct ixgbe_ring *rx_ring,
 685                                int *work_done, int work_to_do)
 686 {
 687         struct ixgbe_adapter *adapter = q_vector->adapter;
 688         struct pci_dev *pdev = adapter->pdev;
 689         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 690         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 691         struct sk_buff *skb;
 692         unsigned int i, rsc_count = 0;
 693         u32 len, staterr;
 694         u16 hdr_info;
 695         bool cleaned = false;
 696         int cleaned_count = 0;
 697         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 698 #ifdef IXGBE_FCOE
 699         int ddp_bytes = 0;
 700 #endif /* IXGBE_FCOE */
 701
 702         i = rx_ring->next_to_clean;
 703         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 704         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 705         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 706
 707         while (staterr & IXGBE_RXD_STAT_DD) {
 708                 u32 upper_len = 0;
 709                 if (*work_done >= work_to_do)
 710                         break;
 711                 (*work_done)++;
 712
 713                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 714                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 715                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 716                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 717                         if (hdr_info & IXGBE_RXDADV_SPH)
 718                                 adapter->rx_hdr_split++;
 719                         if (len > IXGBE_RX_HDR_SIZE)
 720                                 len = IXGBE_RX_HDR_SIZE;
 721                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 722                 } else {
 723                         len = le16_to_cpu(rx_desc->wb.upper.length);
 724                 }
 725
 726                 cleaned = true;
 727                 skb = rx_buffer_info->skb;
 728                 prefetch(skb->data - NET_IP_ALIGN);
 729                 rx_buffer_info->skb = NULL;
 730
 731                 if (rx_buffer_info->dma) {
 732                         pci_unmap_single(pdev, rx_buffer_info->dma,
 733                                          rx_ring->rx_buf_len,
 734                                          PCI_DMA_FROMDEVICE);
 735                         skb_put(skb, len);
 736                 }
 737
 738                 if (upper_len) {
 739                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 740                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 741                         rx_buffer_info->page_dma = 0;
 742                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 743                                            rx_buffer_info->page,
 744                                            rx_buffer_info->page_offset,
 745                                            upper_len);
 746
 747                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 748                             (page_count(rx_buffer_info->page) != 1))
 749                                 rx_buffer_info->page = NULL;
 750                         else
 751                                 get_page(rx_buffer_info->page);
 752
 753                         skb->len += upper_len;
 754                         skb->data_len += upper_len;
 755                         skb->truesize += upper_len;
 756                 }
 757
 758                 i++;
 759                 if (i == rx_ring->count)
 760                         i = 0;
 761
 762                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 763                 prefetch(next_rxd);
 764                 cleaned_count++;
 765
 766                 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
 767                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 768
 769                 if (rsc_count) {
 770                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 771                                      IXGBE_RXDADV_NEXTP_SHIFT;
 772                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 773                         rx_ring->rsc_count += (rsc_count - 1);
 774                 } else {
 775                         next_buffer = &rx_ring->rx_buffer_info[i];
 776                 }
 777
 778                 if (staterr & IXGBE_RXD_STAT_EOP) {
 779                         if (skb->prev)
 780                                 skb = ixgbe_transform_rsc_queue(skb);
 781                         rx_ring->stats.packets++;
 782                         rx_ring->stats.bytes += skb->len;
 783                 } else {
 784                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 785                                 rx_buffer_info->skb = next_buffer->skb;
 786                                 rx_buffer_info->dma = next_buffer->dma;
 787                                 next_buffer->skb = skb;
 788                                 next_buffer->dma = 0;
 789                         } else {
 790                                 skb->next = next_buffer->skb;
 791                                 skb->next->prev = skb;
 792                         }
 793                         adapter->non_eop_descs++;
 794                         goto next_desc;
 795                 }
 796
 797                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 798                         dev_kfree_skb_irq(skb);
 799                         goto next_desc;
 800                 }
 801
 802                 ixgbe_rx_checksum(adapter, staterr, skb);
 803
 804                 /* probably a little skewed due to removing CRC */
 805                 total_rx_bytes += skb->len;
 806                 total_rx_packets++;
 807
 808                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 809 #ifdef IXGBE_FCOE
 810                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 811                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 812                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 813                         if (!ddp_bytes)
 814                                 goto next_desc;
 815                 }
 816 #endif /* IXGBE_FCOE */
 817                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 818
 819 next_desc:
 820                 rx_desc->wb.upper.status_error = 0;
 821
 822                 /* return some buffers to hardware, one at a time is too slow */
 823                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 824                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 825                         cleaned_count = 0;
 826                 }
 827
 828                 /* use prefetched values */
 829                 rx_desc = next_rxd;
 830                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 831
 832                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 833         }
 834
 835         rx_ring->next_to_clean = i;
 836         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 837
 838         if (cleaned_count)
 839                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 840
 841 #ifdef IXGBE_FCOE
 842         /* include DDPed FCoE data */
 843         if (ddp_bytes > 0) {
 844                 unsigned int mss;
 845
 846                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 847                         sizeof(struct fc_frame_header) -
 848                         sizeof(struct fcoe_crc_eof);
 849                 if (mss > 512)
 850                         mss &= ~511;
 851                 total_rx_bytes += ddp_bytes;
 852                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 853         }
 854 #endif /* IXGBE_FCOE */
 855
 856         rx_ring->total_packets += total_rx_packets;
 857         rx_ring->total_bytes += total_rx_bytes;
 858         adapter->net_stats.rx_bytes += total_rx_bytes;
 859         adapter->net_stats.rx_packets += total_rx_packets;
 860
 861         return cleaned;
 862 }
 863
 864 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 865 /**
 866  * ixgbe_configure_msix - Configure MSI-X hardware
 867  * @adapter: board private structure
 868  *
 869  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 870  * interrupts.
 871  **/
 872 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 873 {
 874         struct ixgbe_q_vector *q_vector;
 875         int i, j, q_vectors, v_idx, r_idx;
 876         u32 mask;
 877
 878         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 879
 880         /*
 881          * Populate the IVAR table and set the ITR values to the
 882          * corresponding register.
 883          */
 884         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 885                 q_vector = adapter->q_vector[v_idx];
 886                 /* XXX for_each_bit(...) */
 887                 r_idx = find_first_bit(q_vector->rxr_idx,
 888                                        adapter->num_rx_queues);
 889
 890                 for (i = 0; i < q_vector->rxr_count; i++) {
 891                         j = adapter->rx_ring[r_idx].reg_idx;
 892                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 893                         r_idx = find_next_bit(q_vector->rxr_idx,
 894                                               adapter->num_rx_queues,
 895                                               r_idx + 1);
 896                 }
 897                 r_idx = find_first_bit(q_vector->txr_idx,
 898                                        adapter->num_tx_queues);
 899
 900                 for (i = 0; i < q_vector->txr_count; i++) {
 901                         j = adapter->tx_ring[r_idx].reg_idx;
 902                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 903                         r_idx = find_next_bit(q_vector->txr_idx,
 904                                               adapter->num_tx_queues,
 905                                               r_idx + 1);
 906                 }
 907
 908                 /* if this is a tx only vector halve the interrupt rate */
 909                 if (q_vector->txr_count && !q_vector->rxr_count)
 910                         q_vector->eitr = (adapter->eitr_param >> 1);
 911                 else if (q_vector->rxr_count)
 912                         /* rx only */
 913                         q_vector->eitr = adapter->eitr_param;
 914
 915                 ixgbe_write_eitr(q_vector);
 916         }
 917
 918         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 919                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 920                                v_idx);
 921         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 922                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 923         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 924
 925         /* set up to autoclear timer, and the vectors */
 926         mask = IXGBE_EIMS_ENABLE_MASK;
 927         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 928         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 929 }
 930
 931 enum latency_range {
 932         lowest_latency = 0,
 933         low_latency = 1,
 934         bulk_latency = 2,
 935         latency_invalid = 255
 936 };
 937
 938 /**
 939  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 940  * @adapter: pointer to adapter
 941  * @eitr: eitr setting (ints per sec) to give last timeslice
 942  * @itr_setting: current throttle rate in ints/second
 943  * @packets: the number of packets during this measurement interval
 944  * @bytes: the number of bytes during this measurement interval
 945  *
 946  *      Stores a new ITR value based on packets and byte
 947  *      counts during the last interrupt.  The advantage of per interrupt
 948  *      computation is faster updates and more accurate ITR for the current
 949  *      traffic pattern.  Constants in this function were computed
 950  *      based on theoretical maximum wire speed and thresholds were set based
 951  *      on testing data as well as attempting to minimize response time
 952  *      while increasing bulk throughput.
 953  *      this functionality is controlled by the InterruptThrottleRate module
 954  *      parameter (see ixgbe_param.c)
 955  **/
 956 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 957                            u32 eitr, u8 itr_setting,
 958                            int packets, int bytes)
 959 {
 960         unsigned int retval = itr_setting;
 961         u32 timepassed_us;
 962         u64 bytes_perint;
 963
 964         if (packets == 0)
 965                 goto update_itr_done;
 966
 967
 968         /* simple throttlerate management
 969          *    0-20MB/s lowest (100000 ints/s)
 970          *   20-100MB/s low   (20000 ints/s)
 971          *  100-1249MB/s bulk (8000 ints/s)
 972          */
 973         /* what was last interrupt timeslice? */
 974         timepassed_us = 1000000/eitr;
 975         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 976
 977         switch (itr_setting) {
 978         case lowest_latency:
 979                 if (bytes_perint > adapter->eitr_low)
 980                         retval = low_latency;
 981                 break;
 982         case low_latency:
 983                 if (bytes_perint > adapter->eitr_high)
 984                         retval = bulk_latency;
 985                 else if (bytes_perint <= adapter->eitr_low)
 986                         retval = lowest_latency;
 987                 break;
 988         case bulk_latency:
 989                 if (bytes_perint <= adapter->eitr_high)
 990                         retval = low_latency;
 991                 break;
 992         }
 993
 994 update_itr_done:
 995         return retval;
 996 }
 997
 998 /**
 999  * ixgbe_write_eitr - write EITR register in hardware specific way
1000  * @q_vector: structure containing interrupt and ring information
1001  *
1002  * This function is made to be called by ethtool and by the driver
1003  * when it needs to update EITR registers at runtime.  Hardware
1004  * specific quirks/differences are taken care of here.
1005  */
1006 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1007 {
1008         struct ixgbe_adapter *adapter = q_vector->adapter;
1009         struct ixgbe_hw *hw = &adapter->hw;
1010         int v_idx = q_vector->v_idx;
1011         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1012
1013         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1014                 /* must write high and low 16 bits to reset counter */
1015                 itr_reg |= (itr_reg << 16);
1016         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1017                 /*
1018                  * set the WDIS bit to not clear the timer bits and cause an
1019                  * immediate assertion of the interrupt
1020                  */
1021                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1022         }
1023         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1024 }
1025
1026 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1027 {
1028         struct ixgbe_adapter *adapter = q_vector->adapter;
1029         u32 new_itr;
1030         u8 current_itr, ret_itr;
1031         int i, r_idx;
1032         struct ixgbe_ring *rx_ring, *tx_ring;
1033
1034         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1035         for (i = 0; i < q_vector->txr_count; i++) {
1036                 tx_ring = &(adapter->tx_ring[r_idx]);
1037                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1038                                            q_vector->tx_itr,
1039                                            tx_ring->total_packets,
1040                                            tx_ring->total_bytes);
1041                 /* if the result for this queue would decrease interrupt
1042                  * rate for this vector then use that result */
1043                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1044                                     q_vector->tx_itr - 1 : ret_itr);
1045                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1046                                       r_idx + 1);
1047         }
1048
1049         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1050         for (i = 0; i < q_vector->rxr_count; i++) {
1051                 rx_ring = &(adapter->rx_ring[r_idx]);
1052                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1053                                            q_vector->rx_itr,
1054                                            rx_ring->total_packets,
1055                                            rx_ring->total_bytes);
1056                 /* if the result for this queue would decrease interrupt
1057                  * rate for this vector then use that result */
1058                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1059                                     q_vector->rx_itr - 1 : ret_itr);
1060                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1061                                       r_idx + 1);
1062         }
1063
1064         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1065
1066         switch (current_itr) {
1067         /* counts and packets in update_itr are dependent on these numbers */
1068         case lowest_latency:
1069                 new_itr = 100000;
1070                 break;
1071         case low_latency:
1072                 new_itr = 20000; /* aka hwitr = ~200 */
1073                 break;
1074         case bulk_latency:
1075         default:
1076                 new_itr = 8000;
1077                 break;
1078         }
1079
1080         if (new_itr != q_vector->eitr) {
1081                 /* do an exponential smoothing */
1082                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1083
1084                 /* save the algorithm value here, not the smoothed one */
1085                 q_vector->eitr = new_itr;
1086
1087                 ixgbe_write_eitr(q_vector);
1088         }
1089
1090         return;
1091 }
1092
1093 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1094 {
1095         struct ixgbe_hw *hw = &adapter->hw;
1096
1097         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1098             (eicr & IXGBE_EICR_GPI_SDP1)) {
1099                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1100                 /* write to clear the interrupt */
1101                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1102         }
1103 }
1104
1105 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1106 {
1107         struct ixgbe_hw *hw = &adapter->hw;
1108
1109         if (eicr & IXGBE_EICR_GPI_SDP1) {
1110                 /* Clear the interrupt */
1111                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1112                 schedule_work(&adapter->multispeed_fiber_task);
1113         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1114                 /* Clear the interrupt */
1115                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1116                 schedule_work(&adapter->sfp_config_module_task);
1117         } else {
1118                 /* Interrupt isn't for us... */
1119                 return;
1120         }
1121 }
1122
1123 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1124 {
1125         struct ixgbe_hw *hw = &adapter->hw;
1126
1127         adapter->lsc_int++;
1128         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1129         adapter->link_check_timeout = jiffies;
1130         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1131                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1132                 schedule_work(&adapter->watchdog_task);
1133         }
1134 }
1135
1136 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1137 {
1138         struct net_device *netdev = data;
1139         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1140         struct ixgbe_hw *hw = &adapter->hw;
1141         u32 eicr;
1142
1143         /*
1144          * Workaround for Silicon errata.  Use clear-by-write instead
1145          * of clear-by-read.  Reading with EICS will return the
1146          * interrupt causes without clearing, which later be done
1147          * with the write to EICR.
1148          */
1149         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1150         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1151
1152         if (eicr & IXGBE_EICR_LSC)
1153                 ixgbe_check_lsc(adapter);
1154
1155         if (hw->mac.type == ixgbe_mac_82598EB)
1156                 ixgbe_check_fan_failure(adapter, eicr);
1157
1158         if (hw->mac.type == ixgbe_mac_82599EB) {
1159                 ixgbe_check_sfp_event(adapter, eicr);
1160
1161                 /* Handle Flow Director Full threshold interrupt */
1162                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1163                         int i;
1164                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1165                         /* Disable transmits before FDIR Re-initialization */
1166                         netif_tx_stop_all_queues(netdev);
1167                         for (i = 0; i < adapter->num_tx_queues; i++) {
1168                                 struct ixgbe_ring *tx_ring =
1169                                                            &adapter->tx_ring[i];
1170                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1171                                                        &tx_ring->reinit_state))
1172                                         schedule_work(&adapter->fdir_reinit_task);
1173                         }
1174                 }
1175         }
1176         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1177                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1178
1179         return IRQ_HANDLED;
1180 }
1181
1182 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1183                                            u64 qmask)
1184 {
1185         u32 mask;
1186
1187         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1188                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1189                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1190         } else {
1191                 mask = (qmask & 0xFFFFFFFF);
1192                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1193                 mask = (qmask >> 32);
1194                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1195         }
1196         /* skip the flush */
1197 }
1198
1199 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1200                                             u64 qmask)
1201 {
1202         u32 mask;
1203
1204         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1207         } else {
1208                 mask = (qmask & 0xFFFFFFFF);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1210                 mask = (qmask >> 32);
1211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1212         }
1213         /* skip the flush */
1214 }
1215
1216 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1217 {
1218         struct ixgbe_q_vector *q_vector = data;
1219         struct ixgbe_adapter  *adapter = q_vector->adapter;
1220         struct ixgbe_ring     *tx_ring;
1221         int i, r_idx;
1222
1223         if (!q_vector->txr_count)
1224                 return IRQ_HANDLED;
1225
1226         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1227         for (i = 0; i < q_vector->txr_count; i++) {
1228                 tx_ring = &(adapter->tx_ring[r_idx]);
1229                 tx_ring->total_bytes = 0;
1230                 tx_ring->total_packets = 0;
1231                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1232                                       r_idx + 1);
1233         }
1234
1235         /* disable interrupts on this vector only */
1236         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1237         napi_schedule(&q_vector->napi);
1238
1239         return IRQ_HANDLED;
1240 }
1241
1242 /**
1243  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1244  * @irq: unused
1245  * @data: pointer to our q_vector struct for this interrupt vector
1246  **/
1247 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1248 {
1249         struct ixgbe_q_vector *q_vector = data;
1250         struct ixgbe_adapter  *adapter = q_vector->adapter;
1251         struct ixgbe_ring  *rx_ring;
1252         int r_idx;
1253         int i;
1254
1255         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1256         for (i = 0;  i < q_vector->rxr_count; i++) {
1257                 rx_ring = &(adapter->rx_ring[r_idx]);
1258                 rx_ring->total_bytes = 0;
1259                 rx_ring->total_packets = 0;
1260                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1261                                       r_idx + 1);
1262         }
1263
1264         if (!q_vector->rxr_count)
1265                 return IRQ_HANDLED;
1266
1267         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1268         rx_ring = &(adapter->rx_ring[r_idx]);
1269         /* disable interrupts on this vector only */
1270         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1271         napi_schedule(&q_vector->napi);
1272
1273         return IRQ_HANDLED;
1274 }
1275
1276 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1277 {
1278         struct ixgbe_q_vector *q_vector = data;
1279         struct ixgbe_adapter  *adapter = q_vector->adapter;
1280         struct ixgbe_ring  *ring;
1281         int r_idx;
1282         int i;
1283
1284         if (!q_vector->txr_count && !q_vector->rxr_count)
1285                 return IRQ_HANDLED;
1286
1287         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1288         for (i = 0; i < q_vector->txr_count; i++) {
1289                 ring = &(adapter->tx_ring[r_idx]);
1290                 ring->total_bytes = 0;
1291                 ring->total_packets = 0;
1292                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1293                                       r_idx + 1);
1294         }
1295
1296         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1297         for (i = 0; i < q_vector->rxr_count; i++) {
1298                 ring = &(adapter->rx_ring[r_idx]);
1299                 ring->total_bytes = 0;
1300                 ring->total_packets = 0;
1301                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1302                                       r_idx + 1);
1303         }
1304
1305         /* disable interrupts on this vector only */
1306         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1307         napi_schedule(&q_vector->napi);
1308
1309         return IRQ_HANDLED;
1310 }
1311
1312 /**
1313  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1314  * @napi: napi struct with our devices info in it
1315  * @budget: amount of work driver is allowed to do this pass, in packets
1316  *
1317  * This function is optimized for cleaning one queue only on a single
1318  * q_vector!!!
1319  **/
1320 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1321 {
1322         struct ixgbe_q_vector *q_vector =
1323                                container_of(napi, struct ixgbe_q_vector, napi);
1324         struct ixgbe_adapter *adapter = q_vector->adapter;
1325         struct ixgbe_ring *rx_ring = NULL;
1326         int work_done = 0;
1327         long r_idx;
1328
1329         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1330         rx_ring = &(adapter->rx_ring[r_idx]);
1331 #ifdef CONFIG_IXGBE_DCA
1332         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1333                 ixgbe_update_rx_dca(adapter, rx_ring);
1334 #endif
1335
1336         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1337
1338         /* If all Rx work done, exit the polling mode */
1339         if (work_done < budget) {
1340                 napi_complete(napi);
1341                 if (adapter->itr_setting & 1)
1342                         ixgbe_set_itr_msix(q_vector);
1343                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1344                         ixgbe_irq_enable_queues(adapter,
1345                                                 ((u64)1 << q_vector->v_idx));
1346         }
1347
1348         return work_done;
1349 }
1350
1351 /**
1352  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1353  * @napi: napi struct with our devices info in it
1354  * @budget: amount of work driver is allowed to do this pass, in packets
1355  *
1356  * This function will clean more than one rx queue associated with a
1357  * q_vector.
1358  **/
1359 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1360 {
1361         struct ixgbe_q_vector *q_vector =
1362                                container_of(napi, struct ixgbe_q_vector, napi);
1363         struct ixgbe_adapter *adapter = q_vector->adapter;
1364         struct ixgbe_ring *ring = NULL;
1365         int work_done = 0, i;
1366         long r_idx;
1367         bool tx_clean_complete = true;
1368
1369         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1370         for (i = 0; i < q_vector->txr_count; i++) {
1371                 ring = &(adapter->tx_ring[r_idx]);
1372 #ifdef CONFIG_IXGBE_DCA
1373                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1374                         ixgbe_update_tx_dca(adapter, ring);
1375 #endif
1376                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1377                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1378                                       r_idx + 1);
1379         }
1380
1381         /* attempt to distribute budget to each queue fairly, but don't allow
1382          * the budget to go below 1 because we'll exit polling */
1383         budget /= (q_vector->rxr_count ?: 1);
1384         budget = max(budget, 1);
1385         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1386         for (i = 0; i < q_vector->rxr_count; i++) {
1387                 ring = &(adapter->rx_ring[r_idx]);
1388 #ifdef CONFIG_IXGBE_DCA
1389                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1390                         ixgbe_update_rx_dca(adapter, ring);
1391 #endif
1392                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1393                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1394                                       r_idx + 1);
1395         }
1396
1397         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1398         ring = &(adapter->rx_ring[r_idx]);
1399         /* If all Rx work done, exit the polling mode */
1400         if (work_done < budget) {
1401                 napi_complete(napi);
1402                 if (adapter->itr_setting & 1)
1403                         ixgbe_set_itr_msix(q_vector);
1404                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1405                         ixgbe_irq_enable_queues(adapter,
1406                                                 ((u64)1 << q_vector->v_idx));
1407                 return 0;
1408         }
1409
1410         return work_done;
1411 }
1412
1413 /**
1414  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1415  * @napi: napi struct with our devices info in it
1416  * @budget: amount of work driver is allowed to do this pass, in packets
1417  *
1418  * This function is optimized for cleaning one queue only on a single
1419  * q_vector!!!
1420  **/
1421 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1422 {
1423         struct ixgbe_q_vector *q_vector =
1424                                container_of(napi, struct ixgbe_q_vector, napi);
1425         struct ixgbe_adapter *adapter = q_vector->adapter;
1426         struct ixgbe_ring *tx_ring = NULL;
1427         int work_done = 0;
1428         long r_idx;
1429
1430         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1431         tx_ring = &(adapter->tx_ring[r_idx]);
1432 #ifdef CONFIG_IXGBE_DCA
1433         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1434                 ixgbe_update_tx_dca(adapter, tx_ring);
1435 #endif
1436
1437         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1438                 work_done = budget;
1439
1440         /* If all Rx work done, exit the polling mode */
1441         if (work_done < budget) {
1442                 napi_complete(napi);
1443                 if (adapter->itr_setting & 1)
1444                         ixgbe_set_itr_msix(q_vector);
1445                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1446                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1447         }
1448
1449         return work_done;
1450 }
1451
1452 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1453                                      int r_idx)
1454 {
1455         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1456
1457         set_bit(r_idx, q_vector->rxr_idx);
1458         q_vector->rxr_count++;
1459 }
1460
1461 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1462                                      int t_idx)
1463 {
1464         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1465
1466         set_bit(t_idx, q_vector->txr_idx);
1467         q_vector->txr_count++;
1468 }
1469
1470 /**
1471  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1472  * @adapter: board private structure to initialize
1473  * @vectors: allotted vector count for descriptor rings
1474  *
1475  * This function maps descriptor rings to the queue-specific vectors
1476  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1477  * one vector per ring/queue, but on a constrained vector budget, we
1478  * group the rings as "efficiently" as possible.  You would add new
1479  * mapping configurations in here.
1480  **/
1481 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1482                                       int vectors)
1483 {
1484         int v_start = 0;
1485         int rxr_idx = 0, txr_idx = 0;
1486         int rxr_remaining = adapter->num_rx_queues;
1487         int txr_remaining = adapter->num_tx_queues;
1488         int i, j;
1489         int rqpv, tqpv;
1490         int err = 0;
1491
1492         /* No mapping required if MSI-X is disabled. */
1493         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1494                 goto out;
1495
1496         /*
1497          * The ideal configuration...
1498          * We have enough vectors to map one per queue.
1499          */
1500         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1501                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1502                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1503
1504                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1505                         map_vector_to_txq(adapter, v_start, txr_idx);
1506
1507                 goto out;
1508         }
1509
1510         /*
1511          * If we don't have enough vectors for a 1-to-1
1512          * mapping, we'll have to group them so there are
1513          * multiple queues per vector.
1514          */
1515         /* Re-adjusting *qpv takes care of the remainder. */
1516         for (i = v_start; i < vectors; i++) {
1517                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1518                 for (j = 0; j < rqpv; j++) {
1519                         map_vector_to_rxq(adapter, i, rxr_idx);
1520                         rxr_idx++;
1521                         rxr_remaining--;
1522                 }
1523         }
1524         for (i = v_start; i < vectors; i++) {
1525                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1526                 for (j = 0; j < tqpv; j++) {
1527                         map_vector_to_txq(adapter, i, txr_idx);
1528                         txr_idx++;
1529                         txr_remaining--;
1530                 }
1531         }
1532
1533 out:
1534         return err;
1535 }
1536
1537 /**
1538  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1539  * @adapter: board private structure
1540  *
1541  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1542  * interrupts from the kernel.
1543  **/
1544 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1545 {
1546         struct net_device *netdev = adapter->netdev;
1547         irqreturn_t (*handler)(int, void *);
1548         int i, vector, q_vectors, err;
1549         int ri=0, ti=0;
1550
1551         /* Decrement for Other and TCP Timer vectors */
1552         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1553
1554         /* Map the Tx/Rx rings to the vectors we were allotted. */
1555         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1556         if (err)
1557                 goto out;
1558
1559 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1560                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1561                          &ixgbe_msix_clean_many)
1562         for (vector = 0; vector < q_vectors; vector++) {
1563                 handler = SET_HANDLER(adapter->q_vector[vector]);
1564
1565                 if(handler == &ixgbe_msix_clean_rx) {
1566                         sprintf(adapter->name[vector], "%s-%s-%d",
1567                                 netdev->name, "rx", ri++);
1568                 }
1569                 else if(handler == &ixgbe_msix_clean_tx) {
1570                         sprintf(adapter->name[vector], "%s-%s-%d",
1571                                 netdev->name, "tx", ti++);
1572                 }
1573                 else
1574                         sprintf(adapter->name[vector], "%s-%s-%d",
1575                                 netdev->name, "TxRx", vector);
1576
1577                 err = request_irq(adapter->msix_entries[vector].vector,
1578                                   handler, 0, adapter->name[vector],
1579                                   adapter->q_vector[vector]);
1580                 if (err) {
1581                         DPRINTK(PROBE, ERR,
1582                                 "request_irq failed for MSIX interrupt "
1583                                 "Error: %d\n", err);
1584                         goto free_queue_irqs;
1585                 }
1586         }
1587
1588         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1589         err = request_irq(adapter->msix_entries[vector].vector,
1590                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1591         if (err) {
1592                 DPRINTK(PROBE, ERR,
1593                         "request_irq for msix_lsc failed: %d\n", err);
1594                 goto free_queue_irqs;
1595         }
1596
1597         return 0;
1598
1599 free_queue_irqs:
1600         for (i = vector - 1; i >= 0; i--)
1601                 free_irq(adapter->msix_entries[--vector].vector,
1602                          adapter->q_vector[i]);
1603         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1604         pci_disable_msix(adapter->pdev);
1605         kfree(adapter->msix_entries);
1606         adapter->msix_entries = NULL;
1607 out:
1608         return err;
1609 }
1610
1611 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1612 {
1613         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1614         u8 current_itr;
1615         u32 new_itr = q_vector->eitr;
1616         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1617         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1618
1619         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1620                                             q_vector->tx_itr,
1621                                             tx_ring->total_packets,
1622                                             tx_ring->total_bytes);
1623         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1624                                             q_vector->rx_itr,
1625                                             rx_ring->total_packets,
1626                                             rx_ring->total_bytes);
1627
1628         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1629
1630         switch (current_itr) {
1631         /* counts and packets in update_itr are dependent on these numbers */
1632         case lowest_latency:
1633                 new_itr = 100000;
1634                 break;
1635         case low_latency:
1636                 new_itr = 20000; /* aka hwitr = ~200 */
1637                 break;
1638         case bulk_latency:
1639                 new_itr = 8000;
1640                 break;
1641         default:
1642                 break;
1643         }
1644
1645         if (new_itr != q_vector->eitr) {
1646                 /* do an exponential smoothing */
1647                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1648
1649                 /* save the algorithm value here, not the smoothed one */
1650                 q_vector->eitr = new_itr;
1651
1652                 ixgbe_write_eitr(q_vector);
1653         }
1654
1655         return;
1656 }
1657
1658 /**
1659  * ixgbe_irq_enable - Enable default interrupt generation settings
1660  * @adapter: board private structure
1661  **/
1662 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1663 {
1664         u32 mask;
1665
1666         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1667         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1668                 mask |= IXGBE_EIMS_GPI_SDP1;
1669         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1670                 mask |= IXGBE_EIMS_ECC;
1671                 mask |= IXGBE_EIMS_GPI_SDP1;
1672                 mask |= IXGBE_EIMS_GPI_SDP2;
1673         }
1674         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1675             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1676                 mask |= IXGBE_EIMS_FLOW_DIR;
1677
1678         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1679         ixgbe_irq_enable_queues(adapter, ~0);
1680         IXGBE_WRITE_FLUSH(&adapter->hw);
1681 }
1682
1683 /**
1684  * ixgbe_intr - legacy mode Interrupt Handler
1685  * @irq: interrupt number
1686  * @data: pointer to a network interface device structure
1687  **/
1688 static irqreturn_t ixgbe_intr(int irq, void *data)
1689 {
1690         struct net_device *netdev = data;
1691         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1692         struct ixgbe_hw *hw = &adapter->hw;
1693         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1694         u32 eicr;
1695
1696         /*
1697          * Workaround for silicon errata.  Mask the interrupts
1698          * before the read of EICR.
1699          */
1700         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1701
1702         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1703          * therefore no explict interrupt disable is necessary */
1704         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1705         if (!eicr) {
1706                 /* shared interrupt alert!
1707                  * make sure interrupts are enabled because the read will
1708                  * have disabled interrupts due to EIAM */
1709                 ixgbe_irq_enable(adapter);
1710                 return IRQ_NONE;        /* Not our interrupt */
1711         }
1712
1713         if (eicr & IXGBE_EICR_LSC)
1714                 ixgbe_check_lsc(adapter);
1715
1716         if (hw->mac.type == ixgbe_mac_82599EB)
1717                 ixgbe_check_sfp_event(adapter, eicr);
1718
1719         ixgbe_check_fan_failure(adapter, eicr);
1720
1721         if (napi_schedule_prep(&(q_vector->napi))) {
1722                 adapter->tx_ring[0].total_packets = 0;
1723                 adapter->tx_ring[0].total_bytes = 0;
1724                 adapter->rx_ring[0].total_packets = 0;
1725                 adapter->rx_ring[0].total_bytes = 0;
1726                 /* would disable interrupts here but EIAM disabled it */
1727                 __napi_schedule(&(q_vector->napi));
1728         }
1729
1730         return IRQ_HANDLED;
1731 }
1732
1733 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1734 {
1735         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1736
1737         for (i = 0; i < q_vectors; i++) {
1738                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1739                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1740                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1741                 q_vector->rxr_count = 0;
1742                 q_vector->txr_count = 0;
1743         }
1744 }
1745
1746 /**
1747  * ixgbe_request_irq - initialize interrupts
1748  * @adapter: board private structure
1749  *
1750  * Attempts to configure interrupts using the best available
1751  * capabilities of the hardware and kernel.
1752  **/
1753 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1754 {
1755         struct net_device *netdev = adapter->netdev;
1756         int err;
1757
1758         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1759                 err = ixgbe_request_msix_irqs(adapter);
1760         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1761                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1762                                   netdev->name, netdev);
1763         } else {
1764                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1765                                   netdev->name, netdev);
1766         }
1767
1768         if (err)
1769                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1770
1771         return err;
1772 }
1773
1774 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1775 {
1776         struct net_device *netdev = adapter->netdev;
1777
1778         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1779                 int i, q_vectors;
1780
1781                 q_vectors = adapter->num_msix_vectors;
1782
1783                 i = q_vectors - 1;
1784                 free_irq(adapter->msix_entries[i].vector, netdev);
1785
1786                 i--;
1787                 for (; i >= 0; i--) {
1788                         free_irq(adapter->msix_entries[i].vector,
1789                                  adapter->q_vector[i]);
1790                 }
1791
1792                 ixgbe_reset_q_vectors(adapter);
1793         } else {
1794                 free_irq(adapter->pdev->irq, netdev);
1795         }
1796 }
1797
1798 /**
1799  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1800  * @adapter: board private structure
1801  **/
1802 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1803 {
1804         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1805                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1806         } else {
1807                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1808                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1809                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1810         }
1811         IXGBE_WRITE_FLUSH(&adapter->hw);
1812         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1813                 int i;
1814                 for (i = 0; i < adapter->num_msix_vectors; i++)
1815                         synchronize_irq(adapter->msix_entries[i].vector);
1816         } else {
1817                 synchronize_irq(adapter->pdev->irq);
1818         }
1819 }
1820
1821 /**
1822  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1823  *
1824  **/
1825 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1826 {
1827         struct ixgbe_hw *hw = &adapter->hw;
1828
1829         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1830                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1831
1832         ixgbe_set_ivar(adapter, 0, 0, 0);
1833         ixgbe_set_ivar(adapter, 1, 0, 0);
1834
1835         map_vector_to_rxq(adapter, 0, 0);
1836         map_vector_to_txq(adapter, 0, 0);
1837
1838         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1839 }
1840
1841 /**
1842  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1843  * @adapter: board private structure
1844  *
1845  * Configure the Tx unit of the MAC after a reset.
1846  **/
1847 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1848 {
1849         u64 tdba;
1850         struct ixgbe_hw *hw = &adapter->hw;
1851         u32 i, j, tdlen, txctrl;
1852
1853         /* Setup the HW Tx Head and Tail descriptor pointers */
1854         for (i = 0; i < adapter->num_tx_queues; i++) {
1855                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1856                 j = ring->reg_idx;
1857                 tdba = ring->dma;
1858                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1859                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1860                                 (tdba & DMA_BIT_MASK(32)));
1861                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1862                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1863                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1864                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1865                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1866                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1867                 /* Disable Tx Head Writeback RO bit, since this hoses
1868                  * bookkeeping if things aren't delivered in order.
1869                  */
1870                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1871                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1872                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1873         }
1874         if (hw->mac.type == ixgbe_mac_82599EB) {
1875                 /* We enable 8 traffic classes, DCB only */
1876                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1877                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1878                                         IXGBE_MTQC_8TC_8TQ));
1879         }
1880 }
1881
1882 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1883
1884 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1885 {
1886         struct ixgbe_ring *rx_ring;
1887         u32 srrctl;
1888         int queue0 = 0;
1889         unsigned long mask;
1890         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1891
1892         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1893                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1894                         int dcb_i = feature[RING_F_DCB].indices;
1895                         if (dcb_i == 8)
1896                                 queue0 = index >> 4;
1897                         else if (dcb_i == 4)
1898                                 queue0 = index >> 5;
1899                         else
1900                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1901                                         "configuration\n");
1902 #ifdef IXGBE_FCOE
1903                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1904                                 struct ixgbe_ring_feature *f;
1905
1906                                 rx_ring = &adapter->rx_ring[queue0];
1907                                 f = &adapter->ring_feature[RING_F_FCOE];
1908                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1909                                         queue0 = f->mask + index -
1910                                                  rx_ring->reg_idx - 1;
1911                         }
1912 #endif /* IXGBE_FCOE */
1913                 } else {
1914                         queue0 = index;
1915                 }
1916         } else {
1917                 mask = (unsigned long) feature[RING_F_RSS].mask;
1918                 queue0 = index & mask;
1919                 index = index & mask;
1920         }
1921
1922         rx_ring = &adapter->rx_ring[queue0];
1923
1924         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1925
1926         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1927         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1928
1929         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1930                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1931
1932         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1933 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1934                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1935 #else
1936                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1937 #endif
1938                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1939         } else {
1940                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1941                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1942                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1943         }
1944
1945         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1946 }
1947
1948 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1949 {
1950         u32 mrqc = 0;
1951         int mask;
1952
1953         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1954                 return mrqc;
1955
1956         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1957 #ifdef CONFIG_IXGBE_DCB
1958                                  | IXGBE_FLAG_DCB_ENABLED
1959 #endif
1960                                 );
1961
1962         switch (mask) {
1963         case (IXGBE_FLAG_RSS_ENABLED):
1964                 mrqc = IXGBE_MRQC_RSSEN;
1965                 break;
1966 #ifdef CONFIG_IXGBE_DCB
1967         case (IXGBE_FLAG_DCB_ENABLED):
1968                 mrqc = IXGBE_MRQC_RT8TCEN;
1969                 break;
1970 #endif /* CONFIG_IXGBE_DCB */
1971         default:
1972                 break;
1973         }
1974
1975         return mrqc;
1976 }
1977
1978 /**
1979  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1980  * @adapter: board private structure
1981  *
1982  * Configure the Rx unit of the MAC after a reset.
1983  **/
1984 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1985 {
1986         u64 rdba;
1987         struct ixgbe_hw *hw = &adapter->hw;
1988         struct net_device *netdev = adapter->netdev;
1989         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1990         int i, j;
1991         u32 rdlen, rxctrl, rxcsum;
1992         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1993                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1994                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1995         u32 fctrl, hlreg0;
1996         u32 reta = 0, mrqc = 0;
1997         u32 rdrxctl;
1998         u32 rscctrl;
1999         int rx_buf_len;
2000
2001         /* Decide whether to use packet split mode or not */
2002         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2003
2004 #ifdef IXGBE_FCOE
2005         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2006                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2007 #endif /* IXGBE_FCOE */
2008
2009         /* Set the RX buffer length according to the mode */
2010         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2011                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2012                 if (hw->mac.type == ixgbe_mac_82599EB) {
2013                         /* PSRTYPE must be initialized in 82599 */
2014                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2015                                       IXGBE_PSRTYPE_UDPHDR |
2016                                       IXGBE_PSRTYPE_IPV4HDR |
2017                                       IXGBE_PSRTYPE_IPV6HDR |
2018                                       IXGBE_PSRTYPE_L2HDR;
2019                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2020                 }
2021         } else {
2022                 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
2023                     (netdev->mtu <= ETH_DATA_LEN))
2024                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2025                 else
2026                         rx_buf_len = ALIGN(max_frame, 1024);
2027         }
2028
2029         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2030         fctrl |= IXGBE_FCTRL_BAM;
2031         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2032         fctrl |= IXGBE_FCTRL_PMCF;
2033         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2034
2035         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2036         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2037                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2038         else
2039                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2040 #ifdef IXGBE_FCOE
2041         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2042                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2043 #endif
2044         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2045
2046         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2047         /* disable receives while setting up the descriptors */
2048         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2049         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2050
2051         /*
2052          * Setup the HW Rx Head and Tail Descriptor Pointers and
2053          * the Base and Length of the Rx Descriptor Ring
2054          */
2055         for (i = 0; i < adapter->num_rx_queues; i++) {
2056                 rdba = adapter->rx_ring[i].dma;
2057                 j = adapter->rx_ring[i].reg_idx;
2058                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2059                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2060                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2061                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2062                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2063                 adapter->rx_ring[i].head = IXGBE_RDH(j);
2064                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2065                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2066
2067 #ifdef IXGBE_FCOE
2068                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2069                         struct ixgbe_ring_feature *f;
2070                         f = &adapter->ring_feature[RING_F_FCOE];
2071                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2072                             (i >= f->mask) && (i < f->mask + f->indices))
2073                                 adapter->rx_ring[i].rx_buf_len =
2074                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
2075                 }
2076
2077 #endif /* IXGBE_FCOE */
2078                 ixgbe_configure_srrctl(adapter, j);
2079         }
2080
2081         if (hw->mac.type == ixgbe_mac_82598EB) {
2082                 /*
2083                  * For VMDq support of different descriptor types or
2084                  * buffer sizes through the use of multiple SRRCTL
2085                  * registers, RDRXCTL.MVMEN must be set to 1
2086                  *
2087                  * also, the manual doesn't mention it clearly but DCA hints
2088                  * will only use queue 0's tags unless this bit is set.  Side
2089                  * effects of setting this bit are only that SRRCTL must be
2090                  * fully programmed [0..15]
2091                  */
2092                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2093                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2094                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2095         }
2096
2097         /* Program MRQC for the distribution of queues */
2098         mrqc = ixgbe_setup_mrqc(adapter);
2099
2100         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2101                 /* Fill out redirection table */
2102                 for (i = 0, j = 0; i < 128; i++, j++) {
2103                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2104                                 j = 0;
2105                         /* reta = 4-byte sliding window of
2106                          * 0x00..(indices-1)(indices-1)00..etc. */
2107                         reta = (reta << 8) | (j * 0x11);
2108                         if ((i & 3) == 3)
2109                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2110                 }
2111
2112                 /* Fill out hash function seeds */
2113                 for (i = 0; i < 10; i++)
2114                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2115
2116                 if (hw->mac.type == ixgbe_mac_82598EB)
2117                         mrqc |= IXGBE_MRQC_RSSEN;
2118                     /* Perform hash on these packet types */
2119                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2120                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2121                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2122                       | IXGBE_MRQC_RSS_FIELD_IPV6
2123                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2124                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2125         }
2126         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2127
2128         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2129
2130         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2131             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2132                 /* Disable indicating checksum in descriptor, enables
2133                  * RSS hash */
2134                 rxcsum |= IXGBE_RXCSUM_PCSD;
2135         }
2136         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2137                 /* Enable IPv4 payload checksum for UDP fragments
2138                  * if PCSD is not set */
2139                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2140         }
2141
2142         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2143
2144         if (hw->mac.type == ixgbe_mac_82599EB) {
2145                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2146                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2147                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2148                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2149         }
2150
2151         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
2152                 /* Enable 82599 HW-RSC */
2153                 for (i = 0; i < adapter->num_rx_queues; i++) {
2154                         j = adapter->rx_ring[i].reg_idx;
2155                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2156                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2157                         /*
2158                          * we must limit the number of descriptors so that the
2159                          * total size of max desc * buf_len is not greater
2160                          * than 65535
2161                          */
2162                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2163 #if (MAX_SKB_FRAGS > 16)
2164                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2165 #elif (MAX_SKB_FRAGS > 8)
2166                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2167 #elif (MAX_SKB_FRAGS > 4)
2168                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2169 #else
2170                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2171 #endif
2172                         } else {
2173                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2174                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2175                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2176                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2177                                 else
2178                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2179                         }
2180                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2181                 }
2182                 /* Disable RSC for ACK packets */
2183                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2184                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2185         }
2186 }
2187
2188 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2189 {
2190         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2191         struct ixgbe_hw *hw = &adapter->hw;
2192
2193         /* add VID to filter table */
2194         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2195 }
2196
2197 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2198 {
2199         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2200         struct ixgbe_hw *hw = &adapter->hw;
2201
2202         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203                 ixgbe_irq_disable(adapter);
2204
2205         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2206
2207         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2208                 ixgbe_irq_enable(adapter);
2209
2210         /* remove VID from filter table */
2211         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2212 }
2213
2214 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2215                                    struct vlan_group *grp)
2216 {
2217         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2218         u32 ctrl;
2219         int i, j;
2220
2221         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2222                 ixgbe_irq_disable(adapter);
2223         adapter->vlgrp = grp;
2224
2225         /*
2226          * For a DCB driver, always enable VLAN tag stripping so we can
2227          * still receive traffic from a DCB-enabled host even if we're
2228          * not in DCB mode.
2229          */
2230         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2231         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2232                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2233                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2234                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2235         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2236                 ctrl |= IXGBE_VLNCTRL_VFE;
2237                 /* enable VLAN tag insert/strip */
2238                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2239                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2240                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2241                 for (i = 0; i < adapter->num_rx_queues; i++) {
2242                         j = adapter->rx_ring[i].reg_idx;
2243                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2244                         ctrl |= IXGBE_RXDCTL_VME;
2245                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2246                 }
2247         }
2248         ixgbe_vlan_rx_add_vid(netdev, 0);
2249
2250         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2251                 ixgbe_irq_enable(adapter);
2252 }
2253
2254 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2255 {
2256         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2257
2258         if (adapter->vlgrp) {
2259                 u16 vid;
2260                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2261                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2262                                 continue;
2263                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2264                 }
2265         }
2266 }
2267
2268 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2269 {
2270         struct dev_mc_list *mc_ptr;
2271         u8 *addr = *mc_addr_ptr;
2272         *vmdq = 0;
2273
2274         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2275         if (mc_ptr->next)
2276                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2277         else
2278                 *mc_addr_ptr = NULL;
2279
2280         return addr;
2281 }
2282
2283 /**
2284  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2285  * @netdev: network interface device structure
2286  *
2287  * The set_rx_method entry point is called whenever the unicast/multicast
2288  * address list or the network interface flags are updated.  This routine is
2289  * responsible for configuring the hardware for proper unicast, multicast and
2290  * promiscuous mode.
2291  **/
2292 static void ixgbe_set_rx_mode(struct net_device *netdev)
2293 {
2294         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2295         struct ixgbe_hw *hw = &adapter->hw;
2296         u32 fctrl, vlnctrl;
2297         u8 *addr_list = NULL;
2298         int addr_count = 0;
2299
2300         /* Check for Promiscuous and All Multicast modes */
2301
2302         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2303         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2304
2305         if (netdev->flags & IFF_PROMISC) {
2306                 hw->addr_ctrl.user_set_promisc = 1;
2307                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2308                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2309         } else {
2310                 if (netdev->flags & IFF_ALLMULTI) {
2311                         fctrl |= IXGBE_FCTRL_MPE;
2312                         fctrl &= ~IXGBE_FCTRL_UPE;
2313                 } else {
2314                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2315                 }
2316                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2317                 hw->addr_ctrl.user_set_promisc = 0;
2318         }
2319
2320         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2321         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2322
2323         /* reprogram secondary unicast list */
2324         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2325
2326         /* reprogram multicast list */
2327         addr_count = netdev->mc_count;
2328         if (addr_count)
2329                 addr_list = netdev->mc_list->dmi_addr;
2330         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2331                                         ixgbe_addr_list_itr);
2332 }
2333
2334 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2335 {
2336         int q_idx;
2337         struct ixgbe_q_vector *q_vector;
2338         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2339
2340         /* legacy and MSI only use one vector */
2341         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2342                 q_vectors = 1;
2343
2344         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2345                 struct napi_struct *napi;
2346                 q_vector = adapter->q_vector[q_idx];
2347                 napi = &q_vector->napi;
2348                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2349                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2350                                 if (q_vector->txr_count == 1)
2351                                         napi->poll = &ixgbe_clean_txonly;
2352                                 else if (q_vector->rxr_count == 1)
2353                                         napi->poll = &ixgbe_clean_rxonly;
2354                         }
2355                 }
2356
2357                 napi_enable(napi);
2358         }
2359 }
2360
2361 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2362 {
2363         int q_idx;
2364         struct ixgbe_q_vector *q_vector;
2365         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2366
2367         /* legacy and MSI only use one vector */
2368         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2369                 q_vectors = 1;
2370
2371         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2372                 q_vector = adapter->q_vector[q_idx];
2373                 napi_disable(&q_vector->napi);
2374         }
2375 }
2376
2377 #ifdef CONFIG_IXGBE_DCB
2378 /*
2379  * ixgbe_configure_dcb - Configure DCB hardware
2380  * @adapter: ixgbe adapter struct
2381  *
2382  * This is called by the driver on open to configure the DCB hardware.
2383  * This is also called by the gennetlink interface when reconfiguring
2384  * the DCB state.
2385  */
2386 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2387 {
2388         struct ixgbe_hw *hw = &adapter->hw;
2389         u32 txdctl, vlnctrl;
2390         int i, j;
2391
2392         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2393         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2394         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2395
2396         /* reconfigure the hardware */
2397         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2398
2399         for (i = 0; i < adapter->num_tx_queues; i++) {
2400                 j = adapter->tx_ring[i].reg_idx;
2401                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2402                 /* PThresh workaround for Tx hang with DFP enabled. */
2403                 txdctl |= 32;
2404                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2405         }
2406         /* Enable VLAN tag insert/strip */
2407         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2408         if (hw->mac.type == ixgbe_mac_82598EB) {
2409                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2410                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2411                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2412         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2413                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2414                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2415                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2416                 for (i = 0; i < adapter->num_rx_queues; i++) {
2417                         j = adapter->rx_ring[i].reg_idx;
2418                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2419                         vlnctrl |= IXGBE_RXDCTL_VME;
2420                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2421                 }
2422         }
2423         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2424 }
2425
2426 #endif
2427 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2428 {
2429         struct net_device *netdev = adapter->netdev;
2430         struct ixgbe_hw *hw = &adapter->hw;
2431         int i;
2432
2433         ixgbe_set_rx_mode(netdev);
2434
2435         ixgbe_restore_vlan(adapter);
2436 #ifdef CONFIG_IXGBE_DCB
2437         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2438                 netif_set_gso_max_size(netdev, 32768);
2439                 ixgbe_configure_dcb(adapter);
2440         } else {
2441                 netif_set_gso_max_size(netdev, 65536);
2442         }
2443 #else
2444         netif_set_gso_max_size(netdev, 65536);
2445 #endif
2446
2447 #ifdef IXGBE_FCOE
2448         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2449                 ixgbe_configure_fcoe(adapter);
2450
2451 #endif /* IXGBE_FCOE */
2452         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2453                 for (i = 0; i < adapter->num_tx_queues; i++)
2454                         adapter->tx_ring[i].atr_sample_rate =
2455                                                        adapter->atr_sample_rate;
2456                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2457         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2458                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2459         }
2460
2461         ixgbe_configure_tx(adapter);
2462         ixgbe_configure_rx(adapter);
2463         for (i = 0; i < adapter->num_rx_queues; i++)
2464                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2465                                        (adapter->rx_ring[i].count - 1));
2466 }
2467
2468 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2469 {
2470         switch (hw->phy.type) {
2471         case ixgbe_phy_sfp_avago:
2472         case ixgbe_phy_sfp_ftl:
2473         case ixgbe_phy_sfp_intel:
2474         case ixgbe_phy_sfp_unknown:
2475         case ixgbe_phy_tw_tyco:
2476         case ixgbe_phy_tw_unknown:
2477                 return true;
2478         default:
2479                 return false;
2480         }
2481 }
2482
2483 /**
2484  * ixgbe_sfp_link_config - set up SFP+ link
2485  * @adapter: pointer to private adapter struct
2486  **/
2487 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2488 {
2489         struct ixgbe_hw *hw = &adapter->hw;
2490
2491                 if (hw->phy.multispeed_fiber) {
2492                         /*
2493                          * In multispeed fiber setups, the device may not have
2494                          * had a physical connection when the driver loaded.
2495                          * If that's the case, the initial link configuration
2496                          * couldn't get the MAC into 10G or 1G mode, so we'll
2497                          * never have a link status change interrupt fire.
2498                          * We need to try and force an autonegotiation
2499                          * session, then bring up link.
2500                          */
2501                         hw->mac.ops.setup_sfp(hw);
2502                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2503                                 schedule_work(&adapter->multispeed_fiber_task);
2504                 } else {
2505                         /*
2506                          * Direct Attach Cu and non-multispeed fiber modules
2507                          * still need to be configured properly prior to
2508                          * attempting link.
2509                          */
2510                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2511                                 schedule_work(&adapter->sfp_config_module_task);
2512                 }
2513 }
2514
2515 /**
2516  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2517  * @hw: pointer to private hardware struct
2518  *
2519  * Returns 0 on success, negative on failure
2520  **/
2521 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2522 {
2523         u32 autoneg;
2524         bool link_up = false;
2525         u32 ret = IXGBE_ERR_LINK_SETUP;
2526
2527         if (hw->mac.ops.check_link)
2528                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2529
2530         if (ret)
2531                 goto link_cfg_out;
2532
2533         if (hw->mac.ops.get_link_capabilities)
2534                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2535                                                         &hw->mac.autoneg);
2536         if (ret)
2537                 goto link_cfg_out;
2538
2539         if (hw->mac.ops.setup_link_speed)
2540                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2541 link_cfg_out:
2542         return ret;
2543 }
2544
2545 #define IXGBE_MAX_RX_DESC_POLL 10
2546 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2547                                               int rxr)
2548 {
2549         int j = adapter->rx_ring[rxr].reg_idx;
2550         int k;
2551
2552         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2553                 if (IXGBE_READ_REG(&adapter->hw,
2554                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2555                         break;
2556                 else
2557                         msleep(1);
2558         }
2559         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2560                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2561                         "not set within the polling period\n", rxr);
2562         }
2563         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2564                               (adapter->rx_ring[rxr].count - 1));
2565 }
2566
2567 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2568 {
2569         struct net_device *netdev = adapter->netdev;
2570         struct ixgbe_hw *hw = &adapter->hw;
2571         int i, j = 0;
2572         int num_rx_rings = adapter->num_rx_queues;
2573         int err;
2574         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2575         u32 txdctl, rxdctl, mhadd;
2576         u32 dmatxctl;
2577         u32 gpie;
2578
2579         ixgbe_get_hw_control(adapter);
2580
2581         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2582             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2583                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2584                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2585                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2586                 } else {
2587                         /* MSI only */
2588                         gpie = 0;
2589                 }
2590                 /* XXX: to interrupt immediately for EICS writes, enable this */
2591                 /* gpie |= IXGBE_GPIE_EIMEN; */
2592                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2593         }
2594
2595         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2596                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2597                  * specifically only auto mask tx and rx interrupts */
2598                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2599         }
2600
2601         /* Enable fan failure interrupt if media type is copper */
2602         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2603                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2604                 gpie |= IXGBE_SDP1_GPIEN;
2605                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2606         }
2607
2608         if (hw->mac.type == ixgbe_mac_82599EB) {
2609                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2610                 gpie |= IXGBE_SDP1_GPIEN;
2611                 gpie |= IXGBE_SDP2_GPIEN;
2612                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2613         }
2614
2615 #ifdef IXGBE_FCOE
2616         /* adjust max frame to be able to do baby jumbo for FCoE */
2617         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2618             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2619                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2620
2621 #endif /* IXGBE_FCOE */
2622         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2623         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2624                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2625                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2626
2627                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2628         }
2629
2630         for (i = 0; i < adapter->num_tx_queues; i++) {
2631                 j = adapter->tx_ring[i].reg_idx;
2632                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2633                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2634                 txdctl |= (8 << 16);
2635                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2636         }
2637
2638         if (hw->mac.type == ixgbe_mac_82599EB) {
2639                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2640                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2641                 dmatxctl |= IXGBE_DMATXCTL_TE;
2642                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2643         }
2644         for (i = 0; i < adapter->num_tx_queues; i++) {
2645                 j = adapter->tx_ring[i].reg_idx;
2646                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2647                 txdctl |= IXGBE_TXDCTL_ENABLE;
2648                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2649         }
2650
2651         for (i = 0; i < num_rx_rings; i++) {
2652                 j = adapter->rx_ring[i].reg_idx;
2653                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2654                 /* enable PTHRESH=32 descriptors (half the internal cache)
2655                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2656                  * this also removes a pesky rx_no_buffer_count increment */
2657                 rxdctl |= 0x0020;
2658                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2659                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2660                 if (hw->mac.type == ixgbe_mac_82599EB)
2661                         ixgbe_rx_desc_queue_enable(adapter, i);
2662         }
2663         /* enable all receives */
2664         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2665         if (hw->mac.type == ixgbe_mac_82598EB)
2666                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2667         else
2668                 rxdctl |= IXGBE_RXCTRL_RXEN;
2669         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2670
2671         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2672                 ixgbe_configure_msix(adapter);
2673         else
2674                 ixgbe_configure_msi_and_legacy(adapter);
2675
2676         clear_bit(__IXGBE_DOWN, &adapter->state);
2677         ixgbe_napi_enable_all(adapter);
2678
2679         /* clear any pending interrupts, may auto mask */
2680         IXGBE_READ_REG(hw, IXGBE_EICR);
2681
2682         ixgbe_irq_enable(adapter);
2683
2684         /*
2685          * If this adapter has a fan, check to see if we had a failure
2686          * before we enabled the interrupt.
2687          */
2688         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2689                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2690                 if (esdp & IXGBE_ESDP_SDP1)
2691                         DPRINTK(DRV, CRIT,
2692                                 "Fan has stopped, replace the adapter\n");
2693         }
2694
2695         /*
2696          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2697          * arrived before interrupts were enabled.  We need to kick off
2698          * the SFP+ module setup first, then try to bring up link.
2699          * If we're not hot-pluggable SFP+, we just need to configure link
2700          * and bring it up.
2701          */
2702         err = hw->phy.ops.identify(hw);
2703         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2704                 dev_err(&adapter->pdev->dev, "failed to initialize because "
2705                         "an unsupported SFP+ module type was detected.\n"
2706                         "Reload the driver after installing a supported "
2707                         "module.\n");
2708                 ixgbe_down(adapter);
2709                 return err;
2710         }
2711
2712         if (ixgbe_is_sfp(hw)) {
2713                 ixgbe_sfp_link_config(adapter);
2714         } else {
2715                 err = ixgbe_non_sfp_link_config(hw);
2716                 if (err)
2717                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2718         }
2719
2720         for (i = 0; i < adapter->num_tx_queues; i++)
2721                 set_bit(__IXGBE_FDIR_INIT_DONE,
2722                         &(adapter->tx_ring[i].reinit_state));
2723
2724         /* enable transmits */
2725         netif_tx_start_all_queues(netdev);
2726
2727         /* bring the link up in the watchdog, this could race with our first
2728          * link up interrupt but shouldn't be a problem */
2729         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2730         adapter->link_check_timeout = jiffies;
2731         mod_timer(&adapter->watchdog_timer, jiffies);
2732         return 0;
2733 }
2734
2735 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2736 {
2737         WARN_ON(in_interrupt());
2738         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2739                 msleep(1);
2740         ixgbe_down(adapter);
2741         ixgbe_up(adapter);
2742         clear_bit(__IXGBE_RESETTING, &adapter->state);
2743 }
2744
2745 int ixgbe_up(struct ixgbe_adapter *adapter)
2746 {
2747         /* hardware has been reset, we need to reload some things */
2748         ixgbe_configure(adapter);
2749
2750         return ixgbe_up_complete(adapter);
2751 }
2752
2753 void ixgbe_reset(struct ixgbe_adapter *adapter)
2754 {
2755         struct ixgbe_hw *hw = &adapter->hw;
2756         int err;
2757
2758         err = hw->mac.ops.init_hw(hw);
2759         switch (err) {
2760         case 0:
2761         case IXGBE_ERR_SFP_NOT_PRESENT:
2762                 break;
2763         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2764                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2765                 break;
2766         case IXGBE_ERR_EEPROM_VERSION:
2767                 /* We are running on a pre-production device, log a warning */
2768                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2769                          "adapter/LOM.  Please be aware there may be issues "
2770                          "associated with your hardware.  If you are "
2771                          "experiencing problems please contact your Intel or "
2772                          "hardware representative who provided you with this "
2773                          "hardware.\n");
2774                 break;
2775         default:
2776                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2777         }
2778
2779         /* reprogram the RAR[0] in case user changed it. */
2780         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2781 }
2782
2783 /**
2784  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2785  * @adapter: board private structure
2786  * @rx_ring: ring to free buffers from
2787  **/
2788 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2789                                 struct ixgbe_ring *rx_ring)
2790 {
2791         struct pci_dev *pdev = adapter->pdev;
2792         unsigned long size;
2793         unsigned int i;
2794
2795         /* Free all the Rx ring sk_buffs */
2796
2797         for (i = 0; i < rx_ring->count; i++) {
2798                 struct ixgbe_rx_buffer *rx_buffer_info;
2799
2800                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2801                 if (rx_buffer_info->dma) {
2802                         pci_unmap_single(pdev, rx_buffer_info->dma,
2803                                          rx_ring->rx_buf_len,
2804                                          PCI_DMA_FROMDEVICE);
2805                         rx_buffer_info->dma = 0;
2806                 }
2807                 if (rx_buffer_info->skb) {
2808                         struct sk_buff *skb = rx_buffer_info->skb;
2809                         rx_buffer_info->skb = NULL;
2810                         do {
2811                                 struct sk_buff *this = skb;
2812                                 skb = skb->prev;
2813                                 dev_kfree_skb(this);
2814                         } while (skb);
2815                 }
2816                 if (!rx_buffer_info->page)
2817                         continue;
2818                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2819                                PCI_DMA_FROMDEVICE);
2820                 rx_buffer_info->page_dma = 0;
2821                 put_page(rx_buffer_info->page);
2822                 rx_buffer_info->page = NULL;
2823                 rx_buffer_info->page_offset = 0;
2824         }
2825
2826         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2827         memset(rx_ring->rx_buffer_info, 0, size);
2828
2829         /* Zero out the descriptor ring */
2830         memset(rx_ring->desc, 0, rx_ring->size);
2831
2832         rx_ring->next_to_clean = 0;
2833         rx_ring->next_to_use = 0;
2834
2835         if (rx_ring->head)
2836                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2837         if (rx_ring->tail)
2838                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2839 }
2840
2841 /**
2842  * ixgbe_clean_tx_ring - Free Tx Buffers
2843  * @adapter: board private structure
2844  * @tx_ring: ring to be cleaned
2845  **/
2846 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2847                                 struct ixgbe_ring *tx_ring)
2848 {
2849         struct ixgbe_tx_buffer *tx_buffer_info;
2850         unsigned long size;
2851         unsigned int i;
2852
2853         /* Free all the Tx ring sk_buffs */
2854
2855         for (i = 0; i < tx_ring->count; i++) {
2856                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2857                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2858         }
2859
2860         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2861         memset(tx_ring->tx_buffer_info, 0, size);
2862
2863         /* Zero out the descriptor ring */
2864         memset(tx_ring->desc, 0, tx_ring->size);
2865
2866         tx_ring->next_to_use = 0;
2867         tx_ring->next_to_clean = 0;
2868
2869         if (tx_ring->head)
2870                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2871         if (tx_ring->tail)
2872                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2873 }
2874
2875 /**
2876  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2877  * @adapter: board private structure
2878  **/
2879 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2880 {
2881         int i;
2882
2883         for (i = 0; i < adapter->num_rx_queues; i++)
2884                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2885 }
2886
2887 /**
2888  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2889  * @adapter: board private structure
2890  **/
2891 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2892 {
2893         int i;
2894
2895         for (i = 0; i < adapter->num_tx_queues; i++)
2896                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2897 }
2898
2899 void ixgbe_down(struct ixgbe_adapter *adapter)
2900 {
2901         struct net_device *netdev = adapter->netdev;
2902         struct ixgbe_hw *hw = &adapter->hw;
2903         u32 rxctrl;
2904         u32 txdctl;
2905         int i, j;
2906
2907         /* signal that we are down to the interrupt handler */
2908         set_bit(__IXGBE_DOWN, &adapter->state);
2909
2910         /* disable receives */
2911         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2912         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2913
2914         netif_tx_disable(netdev);
2915
2916         IXGBE_WRITE_FLUSH(hw);
2917         msleep(10);
2918
2919         netif_tx_stop_all_queues(netdev);
2920
2921         ixgbe_irq_disable(adapter);
2922
2923         ixgbe_napi_disable_all(adapter);
2924
2925         del_timer_sync(&adapter->watchdog_timer);
2926         cancel_work_sync(&adapter->watchdog_task);
2927
2928         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2929             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2930                 cancel_work_sync(&adapter->fdir_reinit_task);
2931
2932         /* disable transmits in the hardware now that interrupts are off */
2933         for (i = 0; i < adapter->num_tx_queues; i++) {
2934                 j = adapter->tx_ring[i].reg_idx;
2935                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2936                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2937                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2938         }
2939         /* Disable the Tx DMA engine on 82599 */
2940         if (hw->mac.type == ixgbe_mac_82599EB)
2941                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2942                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2943                                  ~IXGBE_DMATXCTL_TE));
2944
2945         netif_carrier_off(netdev);
2946
2947         if (!pci_channel_offline(adapter->pdev))
2948                 ixgbe_reset(adapter);
2949         ixgbe_clean_all_tx_rings(adapter);
2950         ixgbe_clean_all_rx_rings(adapter);
2951
2952 #ifdef CONFIG_IXGBE_DCA
2953         /* since we reset the hardware DCA settings were cleared */
2954         ixgbe_setup_dca(adapter);
2955 #endif
2956 }
2957
2958 /**
2959  * ixgbe_poll - NAPI Rx polling callback
2960  * @napi: structure for representing this polling device
2961  * @budget: how many packets driver is allowed to clean
2962  *
2963  * This function is used for legacy and MSI, NAPI mode
2964  **/
2965 static int ixgbe_poll(struct napi_struct *napi, int budget)
2966 {
2967         struct ixgbe_q_vector *q_vector =
2968                                 container_of(napi, struct ixgbe_q_vector, napi);
2969         struct ixgbe_adapter *adapter = q_vector->adapter;
2970         int tx_clean_complete, work_done = 0;
2971
2972 #ifdef CONFIG_IXGBE_DCA
2973         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2974                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2975                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2976         }
2977 #endif
2978
2979         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2980         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2981
2982         if (!tx_clean_complete)
2983                 work_done = budget;
2984
2985         /* If budget not fully consumed, exit the polling mode */
2986         if (work_done < budget) {
2987                 napi_complete(napi);
2988                 if (adapter->itr_setting & 1)
2989                         ixgbe_set_itr(adapter);
2990                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2991                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2992         }
2993         return work_done;
2994 }
2995
2996 /**
2997  * ixgbe_tx_timeout - Respond to a Tx Hang
2998  * @netdev: network interface device structure
2999  **/
3000 static void ixgbe_tx_timeout(struct net_device *netdev)
3001 {
3002         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3003
3004         /* Do the reset outside of interrupt context */
3005         schedule_work(&adapter->reset_task);
3006 }
3007
3008 static void ixgbe_reset_task(struct work_struct *work)
3009 {
3010         struct ixgbe_adapter *adapter;
3011         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3012
3013         /* If we're already down or resetting, just bail */
3014         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3015             test_bit(__IXGBE_RESETTING, &adapter->state))
3016                 return;
3017
3018         adapter->tx_timeout_count++;
3019
3020         ixgbe_reinit_locked(adapter);
3021 }
3022
3023 #ifdef CONFIG_IXGBE_DCB
3024 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3025 {
3026         bool ret = false;
3027         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3028
3029         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3030                 return ret;
3031
3032         f->mask = 0x7 << 3;
3033         adapter->num_rx_queues = f->indices;
3034         adapter->num_tx_queues = f->indices;
3035         ret = true;
3036
3037         return ret;
3038 }
3039 #endif
3040
3041 /**
3042  * ixgbe_set_rss_queues: Allocate queues for RSS
3043  * @adapter: board private structure to initialize
3044  *
3045  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3046  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3047  *
3048  **/
3049 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3050 {
3051         bool ret = false;
3052         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3053
3054         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3055                 f->mask = 0xF;
3056                 adapter->num_rx_queues = f->indices;
3057                 adapter->num_tx_queues = f->indices;
3058                 ret = true;
3059         } else {
3060                 ret = false;
3061         }
3062
3063         return ret;
3064 }
3065
3066 /**
3067  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3068  * @adapter: board private structure to initialize
3069  *
3070  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3071  * to the original CPU that initiated the Tx session.  This runs in addition
3072  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3073  * Rx load across CPUs using RSS.
3074  *
3075  **/
3076 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3077 {
3078         bool ret = false;
3079         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3080
3081         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3082         f_fdir->mask = 0;
3083
3084         /* Flow Director must have RSS enabled */
3085         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3086             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3087              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3088                 adapter->num_tx_queues = f_fdir->indices;
3089                 adapter->num_rx_queues = f_fdir->indices;
3090                 ret = true;
3091         } else {
3092                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3093                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3094         }
3095         return ret;
3096 }
3097
3098 #ifdef IXGBE_FCOE
3099 /**
3100  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3101  * @adapter: board private structure to initialize
3102  *
3103  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3104  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3105  * rx queues out of the max number of rx queues, instead, it is used as the
3106  * index of the first rx queue used by FCoE.
3107  *
3108  **/
3109 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3110 {
3111         bool ret = false;
3112         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3113
3114         f->indices = min((int)num_online_cpus(), f->indices);
3115         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3116 #ifdef CONFIG_IXGBE_DCB
3117                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3118                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3119                         ixgbe_set_dcb_queues(adapter);
3120                 }
3121 #endif
3122                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3123                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3124                         ixgbe_set_rss_queues(adapter);
3125                 }
3126                 /* adding FCoE rx rings to the end */
3127                 f->mask = adapter->num_rx_queues;
3128                 adapter->num_rx_queues += f->indices;
3129                 if (adapter->num_tx_queues == 0)
3130                         adapter->num_tx_queues = f->indices;
3131
3132                 ret = true;
3133         }
3134
3135         return ret;
3136 }
3137
3138 #endif /* IXGBE_FCOE */
3139 /*
3140  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3141  * @adapter: board private structure to initialize
3142  *
3143  * This is the top level queue allocation routine.  The order here is very
3144  * important, starting with the "most" number of features turned on at once,
3145  * and ending with the smallest set of features.  This way large combinations
3146  * can be allocated if they're turned on, and smaller combinations are the
3147  * fallthrough conditions.
3148  *
3149  **/
3150 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3151 {
3152 #ifdef IXGBE_FCOE
3153         if (ixgbe_set_fcoe_queues(adapter))
3154                 goto done;
3155
3156 #endif /* IXGBE_FCOE */
3157 #ifdef CONFIG_IXGBE_DCB
3158         if (ixgbe_set_dcb_queues(adapter))
3159                 goto done;
3160
3161 #endif
3162         if (ixgbe_set_fdir_queues(adapter))
3163                 goto done;
3164
3165         if (ixgbe_set_rss_queues(adapter))
3166                 goto done;
3167
3168         /* fallback to base case */
3169         adapter->num_rx_queues = 1;
3170         adapter->num_tx_queues = 1;
3171
3172 done:
3173         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3174         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3175 }
3176
3177 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3178                                        int vectors)
3179 {
3180         int err, vector_threshold;
3181
3182         /* We'll want at least 3 (vector_threshold):
3183          * 1) TxQ[0] Cleanup
3184          * 2) RxQ[0] Cleanup
3185          * 3) Other (Link Status Change, etc.)
3186          * 4) TCP Timer (optional)
3187          */
3188         vector_threshold = MIN_MSIX_COUNT;
3189
3190         /* The more we get, the more we will assign to Tx/Rx Cleanup
3191          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3192          * Right now, we simply care about how many we'll get; we'll
3193          * set them up later while requesting irq's.
3194          */
3195         while (vectors >= vector_threshold) {
3196                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3197                                       vectors);
3198                 if (!err) /* Success in acquiring all requested vectors. */
3199                         break;
3200                 else if (err < 0)
3201                         vectors = 0; /* Nasty failure, quit now */
3202                 else /* err == number of vectors we should try again with */
3203                         vectors = err;
3204         }
3205
3206         if (vectors < vector_threshold) {
3207                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3208                  * This just means we'll go with either a single MSI
3209                  * vector or fall back to legacy interrupts.
3210                  */
3211                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3212                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3213                 kfree(adapter->msix_entries);
3214                 adapter->msix_entries = NULL;
3215         } else {
3216                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3217                 /*
3218                  * Adjust for only the vectors we'll use, which is minimum
3219                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3220                  * vectors we were allocated.
3221                  */
3222                 adapter->num_msix_vectors = min(vectors,
3223                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3224         }
3225 }
3226
3227 /**
3228  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3229  * @adapter: board private structure to initialize
3230  *
3231  * Cache the descriptor ring offsets for RSS to the assigned rings.
3232  *
3233  **/
3234 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3235 {
3236         int i;
3237         bool ret = false;
3238
3239         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3240                 for (i = 0; i < adapter->num_rx_queues; i++)
3241                         adapter->rx_ring[i].reg_idx = i;
3242                 for (i = 0; i < adapter->num_tx_queues; i++)
3243                         adapter->tx_ring[i].reg_idx = i;
3244                 ret = true;
3245         } else {
3246                 ret = false;
3247         }
3248
3249         return ret;
3250 }
3251
3252 #ifdef CONFIG_IXGBE_DCB
3253 /**
3254  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3255  * @adapter: board private structure to initialize
3256  *
3257  * Cache the descriptor ring offsets for DCB to the assigned rings.
3258  *
3259  **/
3260 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3261 {
3262         int i;
3263         bool ret = false;
3264         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3265
3266         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3267                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3268                         /* the number of queues is assumed to be symmetric */
3269                         for (i = 0; i < dcb_i; i++) {
3270                                 adapter->rx_ring[i].reg_idx = i << 3;
3271                                 adapter->tx_ring[i].reg_idx = i << 2;
3272                         }
3273                         ret = true;
3274                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3275                         if (dcb_i == 8) {
3276                                 /*
3277                                  * Tx TC0 starts at: descriptor queue 0
3278                                  * Tx TC1 starts at: descriptor queue 32
3279                                  * Tx TC2 starts at: descriptor queue 64
3280                                  * Tx TC3 starts at: descriptor queue 80
3281                                  * Tx TC4 starts at: descriptor queue 96
3282                                  * Tx TC5 starts at: descriptor queue 104
3283                                  * Tx TC6 starts at: descriptor queue 112
3284                                  * Tx TC7 starts at: descriptor queue 120
3285                                  *
3286                                  * Rx TC0-TC7 are offset by 16 queues each
3287                                  */
3288                                 for (i = 0; i < 3; i++) {
3289                                         adapter->tx_ring[i].reg_idx = i << 5;
3290                                         adapter->rx_ring[i].reg_idx = i << 4;
3291                                 }
3292                                 for ( ; i < 5; i++) {
3293                                         adapter->tx_ring[i].reg_idx =
3294                                                                  ((i + 2) << 4);
3295                                         adapter->rx_ring[i].reg_idx = i << 4;
3296                                 }
3297                                 for ( ; i < dcb_i; i++) {
3298                                         adapter->tx_ring[i].reg_idx =
3299                                                                  ((i + 8) << 3);
3300                                         adapter->rx_ring[i].reg_idx = i << 4;
3301                                 }
3302
3303                                 ret = true;
3304                         } else if (dcb_i == 4) {
3305                                 /*
3306                                  * Tx TC0 starts at: descriptor queue 0
3307                                  * Tx TC1 starts at: descriptor queue 64
3308                                  * Tx TC2 starts at: descriptor queue 96
3309                                  * Tx TC3 starts at: descriptor queue 112
3310                                  *
3311                                  * Rx TC0-TC3 are offset by 32 queues each
3312                                  */
3313                                 adapter->tx_ring[0].reg_idx = 0;
3314                                 adapter->tx_ring[1].reg_idx = 64;
3315                                 adapter->tx_ring[2].reg_idx = 96;
3316                                 adapter->tx_ring[3].reg_idx = 112;
3317                                 for (i = 0 ; i < dcb_i; i++)
3318                                         adapter->rx_ring[i].reg_idx = i << 5;
3319
3320                                 ret = true;
3321                         } else {
3322                                 ret = false;
3323                         }
3324                 } else {
3325                         ret = false;
3326                 }
3327         } else {
3328                 ret = false;
3329         }
3330
3331         return ret;
3332 }
3333 #endif
3334
3335 /**
3336  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3337  * @adapter: board private structure to initialize
3338  *
3339  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3340  *
3341  **/
3342 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3343 {
3344         int i;
3345         bool ret = false;
3346
3347         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3348             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3349              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3350                 for (i = 0; i < adapter->num_rx_queues; i++)
3351                         adapter->rx_ring[i].reg_idx = i;
3352                 for (i = 0; i < adapter->num_tx_queues; i++)
3353                         adapter->tx_ring[i].reg_idx = i;
3354                 ret = true;
3355         }
3356
3357         return ret;
3358 }
3359
3360 #ifdef IXGBE_FCOE
3361 /**
3362  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3363  * @adapter: board private structure to initialize
3364  *
3365  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3366  *
3367  */
3368 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3369 {
3370         int i, fcoe_i = 0;
3371         bool ret = false;
3372         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3373
3374         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3375 #ifdef CONFIG_IXGBE_DCB
3376                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3377                         ixgbe_cache_ring_dcb(adapter);
3378                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3379                 }
3380 #endif /* CONFIG_IXGBE_DCB */
3381                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3382                         ixgbe_cache_ring_rss(adapter);
3383                         fcoe_i = f->mask;
3384                 }
3385                 for (i = 0; i < f->indices; i++, fcoe_i++)
3386                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3387                 ret = true;
3388         }
3389         return ret;
3390 }
3391
3392 #endif /* IXGBE_FCOE */
3393 /**
3394  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3395  * @adapter: board private structure to initialize
3396  *
3397  * Once we know the feature-set enabled for the device, we'll cache
3398  * the register offset the descriptor ring is assigned to.
3399  *
3400  * Note, the order the various feature calls is important.  It must start with
3401  * the "most" features enabled at the same time, then trickle down to the
3402  * least amount of features turned on at once.
3403  **/
3404 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3405 {
3406         /* start with default case */
3407         adapter->rx_ring[0].reg_idx = 0;
3408         adapter->tx_ring[0].reg_idx = 0;
3409
3410 #ifdef IXGBE_FCOE
3411         if (ixgbe_cache_ring_fcoe(adapter))
3412                 return;
3413
3414 #endif /* IXGBE_FCOE */
3415 #ifdef CONFIG_IXGBE_DCB
3416         if (ixgbe_cache_ring_dcb(adapter))
3417                 return;
3418
3419 #endif
3420         if (ixgbe_cache_ring_fdir(adapter))
3421                 return;
3422
3423         if (ixgbe_cache_ring_rss(adapter))
3424                 return;
3425 }
3426
3427 /**
3428  * ixgbe_alloc_queues - Allocate memory for all rings
3429  * @adapter: board private structure to initialize
3430  *
3431  * We allocate one ring per queue at run-time since we don't know the
3432  * number of queues at compile-time.  The polling_netdev array is
3433  * intended for Multiqueue, but should work fine with a single queue.
3434  **/
3435 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3436 {
3437         int i;
3438
3439         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3440                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3441         if (!adapter->tx_ring)
3442                 goto err_tx_ring_allocation;
3443
3444         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3445                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3446         if (!adapter->rx_ring)
3447                 goto err_rx_ring_allocation;
3448
3449         for (i = 0; i < adapter->num_tx_queues; i++) {
3450                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3451                 adapter->tx_ring[i].queue_index = i;
3452         }
3453
3454         for (i = 0; i < adapter->num_rx_queues; i++) {
3455                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3456                 adapter->rx_ring[i].queue_index = i;
3457         }
3458
3459         ixgbe_cache_ring_register(adapter);
3460
3461         return 0;
3462
3463 err_rx_ring_allocation:
3464         kfree(adapter->tx_ring);
3465 err_tx_ring_allocation:
3466         return -ENOMEM;
3467 }
3468
3469 /**
3470  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3471  * @adapter: board private structure to initialize
3472  *
3473  * Attempt to configure the interrupts using the best available
3474  * capabilities of the hardware and the kernel.
3475  **/
3476 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3477 {
3478         struct ixgbe_hw *hw = &adapter->hw;
3479         int err = 0;
3480         int vector, v_budget;
3481
3482         /*
3483          * It's easy to be greedy for MSI-X vectors, but it really
3484          * doesn't do us much good if we have a lot more vectors
3485          * than CPU's.  So let's be conservative and only ask for
3486          * (roughly) twice the number of vectors as there are CPU's.
3487          */
3488         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3489                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3490
3491         /*
3492          * At the same time, hardware can only support a maximum of
3493          * hw.mac->max_msix_vectors vectors.  With features
3494          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3495          * descriptor queues supported by our device.  Thus, we cap it off in
3496          * those rare cases where the cpu count also exceeds our vector limit.
3497          */
3498         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3499
3500         /* A failure in MSI-X entry allocation isn't fatal, but it does
3501          * mean we disable MSI-X capabilities of the adapter. */
3502         adapter->msix_entries = kcalloc(v_budget,
3503                                         sizeof(struct msix_entry), GFP_KERNEL);
3504         if (adapter->msix_entries) {
3505                 for (vector = 0; vector < v_budget; vector++)
3506                         adapter->msix_entries[vector].entry = vector;
3507
3508                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3509
3510                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3511                         goto out;
3512         }
3513
3514         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3515         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3516         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3517         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3518         adapter->atr_sample_rate = 0;
3519         ixgbe_set_num_queues(adapter);
3520
3521         err = pci_enable_msi(adapter->pdev);
3522         if (!err) {
3523                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3524         } else {
3525                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3526                         "falling back to legacy.  Error: %d\n", err);
3527                 /* reset err */
3528                 err = 0;
3529         }
3530
3531 out:
3532         return err;
3533 }
3534
3535 /**
3536  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3537  * @adapter: board private structure to initialize
3538  *
3539  * We allocate one q_vector per queue interrupt.  If allocation fails we
3540  * return -ENOMEM.
3541  **/
3542 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3543 {
3544         int q_idx, num_q_vectors;
3545         struct ixgbe_q_vector *q_vector;
3546         int napi_vectors;
3547         int (*poll)(struct napi_struct *, int);
3548
3549         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3550                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3551                 napi_vectors = adapter->num_rx_queues;
3552                 poll = &ixgbe_clean_rxtx_many;
3553         } else {
3554                 num_q_vectors = 1;
3555                 napi_vectors = 1;
3556                 poll = &ixgbe_poll;
3557         }
3558
3559         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3560                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3561                 if (!q_vector)
3562                         goto err_out;
3563                 q_vector->adapter = adapter;
3564                 q_vector->eitr = adapter->eitr_param;
3565                 q_vector->v_idx = q_idx;
3566                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3567                 adapter->q_vector[q_idx] = q_vector;
3568         }
3569
3570         return 0;
3571
3572 err_out:
3573         while (q_idx) {
3574                 q_idx--;
3575                 q_vector = adapter->q_vector[q_idx];
3576                 netif_napi_del(&q_vector->napi);
3577                 kfree(q_vector);
3578                 adapter->q_vector[q_idx] = NULL;
3579         }
3580         return -ENOMEM;
3581 }
3582
3583 /**
3584  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3585  * @adapter: board private structure to initialize
3586  *
3587  * This function frees the memory allocated to the q_vectors.  In addition if
3588  * NAPI is enabled it will delete any references to the NAPI struct prior
3589  * to freeing the q_vector.
3590  **/
3591 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3592 {
3593         int q_idx, num_q_vectors;
3594
3595         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3596                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3597         else
3598                 num_q_vectors = 1;
3599
3600         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3601                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3602                 adapter->q_vector[q_idx] = NULL;
3603                 netif_napi_del(&q_vector->napi);
3604                 kfree(q_vector);
3605         }
3606 }
3607
3608 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3609 {
3610         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3611                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3612                 pci_disable_msix(adapter->pdev);
3613                 kfree(adapter->msix_entries);
3614                 adapter->msix_entries = NULL;
3615         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3616                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3617                 pci_disable_msi(adapter->pdev);
3618         }
3619         return;
3620 }
3621
3622 /**
3623  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3624  * @adapter: board private structure to initialize
3625  *
3626  * We determine which interrupt scheme to use based on...
3627  * - Kernel support (MSI, MSI-X)
3628  *   - which can be user-defined (via MODULE_PARAM)
3629  * - Hardware queue count (num_*_queues)
3630  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3631  **/
3632 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3633 {
3634         int err;
3635
3636         /* Number of supported queues */
3637         ixgbe_set_num_queues(adapter);
3638
3639         err = ixgbe_set_interrupt_capability(adapter);
3640         if (err) {
3641                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3642                 goto err_set_interrupt;
3643         }
3644
3645         err = ixgbe_alloc_q_vectors(adapter);
3646         if (err) {
3647                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3648                         "vectors\n");
3649                 goto err_alloc_q_vectors;
3650         }
3651
3652         err = ixgbe_alloc_queues(adapter);
3653         if (err) {
3654                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3655                 goto err_alloc_queues;
3656         }
3657
3658         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3659                 "Tx Queue count = %u\n",
3660                 (adapter->num_rx_queues > 1) ? "Enabled" :
3661                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3662
3663         set_bit(__IXGBE_DOWN, &adapter->state);
3664
3665         return 0;
3666
3667 err_alloc_queues:
3668         ixgbe_free_q_vectors(adapter);
3669 err_alloc_q_vectors:
3670         ixgbe_reset_interrupt_capability(adapter);
3671 err_set_interrupt:
3672         return err;
3673 }
3674
3675 /**
3676  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3677  * @adapter: board private structure to clear interrupt scheme on
3678  *
3679  * We go through and clear interrupt specific resources and reset the structure
3680  * to pre-load conditions
3681  **/
3682 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3683 {
3684         kfree(adapter->tx_ring);
3685         kfree(adapter->rx_ring);
3686         adapter->tx_ring = NULL;
3687         adapter->rx_ring = NULL;
3688
3689         ixgbe_free_q_vectors(adapter);
3690         ixgbe_reset_interrupt_capability(adapter);
3691 }
3692
3693 /**
3694  * ixgbe_sfp_timer - worker thread to find a missing module
3695  * @data: pointer to our adapter struct
3696  **/
3697 static void ixgbe_sfp_timer(unsigned long data)
3698 {
3699         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3700
3701         /*
3702          * Do the sfp_timer outside of interrupt context due to the
3703          * delays that sfp+ detection requires
3704          */
3705         schedule_work(&adapter->sfp_task);
3706 }
3707
3708 /**
3709  * ixgbe_sfp_task - worker thread to find a missing module
3710  * @work: pointer to work_struct containing our data
3711  **/
3712 static void ixgbe_sfp_task(struct work_struct *work)
3713 {
3714         struct ixgbe_adapter *adapter = container_of(work,
3715                                                      struct ixgbe_adapter,
3716                                                      sfp_task);
3717         struct ixgbe_hw *hw = &adapter->hw;
3718
3719         if ((hw->phy.type == ixgbe_phy_nl) &&
3720             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3721                 s32 ret = hw->phy.ops.identify_sfp(hw);
3722                 if (ret)
3723                         goto reschedule;
3724                 ret = hw->phy.ops.reset(hw);
3725                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3726                         dev_err(&adapter->pdev->dev, "failed to initialize "
3727                                 "because an unsupported SFP+ module type "
3728                                 "was detected.\n"
3729                                 "Reload the driver after installing a "
3730                                 "supported module.\n");
3731                         unregister_netdev(adapter->netdev);
3732                 } else {
3733                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3734                                 hw->phy.sfp_type);
3735                 }
3736                 /* don't need this routine any more */
3737                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3738         }
3739         return;
3740 reschedule:
3741         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3742                 mod_timer(&adapter->sfp_timer,
3743                           round_jiffies(jiffies + (2 * HZ)));
3744 }
3745
3746 /**
3747  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3748  * @adapter: board private structure to initialize
3749  *
3750  * ixgbe_sw_init initializes the Adapter private data structure.
3751  * Fields are initialized based on PCI device information and
3752  * OS network device settings (MTU size).
3753  **/
3754 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3755 {
3756         struct ixgbe_hw *hw = &adapter->hw;
3757         struct pci_dev *pdev = adapter->pdev;
3758         unsigned int rss;
3759 #ifdef CONFIG_IXGBE_DCB
3760         int j;
3761         struct tc_configuration *tc;
3762 #endif
3763
3764         /* PCI config space info */
3765
3766         hw->vendor_id = pdev->vendor;
3767         hw->device_id = pdev->device;
3768         hw->revision_id = pdev->revision;
3769         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3770         hw->subsystem_device_id = pdev->subsystem_device;
3771
3772         /* Set capability flags */
3773         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3774         adapter->ring_feature[RING_F_RSS].indices = rss;
3775         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3776         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3777         if (hw->mac.type == ixgbe_mac_82598EB) {
3778                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3779                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3780                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3781         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3782                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3783                 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3784                 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
3785                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3786                 adapter->ring_feature[RING_F_FDIR].indices =
3787                                                          IXGBE_MAX_FDIR_INDICES;
3788                 adapter->atr_sample_rate = 20;
3789                 adapter->fdir_pballoc = 0;
3790 #ifdef IXGBE_FCOE
3791                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3792                 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3793 #endif /* IXGBE_FCOE */
3794         }
3795
3796 #ifdef CONFIG_IXGBE_DCB
3797         /* Configure DCB traffic classes */
3798         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3799                 tc = &adapter->dcb_cfg.tc_config[j];
3800                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3801                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3802                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3803                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3804                 tc->dcb_pfc = pfc_disabled;
3805         }
3806         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3807         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3808         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3809         adapter->dcb_cfg.pfc_mode_enable = false;
3810         adapter->dcb_cfg.round_robin_enable = false;
3811         adapter->dcb_set_bitmap = 0x00;
3812         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3813                            adapter->ring_feature[RING_F_DCB].indices);
3814
3815 #endif
3816
3817         /* default flow control settings */
3818         hw->fc.requested_mode = ixgbe_fc_full;
3819         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3820 #ifdef CONFIG_DCB
3821         adapter->last_lfc_mode = hw->fc.current_mode;
3822 #endif
3823         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3824         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3825         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3826         hw->fc.send_xon = true;
3827         hw->fc.disable_fc_autoneg = false;
3828
3829         /* enable itr by default in dynamic mode */
3830         adapter->itr_setting = 1;
3831         adapter->eitr_param = 20000;
3832
3833         /* set defaults for eitr in MegaBytes */
3834         adapter->eitr_low = 10;
3835         adapter->eitr_high = 20;
3836
3837         /* set default ring sizes */
3838         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3839         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3840
3841         /* initialize eeprom parameters */
3842         if (ixgbe_init_eeprom_params_generic(hw)) {
3843                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3844                 return -EIO;
3845         }
3846
3847         /* enable rx csum by default */
3848         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3849
3850         set_bit(__IXGBE_DOWN, &adapter->state);
3851
3852         return 0;
3853 }
3854
3855 /**
3856  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3857  * @adapter: board private structure
3858  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3859  *
3860  * Return 0 on success, negative on failure
3861  **/
3862 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3863                              struct ixgbe_ring *tx_ring)
3864 {
3865         struct pci_dev *pdev = adapter->pdev;
3866         int size;
3867
3868         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3869         tx_ring->tx_buffer_info = vmalloc(size);
3870         if (!tx_ring->tx_buffer_info)
3871                 goto err;
3872         memset(tx_ring->tx_buffer_info, 0, size);
3873
3874         /* round up to nearest 4K */
3875         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3876         tx_ring->size = ALIGN(tx_ring->size, 4096);
3877
3878         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3879                                              &tx_ring->dma);
3880         if (!tx_ring->desc)
3881                 goto err;
3882
3883         tx_ring->next_to_use = 0;
3884         tx_ring->next_to_clean = 0;
3885         tx_ring->work_limit = tx_ring->count;
3886         return 0;
3887
3888 err:
3889         vfree(tx_ring->tx_buffer_info);
3890         tx_ring->tx_buffer_info = NULL;
3891         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3892                             "descriptor ring\n");
3893         return -ENOMEM;
3894 }
3895
3896 /**
3897  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3898  * @adapter: board private structure
3899  *
3900  * If this function returns with an error, then it's possible one or
3901  * more of the rings is populated (while the rest are not).  It is the
3902  * callers duty to clean those orphaned rings.
3903  *
3904  * Return 0 on success, negative on failure
3905  **/
3906 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3907 {
3908         int i, err = 0;
3909
3910         for (i = 0; i < adapter->num_tx_queues; i++) {
3911                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3912                 if (!err)
3913                         continue;
3914                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3915                 break;
3916         }
3917
3918         return err;
3919 }
3920
3921 /**
3922  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3923  * @adapter: board private structure
3924  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3925  *
3926  * Returns 0 on success, negative on failure
3927  **/
3928 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3929                              struct ixgbe_ring *rx_ring)
3930 {
3931         struct pci_dev *pdev = adapter->pdev;
3932         int size;
3933
3934         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3935         rx_ring->rx_buffer_info = vmalloc(size);
3936         if (!rx_ring->rx_buffer_info) {
3937                 DPRINTK(PROBE, ERR,
3938                         "vmalloc allocation failed for the rx desc ring\n");
3939                 goto alloc_failed;
3940         }
3941         memset(rx_ring->rx_buffer_info, 0, size);
3942
3943         /* Round up to nearest 4K */
3944         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3945         rx_ring->size = ALIGN(rx_ring->size, 4096);
3946
3947         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3948
3949         if (!rx_ring->desc) {
3950                 DPRINTK(PROBE, ERR,
3951                         "Memory allocation failed for the rx desc ring\n");
3952                 vfree(rx_ring->rx_buffer_info);
3953                 goto alloc_failed;
3954         }
3955
3956         rx_ring->next_to_clean = 0;
3957         rx_ring->next_to_use = 0;
3958
3959         return 0;
3960
3961 alloc_failed:
3962         return -ENOMEM;
3963 }
3964
3965 /**
3966  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3967  * @adapter: board private structure
3968  *
3969  * If this function returns with an error, then it's possible one or
3970  * more of the rings is populated (while the rest are not).  It is the
3971  * callers duty to clean those orphaned rings.
3972  *
3973  * Return 0 on success, negative on failure
3974  **/
3975
3976 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3977 {
3978         int i, err = 0;
3979
3980         for (i = 0; i < adapter->num_rx_queues; i++) {
3981                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3982                 if (!err)
3983                         continue;
3984                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3985                 break;
3986         }
3987
3988         return err;
3989 }
3990
3991 /**
3992  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3993  * @adapter: board private structure
3994  * @tx_ring: Tx descriptor ring for a specific queue
3995  *
3996  * Free all transmit software resources
3997  **/
3998 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3999                              struct ixgbe_ring *tx_ring)
4000 {
4001         struct pci_dev *pdev = adapter->pdev;
4002
4003         ixgbe_clean_tx_ring(adapter, tx_ring);
4004
4005         vfree(tx_ring->tx_buffer_info);
4006         tx_ring->tx_buffer_info = NULL;
4007
4008         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4009
4010         tx_ring->desc = NULL;
4011 }
4012
4013 /**
4014  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4015  * @adapter: board private structure
4016  *
4017  * Free all transmit software resources
4018  **/
4019 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4020 {
4021         int i;
4022
4023         for (i = 0; i < adapter->num_tx_queues; i++)
4024                 if (adapter->tx_ring[i].desc)
4025                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4026 }
4027
4028 /**
4029  * ixgbe_free_rx_resources - Free Rx Resources
4030  * @adapter: board private structure
4031  * @rx_ring: ring to clean the resources from
4032  *
4033  * Free all receive software resources
4034  **/
4035 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4036                              struct ixgbe_ring *rx_ring)
4037 {
4038         struct pci_dev *pdev = adapter->pdev;
4039
4040         ixgbe_clean_rx_ring(adapter, rx_ring);
4041
4042         vfree(rx_ring->rx_buffer_info);
4043         rx_ring->rx_buffer_info = NULL;
4044
4045         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4046
4047         rx_ring->desc = NULL;
4048 }
4049
4050 /**
4051  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4052  * @adapter: board private structure
4053  *
4054  * Free all receive software resources
4055  **/
4056 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4057 {
4058         int i;
4059
4060         for (i = 0; i < adapter->num_rx_queues; i++)
4061                 if (adapter->rx_ring[i].desc)
4062                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4063 }
4064
4065 /**
4066  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4067  * @netdev: network interface device structure
4068  * @new_mtu: new value for maximum frame size
4069  *
4070  * Returns 0 on success, negative on failure
4071  **/
4072 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4073 {
4074         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4075         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4076
4077         /* MTU < 68 is an error and causes problems on some kernels */
4078         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4079                 return -EINVAL;
4080
4081         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4082                 netdev->mtu, new_mtu);
4083         /* must set new MTU before calling down or up */
4084         netdev->mtu = new_mtu;
4085
4086         if (netif_running(netdev))
4087                 ixgbe_reinit_locked(adapter);
4088
4089         return 0;
4090 }
4091
4092 /**
4093  * ixgbe_open - Called when a network interface is made active
4094  * @netdev: network interface device structure
4095  *
4096  * Returns 0 on success, negative value on failure
4097  *
4098  * The open entry point is called when a network interface is made
4099  * active by the system (IFF_UP).  At this point all resources needed
4100  * for transmit and receive operations are allocated, the interrupt
4101  * handler is registered with the OS, the watchdog timer is started,
4102  * and the stack is notified that the interface is ready.
4103  **/
4104 static int ixgbe_open(struct net_device *netdev)
4105 {
4106         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4107         int err;
4108
4109         /* disallow open during test */
4110         if (test_bit(__IXGBE_TESTING, &adapter->state))
4111                 return -EBUSY;
4112
4113         netif_carrier_off(netdev);
4114
4115         /* allocate transmit descriptors */
4116         err = ixgbe_setup_all_tx_resources(adapter);
4117         if (err)
4118                 goto err_setup_tx;
4119
4120         /* allocate receive descriptors */
4121         err = ixgbe_setup_all_rx_resources(adapter);
4122         if (err)
4123                 goto err_setup_rx;
4124
4125         ixgbe_configure(adapter);
4126
4127         err = ixgbe_request_irq(adapter);
4128         if (err)
4129                 goto err_req_irq;
4130
4131         err = ixgbe_up_complete(adapter);
4132         if (err)
4133                 goto err_up;
4134
4135         netif_tx_start_all_queues(netdev);
4136
4137         return 0;
4138
4139 err_up:
4140         ixgbe_release_hw_control(adapter);
4141         ixgbe_free_irq(adapter);
4142 err_req_irq:
4143 err_setup_rx:
4144         ixgbe_free_all_rx_resources(adapter);
4145 err_setup_tx:
4146         ixgbe_free_all_tx_resources(adapter);
4147         ixgbe_reset(adapter);
4148
4149         return err;
4150 }
4151
4152 /**
4153  * ixgbe_close - Disables a network interface
4154  * @netdev: network interface device structure
4155  *
4156  * Returns 0, this is not allowed to fail
4157  *
4158  * The close entry point is called when an interface is de-activated
4159  * by the OS.  The hardware is still under the drivers control, but
4160  * needs to be disabled.  A global MAC reset is issued to stop the
4161  * hardware, and all transmit and receive resources are freed.
4162  **/
4163 static int ixgbe_close(struct net_device *netdev)
4164 {
4165         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4166
4167         ixgbe_down(adapter);
4168         ixgbe_free_irq(adapter);
4169
4170         ixgbe_free_all_tx_resources(adapter);
4171         ixgbe_free_all_rx_resources(adapter);
4172
4173         ixgbe_release_hw_control(adapter);
4174
4175         return 0;
4176 }
4177
4178 #ifdef CONFIG_PM
4179 static int ixgbe_resume(struct pci_dev *pdev)
4180 {
4181         struct net_device *netdev = pci_get_drvdata(pdev);
4182         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4183         u32 err;
4184
4185         pci_set_power_state(pdev, PCI_D0);
4186         pci_restore_state(pdev);
4187
4188         err = pci_enable_device_mem(pdev);
4189         if (err) {
4190                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4191                                 "suspend\n");
4192                 return err;
4193         }
4194         pci_set_master(pdev);
4195
4196         pci_wake_from_d3(pdev, false);
4197
4198         err = ixgbe_init_interrupt_scheme(adapter);
4199         if (err) {
4200                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4201                                 "device\n");
4202                 return err;
4203         }
4204
4205         ixgbe_reset(adapter);
4206
4207         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4208
4209         if (netif_running(netdev)) {
4210                 err = ixgbe_open(adapter->netdev);
4211                 if (err)
4212                         return err;
4213         }
4214
4215         netif_device_attach(netdev);
4216
4217         return 0;
4218 }
4219 #endif /* CONFIG_PM */
4220
4221 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4222 {
4223         struct net_device *netdev = pci_get_drvdata(pdev);
4224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4225         struct ixgbe_hw *hw = &adapter->hw;
4226         u32 ctrl, fctrl;
4227         u32 wufc = adapter->wol;
4228 #ifdef CONFIG_PM
4229         int retval = 0;
4230 #endif
4231
4232         netif_device_detach(netdev);
4233
4234         if (netif_running(netdev)) {
4235                 ixgbe_down(adapter);
4236                 ixgbe_free_irq(adapter);
4237                 ixgbe_free_all_tx_resources(adapter);
4238                 ixgbe_free_all_rx_resources(adapter);
4239         }
4240         ixgbe_clear_interrupt_scheme(adapter);
4241
4242 #ifdef CONFIG_PM
4243         retval = pci_save_state(pdev);
4244         if (retval)
4245                 return retval;
4246
4247 #endif
4248         if (wufc) {
4249                 ixgbe_set_rx_mode(netdev);
4250
4251                 /* turn on all-multi mode if wake on multicast is enabled */
4252                 if (wufc & IXGBE_WUFC_MC) {
4253                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4254                         fctrl |= IXGBE_FCTRL_MPE;
4255                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4256                 }
4257
4258                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4259                 ctrl |= IXGBE_CTRL_GIO_DIS;
4260                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4261
4262                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4263         } else {
4264                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4265                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4266         }
4267
4268         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4269                 pci_wake_from_d3(pdev, true);
4270         else
4271                 pci_wake_from_d3(pdev, false);
4272
4273         *enable_wake = !!wufc;
4274
4275         ixgbe_release_hw_control(adapter);
4276
4277         pci_disable_device(pdev);
4278
4279         return 0;
4280 }
4281
4282 #ifdef CONFIG_PM
4283 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4284 {
4285         int retval;
4286         bool wake;
4287
4288         retval = __ixgbe_shutdown(pdev, &wake);
4289         if (retval)
4290                 return retval;
4291
4292         if (wake) {
4293                 pci_prepare_to_sleep(pdev);
4294         } else {
4295                 pci_wake_from_d3(pdev, false);
4296                 pci_set_power_state(pdev, PCI_D3hot);
4297         }
4298
4299         return 0;
4300 }
4301 #endif /* CONFIG_PM */
4302
4303 static void ixgbe_shutdown(struct pci_dev *pdev)
4304 {
4305         bool wake;
4306
4307         __ixgbe_shutdown(pdev, &wake);
4308
4309         if (system_state == SYSTEM_POWER_OFF) {
4310                 pci_wake_from_d3(pdev, wake);
4311                 pci_set_power_state(pdev, PCI_D3hot);
4312         }
4313 }
4314
4315 /**
4316  * ixgbe_update_stats - Update the board statistics counters.
4317  * @adapter: board private structure
4318  **/
4319 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4320 {
4321         struct ixgbe_hw *hw = &adapter->hw;
4322         u64 total_mpc = 0;
4323         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4324
4325         if (hw->mac.type == ixgbe_mac_82599EB) {
4326                 u64 rsc_count = 0;
4327                 for (i = 0; i < 16; i++)
4328                         adapter->hw_rx_no_dma_resources +=
4329                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4330                 for (i = 0; i < adapter->num_rx_queues; i++)
4331                         rsc_count += adapter->rx_ring[i].rsc_count;
4332                 adapter->rsc_count = rsc_count;
4333         }
4334
4335         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4336         for (i = 0; i < 8; i++) {
4337                 /* for packet buffers not used, the register should read 0 */
4338                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4339                 missed_rx += mpc;
4340                 adapter->stats.mpc[i] += mpc;
4341                 total_mpc += adapter->stats.mpc[i];
4342                 if (hw->mac.type == ixgbe_mac_82598EB)
4343                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4344                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4345                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4346                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4347                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4348                 if (hw->mac.type == ixgbe_mac_82599EB) {
4349                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4350                                                             IXGBE_PXONRXCNT(i));
4351                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4352                                                            IXGBE_PXOFFRXCNT(i));
4353                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4354                 } else {
4355                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4356                                                               IXGBE_PXONRXC(i));
4357                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4358                                                              IXGBE_PXOFFRXC(i));
4359                 }
4360                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4361                                                             IXGBE_PXONTXC(i));
4362                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4363                                                              IXGBE_PXOFFTXC(i));
4364         }
4365         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4366         /* work around hardware counting issue */
4367         adapter->stats.gprc -= missed_rx;
4368
4369         /* 82598 hardware only has a 32 bit counter in the high register */
4370         if (hw->mac.type == ixgbe_mac_82599EB) {
4371                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4372                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4373                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4374                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4375                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4376                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4377                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4378                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4379                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4380                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4381 #ifdef IXGBE_FCOE
4382                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4383                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4384                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4385                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4386                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4387                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4388 #endif /* IXGBE_FCOE */
4389         } else {
4390                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4391                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4392                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4393                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4394                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4395         }
4396         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4397         adapter->stats.bprc += bprc;
4398         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4399         if (hw->mac.type == ixgbe_mac_82598EB)
4400                 adapter->stats.mprc -= bprc;
4401         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4402         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4403         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4404         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4405         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4406         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4407         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4408         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4409         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4410         adapter->stats.lxontxc += lxon;
4411         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4412         adapter->stats.lxofftxc += lxoff;
4413         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4414         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4415         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4416         /*
4417          * 82598 errata - tx of flow control packets is included in tx counters
4418          */
4419         xon_off_tot = lxon + lxoff;
4420         adapter->stats.gptc -= xon_off_tot;
4421         adapter->stats.mptc -= xon_off_tot;
4422         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4423         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4424         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4425         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4426         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4427         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4428         adapter->stats.ptc64 -= xon_off_tot;
4429         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4430         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4431         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4432         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4433         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4434         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4435
4436         /* Fill out the OS statistics structure */
4437         adapter->net_stats.multicast = adapter->stats.mprc;
4438
4439         /* Rx Errors */
4440         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4441                                        adapter->stats.rlec;
4442         adapter->net_stats.rx_dropped = 0;
4443         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4444         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4445         adapter->net_stats.rx_missed_errors = total_mpc;
4446 }
4447
4448 /**
4449  * ixgbe_watchdog - Timer Call-back
4450  * @data: pointer to adapter cast into an unsigned long
4451  **/
4452 static void ixgbe_watchdog(unsigned long data)
4453 {
4454         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4455         struct ixgbe_hw *hw = &adapter->hw;
4456         u64 eics = 0;
4457         int i;
4458
4459         /*
4460          *  Do the watchdog outside of interrupt context due to the lovely
4461          * delays that some of the newer hardware requires
4462          */
4463
4464         if (test_bit(__IXGBE_DOWN, &adapter->state))
4465                 goto watchdog_short_circuit;
4466
4467         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4468                 /*
4469                  * for legacy and MSI interrupts don't set any bits
4470                  * that are enabled for EIAM, because this operation
4471                  * would set *both* EIMS and EICS for any bit in EIAM
4472                  */
4473                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4474                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4475                 goto watchdog_reschedule;
4476         }
4477
4478         /* get one bit for every active tx/rx interrupt vector */
4479         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4480                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4481                 if (qv->rxr_count || qv->txr_count)
4482                         eics |= ((u64)1 << i);
4483         }
4484
4485         /* Cause software interrupt to ensure rx rings are cleaned */
4486         ixgbe_irq_rearm_queues(adapter, eics);
4487
4488 watchdog_reschedule:
4489         /* Reset the timer */
4490         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4491
4492 watchdog_short_circuit:
4493         schedule_work(&adapter->watchdog_task);
4494 }
4495
4496 /**
4497  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4498  * @work: pointer to work_struct containing our data
4499  **/
4500 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4501 {
4502         struct ixgbe_adapter *adapter = container_of(work,
4503                                                      struct ixgbe_adapter,
4504                                                      multispeed_fiber_task);
4505         struct ixgbe_hw *hw = &adapter->hw;
4506         u32 autoneg;
4507
4508         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4509         if (hw->mac.ops.get_link_capabilities)
4510                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4511                                                   &hw->mac.autoneg);
4512         if (hw->mac.ops.setup_link_speed)
4513                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4514         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4515         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4516 }
4517
4518 /**
4519  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4520  * @work: pointer to work_struct containing our data
4521  **/
4522 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4523 {
4524         struct ixgbe_adapter *adapter = container_of(work,
4525                                                      struct ixgbe_adapter,
4526                                                      sfp_config_module_task);
4527         struct ixgbe_hw *hw = &adapter->hw;
4528         u32 err;
4529
4530         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4531         err = hw->phy.ops.identify_sfp(hw);
4532         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4533                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4534                         "an unsupported SFP+ module type was detected.\n"
4535                         "Reload the driver after installing a supported "
4536                         "module.\n");
4537                 ixgbe_down(adapter);
4538                 return;
4539         }
4540         hw->mac.ops.setup_sfp(hw);
4541
4542         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4543                 /* This will also work for DA Twinax connections */
4544                 schedule_work(&adapter->multispeed_fiber_task);
4545         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4546 }
4547
4548 /**
4549  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4550  * @work: pointer to work_struct containing our data
4551  **/
4552 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4553 {
4554         struct ixgbe_adapter *adapter = container_of(work,
4555                                                      struct ixgbe_adapter,
4556                                                      fdir_reinit_task);
4557         struct ixgbe_hw *hw = &adapter->hw;
4558         int i;
4559
4560         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4561                 for (i = 0; i < adapter->num_tx_queues; i++)
4562                         set_bit(__IXGBE_FDIR_INIT_DONE,
4563                                 &(adapter->tx_ring[i].reinit_state));
4564         } else {
4565                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4566                         "ignored adding FDIR ATR filters \n");
4567         }
4568         /* Done FDIR Re-initialization, enable transmits */
4569         netif_tx_start_all_queues(adapter->netdev);
4570 }
4571
4572 /**
4573  * ixgbe_watchdog_task - worker thread to bring link up
4574  * @work: pointer to work_struct containing our data
4575  **/
4576 static void ixgbe_watchdog_task(struct work_struct *work)
4577 {
4578         struct ixgbe_adapter *adapter = container_of(work,
4579                                                      struct ixgbe_adapter,
4580                                                      watchdog_task);
4581         struct net_device *netdev = adapter->netdev;
4582         struct ixgbe_hw *hw = &adapter->hw;
4583         u32 link_speed = adapter->link_speed;
4584         bool link_up = adapter->link_up;
4585         int i;
4586         struct ixgbe_ring *tx_ring;
4587         int some_tx_pending = 0;
4588
4589         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4590
4591         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4592                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4593                 if (link_up) {
4594 #ifdef CONFIG_DCB
4595                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4596                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4597                                         hw->mac.ops.fc_enable(hw, i);
4598                         } else {
4599                                 hw->mac.ops.fc_enable(hw, 0);
4600                         }
4601 #else
4602                         hw->mac.ops.fc_enable(hw, 0);
4603 #endif
4604                 }
4605
4606                 if (link_up ||
4607                     time_after(jiffies, (adapter->link_check_timeout +
4608                                          IXGBE_TRY_LINK_TIMEOUT))) {
4609                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4610                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4611                 }
4612                 adapter->link_up = link_up;
4613                 adapter->link_speed = link_speed;
4614         }
4615
4616         if (link_up) {
4617                 if (!netif_carrier_ok(netdev)) {
4618                         bool flow_rx, flow_tx;
4619
4620                         if (hw->mac.type == ixgbe_mac_82599EB) {
4621                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4622                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4623                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4624                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4625                         } else {
4626                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4627                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4628                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4629                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4630                         }
4631
4632                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4633                                "Flow Control: %s\n",
4634                                netdev->name,
4635                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4636                                 "10 Gbps" :
4637                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4638                                  "1 Gbps" : "unknown speed")),
4639                                ((flow_rx && flow_tx) ? "RX/TX" :
4640                                 (flow_rx ? "RX" :
4641                                 (flow_tx ? "TX" : "None"))));
4642
4643                         netif_carrier_on(netdev);
4644                 } else {
4645                         /* Force detection of hung controller */
4646                         adapter->detect_tx_hung = true;
4647                 }
4648         } else {
4649                 adapter->link_up = false;
4650                 adapter->link_speed = 0;
4651                 if (netif_carrier_ok(netdev)) {
4652                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4653                                netdev->name);
4654                         netif_carrier_off(netdev);
4655                 }
4656         }
4657
4658         if (!netif_carrier_ok(netdev)) {
4659                 for (i = 0; i < adapter->num_tx_queues; i++) {
4660                         tx_ring = &adapter->tx_ring[i];
4661                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4662                                 some_tx_pending = 1;
4663                                 break;
4664                         }
4665                 }
4666
4667                 if (some_tx_pending) {
4668                         /* We've lost link, so the controller stops DMA,
4669                          * but we've got queued Tx work that's never going
4670                          * to get done, so reset controller to flush Tx.
4671                          * (Do the reset outside of interrupt context).
4672                          */
4673                          schedule_work(&adapter->reset_task);
4674                 }
4675         }
4676
4677         ixgbe_update_stats(adapter);
4678         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4679 }
4680
4681 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4682                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4683                      u32 tx_flags, u8 *hdr_len)
4684 {
4685         struct ixgbe_adv_tx_context_desc *context_desc;
4686         unsigned int i;
4687         int err;
4688         struct ixgbe_tx_buffer *tx_buffer_info;
4689         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4690         u32 mss_l4len_idx, l4len;
4691
4692         if (skb_is_gso(skb)) {
4693                 if (skb_header_cloned(skb)) {
4694                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4695                         if (err)
4696                                 return err;
4697                 }
4698                 l4len = tcp_hdrlen(skb);
4699                 *hdr_len += l4len;
4700
4701                 if (skb->protocol == htons(ETH_P_IP)) {
4702                         struct iphdr *iph = ip_hdr(skb);
4703                         iph->tot_len = 0;
4704                         iph->check = 0;
4705                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4706                                                                  iph->daddr, 0,
4707                                                                  IPPROTO_TCP,
4708                                                                  0);
4709                         adapter->hw_tso_ctxt++;
4710                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4711                         ipv6_hdr(skb)->payload_len = 0;
4712                         tcp_hdr(skb)->check =
4713                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4714                                              &ipv6_hdr(skb)->daddr,
4715                                              0, IPPROTO_TCP, 0);
4716                         adapter->hw_tso6_ctxt++;
4717                 }
4718
4719                 i = tx_ring->next_to_use;
4720
4721                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4722                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4723
4724                 /* VLAN MACLEN IPLEN */
4725                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4726                         vlan_macip_lens |=
4727                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4728                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4729                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4730                 *hdr_len += skb_network_offset(skb);
4731                 vlan_macip_lens |=
4732                     (skb_transport_header(skb) - skb_network_header(skb));
4733                 *hdr_len +=
4734                     (skb_transport_header(skb) - skb_network_header(skb));
4735                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4736                 context_desc->seqnum_seed = 0;
4737
4738                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4739                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4740                                    IXGBE_ADVTXD_DTYP_CTXT);
4741
4742                 if (skb->protocol == htons(ETH_P_IP))
4743                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4744                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4745                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4746
4747                 /* MSS L4LEN IDX */
4748                 mss_l4len_idx =
4749                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4750                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4751                 /* use index 1 for TSO */
4752                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4753                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4754
4755                 tx_buffer_info->time_stamp = jiffies;
4756                 tx_buffer_info->next_to_watch = i;
4757
4758                 i++;
4759                 if (i == tx_ring->count)
4760                         i = 0;
4761                 tx_ring->next_to_use = i;
4762
4763                 return true;
4764         }
4765         return false;
4766 }
4767
4768 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4769                           struct ixgbe_ring *tx_ring,
4770                           struct sk_buff *skb, u32 tx_flags)
4771 {
4772         struct ixgbe_adv_tx_context_desc *context_desc;
4773         unsigned int i;
4774         struct ixgbe_tx_buffer *tx_buffer_info;
4775         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4776
4777         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4778             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4779                 i = tx_ring->next_to_use;
4780                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4781                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4782
4783                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4784                         vlan_macip_lens |=
4785                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4786                 vlan_macip_lens |= (skb_network_offset(skb) <<
4787                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4788                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4789                         vlan_macip_lens |= (skb_transport_header(skb) -
4790                                             skb_network_header(skb));
4791
4792                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4793                 context_desc->seqnum_seed = 0;
4794
4795                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4796                                     IXGBE_ADVTXD_DTYP_CTXT);
4797
4798                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4799                         switch (skb->protocol) {
4800                         case cpu_to_be16(ETH_P_IP):
4801                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4802                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4803                                         type_tucmd_mlhl |=
4804                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4805                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4806                                         type_tucmd_mlhl |=
4807                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4808                                 break;
4809                         case cpu_to_be16(ETH_P_IPV6):
4810                                 /* XXX what about other V6 headers?? */
4811                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4812                                         type_tucmd_mlhl |=
4813                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4814                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4815                                         type_tucmd_mlhl |=
4816                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4817                                 break;
4818                         default:
4819                                 if (unlikely(net_ratelimit())) {
4820                                         DPRINTK(PROBE, WARNING,
4821                                          "partial checksum but proto=%x!\n",
4822                                          skb->protocol);
4823                                 }
4824                                 break;
4825                         }
4826                 }
4827
4828                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4829                 /* use index zero for tx checksum offload */
4830                 context_desc->mss_l4len_idx = 0;
4831
4832                 tx_buffer_info->time_stamp = jiffies;
4833                 tx_buffer_info->next_to_watch = i;
4834
4835                 adapter->hw_csum_tx_good++;
4836                 i++;
4837                 if (i == tx_ring->count)
4838                         i = 0;
4839                 tx_ring->next_to_use = i;
4840
4841                 return true;
4842         }
4843
4844         return false;
4845 }
4846
4847 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4848                         struct ixgbe_ring *tx_ring,
4849                         struct sk_buff *skb, u32 tx_flags,
4850                         unsigned int first)
4851 {
4852         struct ixgbe_tx_buffer *tx_buffer_info;
4853         unsigned int len;
4854         unsigned int total = skb->len;
4855         unsigned int offset = 0, size, count = 0, i;
4856         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4857         unsigned int f;
4858         dma_addr_t *map;
4859
4860         i = tx_ring->next_to_use;
4861
4862         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4863                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4864                 return 0;
4865         }
4866
4867         map = skb_shinfo(skb)->dma_maps;
4868
4869         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4870                 /* excluding fcoe_crc_eof for FCoE */
4871                 total -= sizeof(struct fcoe_crc_eof);
4872
4873         len = min(skb_headlen(skb), total);
4874         while (len) {
4875                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4876                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4877
4878                 tx_buffer_info->length = size;
4879                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4880                 tx_buffer_info->time_stamp = jiffies;
4881                 tx_buffer_info->next_to_watch = i;
4882
4883                 len -= size;
4884                 total -= size;
4885                 offset += size;
4886                 count++;
4887
4888                 if (len) {
4889                         i++;
4890                         if (i == tx_ring->count)
4891                                 i = 0;
4892                 }
4893         }
4894
4895         for (f = 0; f < nr_frags; f++) {
4896                 struct skb_frag_struct *frag;
4897
4898                 frag = &skb_shinfo(skb)->frags[f];
4899                 len = min((unsigned int)frag->size, total);
4900                 offset = 0;
4901
4902                 while (len) {
4903                         i++;
4904                         if (i == tx_ring->count)
4905                                 i = 0;
4906
4907                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4908                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4909
4910                         tx_buffer_info->length = size;
4911                         tx_buffer_info->dma = map[f] + offset;
4912                         tx_buffer_info->time_stamp = jiffies;
4913                         tx_buffer_info->next_to_watch = i;
4914
4915                         len -= size;
4916                         total -= size;
4917                         offset += size;
4918                         count++;
4919                 }
4920                 if (total == 0)
4921                         break;
4922         }
4923
4924         tx_ring->tx_buffer_info[i].skb = skb;
4925         tx_ring->tx_buffer_info[first].next_to_watch = i;
4926
4927         return count;
4928 }
4929
4930 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4931                            struct ixgbe_ring *tx_ring,
4932                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4933 {
4934         union ixgbe_adv_tx_desc *tx_desc = NULL;
4935         struct ixgbe_tx_buffer *tx_buffer_info;
4936         u32 olinfo_status = 0, cmd_type_len = 0;
4937         unsigned int i;
4938         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4939
4940         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4941
4942         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4943
4944         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4945                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4946
4947         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4948                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4949
4950                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4951                                  IXGBE_ADVTXD_POPTS_SHIFT;
4952
4953                 /* use index 1 context for tso */
4954                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4955                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4956                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4957                                          IXGBE_ADVTXD_POPTS_SHIFT;
4958
4959         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4960                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4961                                  IXGBE_ADVTXD_POPTS_SHIFT;
4962
4963         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4964                 olinfo_status |= IXGBE_ADVTXD_CC;
4965                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4966                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4967                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4968         }
4969
4970         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4971
4972         i = tx_ring->next_to_use;
4973         while (count--) {
4974                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4975                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4976                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4977                 tx_desc->read.cmd_type_len =
4978                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4979                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4980                 i++;
4981                 if (i == tx_ring->count)
4982                         i = 0;
4983         }
4984
4985         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4986
4987         /*
4988          * Force memory writes to complete before letting h/w
4989          * know there are new descriptors to fetch.  (Only
4990          * applicable for weak-ordered memory model archs,
4991          * such as IA-64).
4992          */
4993         wmb();
4994
4995         tx_ring->next_to_use = i;
4996         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4997 }
4998
4999 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5000                       int queue, u32 tx_flags)
5001 {
5002         /* Right now, we support IPv4 only */
5003         struct ixgbe_atr_input atr_input;
5004         struct tcphdr *th;
5005         struct udphdr *uh;
5006         struct iphdr *iph = ip_hdr(skb);
5007         struct ethhdr *eth = (struct ethhdr *)skb->data;
5008         u16 vlan_id, src_port, dst_port, flex_bytes;
5009         u32 src_ipv4_addr, dst_ipv4_addr;
5010         u8 l4type = 0;
5011
5012         /* check if we're UDP or TCP */
5013         if (iph->protocol == IPPROTO_TCP) {
5014                 th = tcp_hdr(skb);
5015                 src_port = th->source;
5016                 dst_port = th->dest;
5017                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5018                 /* l4type IPv4 type is 0, no need to assign */
5019         } else if(iph->protocol == IPPROTO_UDP) {
5020                 uh = udp_hdr(skb);
5021                 src_port = uh->source;
5022                 dst_port = uh->dest;
5023                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5024                 /* l4type IPv4 type is 0, no need to assign */
5025         } else {
5026                 /* Unsupported L4 header, just bail here */
5027                 return;
5028         }
5029
5030         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5031
5032         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5033                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5034         src_ipv4_addr = iph->saddr;
5035         dst_ipv4_addr = iph->daddr;
5036         flex_bytes = eth->h_proto;
5037
5038         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5039         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5040         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5041         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5042         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5043         /* src and dst are inverted, think how the receiver sees them */
5044         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5045         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5046
5047         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5048         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5049 }
5050
5051 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5052                                  struct ixgbe_ring *tx_ring, int size)
5053 {
5054         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5055
5056         netif_stop_subqueue(netdev, tx_ring->queue_index);
5057         /* Herbert's original patch had:
5058          *  smp_mb__after_netif_stop_queue();
5059          * but since that doesn't exist yet, just open code it. */
5060         smp_mb();
5061
5062         /* We need to check again in a case another CPU has just
5063          * made room available. */
5064         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5065                 return -EBUSY;
5066
5067         /* A reprieve! - use start_queue because it doesn't call schedule */
5068         netif_start_subqueue(netdev, tx_ring->queue_index);
5069         ++adapter->restart_queue;
5070         return 0;
5071 }
5072
5073 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5074                               struct ixgbe_ring *tx_ring, int size)
5075 {
5076         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5077                 return 0;
5078         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5079 }
5080
5081 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5082 {
5083         struct ixgbe_adapter *adapter = netdev_priv(dev);
5084
5085         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5086                 return smp_processor_id();
5087
5088         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5089                 return 0;  /* All traffic should default to class 0 */
5090
5091         return skb_tx_hash(dev, skb);
5092 }
5093
5094 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5095 {
5096         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5097         struct ixgbe_ring *tx_ring;
5098         unsigned int first;
5099         unsigned int tx_flags = 0;
5100         u8 hdr_len = 0;
5101         int r_idx = 0, tso;
5102         int count = 0;
5103         unsigned int f;
5104
5105         r_idx = skb->queue_mapping;
5106         tx_ring = &adapter->tx_ring[r_idx];
5107
5108         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5109                 tx_flags |= vlan_tx_tag_get(skb);
5110                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5111                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5112                         tx_flags |= (skb->queue_mapping << 13);
5113                 }
5114                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5115                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5116         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5117                 tx_flags |= (skb->queue_mapping << 13);
5118                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5119                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5120         }
5121
5122         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5123             (skb->protocol == htons(ETH_P_FCOE)))
5124                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5125
5126         /* four things can cause us to need a context descriptor */
5127         if (skb_is_gso(skb) ||
5128             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5129             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5130             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5131                 count++;
5132
5133         count += TXD_USE_COUNT(skb_headlen(skb));
5134         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5135                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5136
5137         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5138                 adapter->tx_busy++;
5139                 return NETDEV_TX_BUSY;
5140         }
5141
5142         first = tx_ring->next_to_use;
5143         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5144 #ifdef IXGBE_FCOE
5145                 /* setup tx offload for FCoE */
5146                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5147                 if (tso < 0) {
5148                         dev_kfree_skb_any(skb);
5149                         return NETDEV_TX_OK;
5150                 }
5151                 if (tso)
5152                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5153 #endif /* IXGBE_FCOE */
5154         } else {
5155                 if (skb->protocol == htons(ETH_P_IP))
5156                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5157                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5158                 if (tso < 0) {
5159                         dev_kfree_skb_any(skb);
5160                         return NETDEV_TX_OK;
5161                 }
5162
5163                 if (tso)
5164                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5165                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5166                          (skb->ip_summed == CHECKSUM_PARTIAL))
5167                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5168         }
5169
5170         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5171         if (count) {
5172                 /* add the ATR filter if ATR is on */
5173                 if (tx_ring->atr_sample_rate) {
5174                         ++tx_ring->atr_count;
5175                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5176                              test_bit(__IXGBE_FDIR_INIT_DONE,
5177                                       &tx_ring->reinit_state)) {
5178                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5179                                           tx_flags);
5180                                 tx_ring->atr_count = 0;
5181                         }
5182                 }
5183                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5184                                hdr_len);
5185                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5186
5187         } else {
5188                 dev_kfree_skb_any(skb);
5189                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5190                 tx_ring->next_to_use = first;
5191         }
5192
5193         return NETDEV_TX_OK;
5194 }
5195
5196 /**
5197  * ixgbe_get_stats - Get System Network Statistics
5198  * @netdev: network interface device structure
5199  *
5200  * Returns the address of the device statistics structure.
5201  * The statistics are actually updated from the timer callback.
5202  **/
5203 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5204 {
5205         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5206
5207         /* only return the current stats */
5208         return &adapter->net_stats;
5209 }
5210
5211 /**
5212  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5213  * @netdev: network interface device structure
5214  * @p: pointer to an address structure
5215  *
5216  * Returns 0 on success, negative on failure
5217  **/
5218 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5219 {
5220         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5221         struct ixgbe_hw *hw = &adapter->hw;
5222         struct sockaddr *addr = p;
5223
5224         if (!is_valid_ether_addr(addr->sa_data))
5225                 return -EADDRNOTAVAIL;
5226
5227         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5228         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5229
5230         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5231
5232         return 0;
5233 }
5234
5235 static int
5236 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5237 {
5238         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5239         struct ixgbe_hw *hw = &adapter->hw;
5240         u16 value;
5241         int rc;
5242
5243         if (prtad != hw->phy.mdio.prtad)
5244                 return -EINVAL;
5245         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5246         if (!rc)
5247                 rc = value;
5248         return rc;
5249 }
5250
5251 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5252                             u16 addr, u16 value)
5253 {
5254         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5255         struct ixgbe_hw *hw = &adapter->hw;
5256
5257         if (prtad != hw->phy.mdio.prtad)
5258                 return -EINVAL;
5259         return hw->phy.ops.write_reg(hw, addr, devad, value);
5260 }
5261
5262 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5263 {
5264         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5265
5266         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5267 }
5268
5269 /**
5270  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5271  * netdev->dev_addrs
5272  * @netdev: network interface device structure
5273  *
5274  * Returns non-zero on failure
5275  **/
5276 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5277 {
5278         int err = 0;
5279         struct ixgbe_adapter *adapter = netdev_priv(dev);
5280         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5281
5282         if (is_valid_ether_addr(mac->san_addr)) {
5283                 rtnl_lock();
5284                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5285                 rtnl_unlock();
5286         }
5287         return err;
5288 }
5289
5290 /**
5291  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5292  * netdev->dev_addrs
5293  * @netdev: network interface device structure
5294  *
5295  * Returns non-zero on failure
5296  **/
5297 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5298 {
5299         int err = 0;
5300         struct ixgbe_adapter *adapter = netdev_priv(dev);
5301         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5302
5303         if (is_valid_ether_addr(mac->san_addr)) {
5304                 rtnl_lock();
5305                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5306                 rtnl_unlock();
5307         }
5308         return err;
5309 }
5310
5311 #ifdef CONFIG_NET_POLL_CONTROLLER
5312 /*
5313  * Polling 'interrupt' - used by things like netconsole to send skbs
5314  * without having to re-enable interrupts. It's not called while
5315  * the interrupt routine is executing.
5316  */
5317 static void ixgbe_netpoll(struct net_device *netdev)
5318 {
5319         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5320
5321         disable_irq(adapter->pdev->irq);
5322         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5323         ixgbe_intr(adapter->pdev->irq, netdev);
5324         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5325         enable_irq(adapter->pdev->irq);
5326 }
5327 #endif
5328
5329 static const struct net_device_ops ixgbe_netdev_ops = {
5330         .ndo_open               = ixgbe_open,
5331         .ndo_stop               = ixgbe_close,
5332         .ndo_start_xmit         = ixgbe_xmit_frame,
5333         .ndo_select_queue       = ixgbe_select_queue,
5334         .ndo_get_stats          = ixgbe_get_stats,
5335         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5336         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5337         .ndo_validate_addr      = eth_validate_addr,
5338         .ndo_set_mac_address    = ixgbe_set_mac,
5339         .ndo_change_mtu         = ixgbe_change_mtu,
5340         .ndo_tx_timeout         = ixgbe_tx_timeout,
5341         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5342         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5343         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5344         .ndo_do_ioctl           = ixgbe_ioctl,
5345 #ifdef CONFIG_NET_POLL_CONTROLLER
5346         .ndo_poll_controller    = ixgbe_netpoll,
5347 #endif
5348 #ifdef IXGBE_FCOE
5349         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5350         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5351 #endif /* IXGBE_FCOE */
5352 };
5353
5354 /**
5355  * ixgbe_probe - Device Initialization Routine
5356  * @pdev: PCI device information struct
5357  * @ent: entry in ixgbe_pci_tbl
5358  *
5359  * Returns 0 on success, negative on failure
5360  *
5361  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5362  * The OS initialization, configuring of the adapter private structure,
5363  * and a hardware reset occur.
5364  **/
5365 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5366                                  const struct pci_device_id *ent)
5367 {
5368         struct net_device *netdev;
5369         struct ixgbe_adapter *adapter = NULL;
5370         struct ixgbe_hw *hw;
5371         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5372         static int cards_found;
5373         int i, err, pci_using_dac;
5374 #ifdef IXGBE_FCOE
5375         u16 device_caps;
5376 #endif
5377         u32 part_num, eec;
5378
5379         err = pci_enable_device_mem(pdev);
5380         if (err)
5381                 return err;
5382
5383         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5384             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5385                 pci_using_dac = 1;
5386         } else {
5387                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5388                 if (err) {
5389                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5390                         if (err) {
5391                                 dev_err(&pdev->dev, "No usable DMA "
5392                                         "configuration, aborting\n");
5393                                 goto err_dma;
5394                         }
5395                 }
5396                 pci_using_dac = 0;
5397         }
5398
5399         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5400                                            IORESOURCE_MEM), ixgbe_driver_name);
5401         if (err) {
5402                 dev_err(&pdev->dev,
5403                         "pci_request_selected_regions failed 0x%x\n", err);
5404                 goto err_pci_reg;
5405         }
5406
5407         err = pci_enable_pcie_error_reporting(pdev);
5408         if (err) {
5409                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5410                                     "0x%x\n", err);
5411                 /* non-fatal, continue */
5412         }
5413
5414         pci_set_master(pdev);
5415         pci_save_state(pdev);
5416
5417         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5418         if (!netdev) {
5419                 err = -ENOMEM;
5420                 goto err_alloc_etherdev;
5421         }
5422
5423         SET_NETDEV_DEV(netdev, &pdev->dev);
5424
5425         pci_set_drvdata(pdev, netdev);
5426         adapter = netdev_priv(netdev);
5427
5428         adapter->netdev = netdev;
5429         adapter->pdev = pdev;
5430         hw = &adapter->hw;
5431         hw->back = adapter;
5432         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5433
5434         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5435                               pci_resource_len(pdev, 0));
5436         if (!hw->hw_addr) {
5437                 err = -EIO;
5438                 goto err_ioremap;
5439         }
5440
5441         for (i = 1; i <= 5; i++) {
5442                 if (pci_resource_len(pdev, i) == 0)
5443                         continue;
5444         }
5445
5446         netdev->netdev_ops = &ixgbe_netdev_ops;
5447         ixgbe_set_ethtool_ops(netdev);
5448         netdev->watchdog_timeo = 5 * HZ;
5449         strcpy(netdev->name, pci_name(pdev));
5450
5451         adapter->bd_number = cards_found;
5452
5453         /* Setup hw api */
5454         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5455         hw->mac.type  = ii->mac;
5456
5457         /* EEPROM */
5458         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5459         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5460         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5461         if (!(eec & (1 << 8)))
5462                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5463
5464         /* PHY */
5465         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5466         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5467         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5468         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5469         hw->phy.mdio.mmds = 0;
5470         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5471         hw->phy.mdio.dev = netdev;
5472         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5473         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5474
5475         /* set up this timer and work struct before calling get_invariants
5476          * which might start the timer
5477          */
5478         init_timer(&adapter->sfp_timer);
5479         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5480         adapter->sfp_timer.data = (unsigned long) adapter;
5481
5482         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5483
5484         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5485         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5486
5487         /* a new SFP+ module arrival, called from GPI SDP2 context */
5488         INIT_WORK(&adapter->sfp_config_module_task,
5489                   ixgbe_sfp_config_module_task);
5490
5491         ii->get_invariants(hw);
5492
5493         /* setup the private structure */
5494         err = ixgbe_sw_init(adapter);
5495         if (err)
5496                 goto err_sw_init;
5497
5498         /*
5499          * If there is a fan on this device and it has failed log the
5500          * failure.
5501          */
5502         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5503                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5504                 if (esdp & IXGBE_ESDP_SDP1)
5505                         DPRINTK(PROBE, CRIT,
5506                                 "Fan has stopped, replace the adapter\n");
5507         }
5508
5509         /* reset_hw fills in the perm_addr as well */
5510         err = hw->mac.ops.reset_hw(hw);
5511         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5512             hw->mac.type == ixgbe_mac_82598EB) {
5513                 /*
5514                  * Start a kernel thread to watch for a module to arrive.
5515                  * Only do this for 82598, since 82599 will generate
5516                  * interrupts on module arrival.
5517                  */
5518                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5519                 mod_timer(&adapter->sfp_timer,
5520                           round_jiffies(jiffies + (2 * HZ)));
5521                 err = 0;
5522         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5523                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5524                         "an unsupported SFP+ module type was detected.\n"
5525                         "Reload the driver after installing a supported "
5526                         "module.\n");
5527                 goto err_sw_init;
5528         } else if (err) {
5529                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5530                 goto err_sw_init;
5531         }
5532
5533         netdev->features = NETIF_F_SG |
5534                            NETIF_F_IP_CSUM |
5535                            NETIF_F_HW_VLAN_TX |
5536                            NETIF_F_HW_VLAN_RX |
5537                            NETIF_F_HW_VLAN_FILTER;
5538
5539         netdev->features |= NETIF_F_IPV6_CSUM;
5540         netdev->features |= NETIF_F_TSO;
5541         netdev->features |= NETIF_F_TSO6;
5542         netdev->features |= NETIF_F_GRO;
5543
5544         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5545                 netdev->features |= NETIF_F_SCTP_CSUM;
5546
5547         netdev->vlan_features |= NETIF_F_TSO;
5548         netdev->vlan_features |= NETIF_F_TSO6;
5549         netdev->vlan_features |= NETIF_F_IP_CSUM;
5550         netdev->vlan_features |= NETIF_F_SG;
5551
5552         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5553                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5554
5555 #ifdef CONFIG_IXGBE_DCB
5556         netdev->dcbnl_ops = &dcbnl_ops;
5557 #endif
5558
5559 #ifdef IXGBE_FCOE
5560         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5561                 if (hw->mac.ops.get_device_caps) {
5562                         hw->mac.ops.get_device_caps(hw, &device_caps);
5563                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5564                                 netdev->features |= NETIF_F_FCOE_CRC;
5565                                 netdev->features |= NETIF_F_FSO;
5566                                 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5567                                 DPRINTK(DRV, INFO, "FCoE enabled, "
5568                                         "disabling Flow Director\n");
5569                                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
5570                                 adapter->flags &=
5571                                         ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5572                                 adapter->atr_sample_rate = 0;
5573                         } else {
5574                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5575                         }
5576                 }
5577         }
5578 #endif /* IXGBE_FCOE */
5579         if (pci_using_dac)
5580                 netdev->features |= NETIF_F_HIGHDMA;
5581
5582         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
5583                 netdev->features |= NETIF_F_LRO;
5584
5585         /* make sure the EEPROM is good */
5586         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5587                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5588                 err = -EIO;
5589                 goto err_eeprom;
5590         }
5591
5592         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5593         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5594
5595         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5596                 dev_err(&pdev->dev, "invalid MAC address\n");
5597                 err = -EIO;
5598                 goto err_eeprom;
5599         }
5600
5601         init_timer(&adapter->watchdog_timer);
5602         adapter->watchdog_timer.function = &ixgbe_watchdog;
5603         adapter->watchdog_timer.data = (unsigned long)adapter;
5604
5605         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5606         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5607
5608         err = ixgbe_init_interrupt_scheme(adapter);
5609         if (err)
5610                 goto err_sw_init;
5611
5612         switch (pdev->device) {
5613         case IXGBE_DEV_ID_82599_KX4:
5614                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5615                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5616                 /* Enable ACPI wakeup in GRC */
5617                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5618                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5619                 break;
5620         default:
5621                 adapter->wol = 0;
5622                 break;
5623         }
5624         device_init_wakeup(&adapter->pdev->dev, true);
5625         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5626
5627         /* pick up the PCI bus settings for reporting later */
5628         hw->mac.ops.get_bus_info(hw);
5629
5630         /* print bus type/speed/width info */
5631         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5632                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5633                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5634                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5635                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5636                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5637                  "Unknown"),
5638                 netdev->dev_addr);
5639         ixgbe_read_pba_num_generic(hw, &part_num);
5640         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5641                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5642                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5643                          (part_num >> 8), (part_num & 0xff));
5644         else
5645                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5646                          hw->mac.type, hw->phy.type,
5647                          (part_num >> 8), (part_num & 0xff));
5648
5649         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5650                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5651                          "this card is not sufficient for optimal "
5652                          "performance.\n");
5653                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5654                          "PCI-Express slot is required.\n");
5655         }
5656
5657         /* save off EEPROM version number */
5658         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5659
5660         /* reset the hardware with the new settings */
5661         err = hw->mac.ops.start_hw(hw);
5662
5663         if (err == IXGBE_ERR_EEPROM_VERSION) {
5664                 /* We are running on a pre-production device, log a warning */
5665                 dev_warn(&pdev->dev, "This device is a pre-production "
5666                          "adapter/LOM.  Please be aware there may be issues "
5667                          "associated with your hardware.  If you are "
5668                          "experiencing problems please contact your Intel or "
5669                          "hardware representative who provided you with this "
5670                          "hardware.\n");
5671         }
5672         strcpy(netdev->name, "eth%d");
5673         err = register_netdev(netdev);
5674         if (err)
5675                 goto err_register;
5676
5677         /* carrier off reporting is important to ethtool even BEFORE open */
5678         netif_carrier_off(netdev);
5679
5680         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5681             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5682                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5683
5684 #ifdef CONFIG_IXGBE_DCA
5685         if (dca_add_requester(&pdev->dev) == 0) {
5686                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5687                 ixgbe_setup_dca(adapter);
5688         }
5689 #endif
5690         /* add san mac addr to netdev */
5691         ixgbe_add_sanmac_netdev(netdev);
5692
5693         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5694         cards_found++;
5695         return 0;
5696
5697 err_register:
5698         ixgbe_release_hw_control(adapter);
5699         ixgbe_clear_interrupt_scheme(adapter);
5700 err_sw_init:
5701 err_eeprom:
5702         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5703         del_timer_sync(&adapter->sfp_timer);
5704         cancel_work_sync(&adapter->sfp_task);
5705         cancel_work_sync(&adapter->multispeed_fiber_task);
5706         cancel_work_sync(&adapter->sfp_config_module_task);
5707         iounmap(hw->hw_addr);
5708 err_ioremap:
5709         free_netdev(netdev);
5710 err_alloc_etherdev:
5711         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5712                                      IORESOURCE_MEM));
5713 err_pci_reg:
5714 err_dma:
5715         pci_disable_device(pdev);
5716         return err;
5717 }
5718
5719 /**
5720  * ixgbe_remove - Device Removal Routine
5721  * @pdev: PCI device information struct
5722  *
5723  * ixgbe_remove is called by the PCI subsystem to alert the driver
5724  * that it should release a PCI device.  The could be caused by a
5725  * Hot-Plug event, or because the driver is going to be removed from
5726  * memory.
5727  **/
5728 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5729 {
5730         struct net_device *netdev = pci_get_drvdata(pdev);
5731         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5732         int err;
5733
5734         set_bit(__IXGBE_DOWN, &adapter->state);
5735         /* clear the module not found bit to make sure the worker won't
5736          * reschedule
5737          */
5738         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5739         del_timer_sync(&adapter->watchdog_timer);
5740
5741         del_timer_sync(&adapter->sfp_timer);
5742         cancel_work_sync(&adapter->watchdog_task);
5743         cancel_work_sync(&adapter->sfp_task);
5744         cancel_work_sync(&adapter->multispeed_fiber_task);
5745         cancel_work_sync(&adapter->sfp_config_module_task);
5746         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5747             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5748                 cancel_work_sync(&adapter->fdir_reinit_task);
5749         flush_scheduled_work();
5750
5751 #ifdef CONFIG_IXGBE_DCA
5752         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5753                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5754                 dca_remove_requester(&pdev->dev);
5755                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5756         }
5757
5758 #endif
5759 #ifdef IXGBE_FCOE
5760         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5761                 ixgbe_cleanup_fcoe(adapter);
5762
5763 #endif /* IXGBE_FCOE */
5764
5765         /* remove the added san mac */
5766         ixgbe_del_sanmac_netdev(netdev);
5767
5768         if (netdev->reg_state == NETREG_REGISTERED)
5769                 unregister_netdev(netdev);
5770
5771         ixgbe_clear_interrupt_scheme(adapter);
5772
5773         ixgbe_release_hw_control(adapter);
5774
5775         iounmap(adapter->hw.hw_addr);
5776         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5777                                      IORESOURCE_MEM));
5778
5779         DPRINTK(PROBE, INFO, "complete\n");
5780
5781         free_netdev(netdev);
5782
5783         err = pci_disable_pcie_error_reporting(pdev);
5784         if (err)
5785                 dev_err(&pdev->dev,
5786                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5787
5788         pci_disable_device(pdev);
5789 }
5790
5791 /**
5792  * ixgbe_io_error_detected - called when PCI error is detected
5793  * @pdev: Pointer to PCI device
5794  * @state: The current pci connection state
5795  *
5796  * This function is called after a PCI bus error affecting
5797  * this device has been detected.
5798  */
5799 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5800                                                 pci_channel_state_t state)
5801 {
5802         struct net_device *netdev = pci_get_drvdata(pdev);
5803         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5804
5805         netif_device_detach(netdev);
5806
5807         if (state == pci_channel_io_perm_failure)
5808                 return PCI_ERS_RESULT_DISCONNECT;
5809
5810         if (netif_running(netdev))
5811                 ixgbe_down(adapter);
5812         pci_disable_device(pdev);
5813
5814         /* Request a slot reset. */
5815         return PCI_ERS_RESULT_NEED_RESET;
5816 }
5817
5818 /**
5819  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5820  * @pdev: Pointer to PCI device
5821  *
5822  * Restart the card from scratch, as if from a cold-boot.
5823  */
5824 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5825 {
5826         struct net_device *netdev = pci_get_drvdata(pdev);
5827         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5828         pci_ers_result_t result;
5829         int err;
5830
5831         if (pci_enable_device_mem(pdev)) {
5832                 DPRINTK(PROBE, ERR,
5833                         "Cannot re-enable PCI device after reset.\n");
5834                 result = PCI_ERS_RESULT_DISCONNECT;
5835         } else {
5836                 pci_set_master(pdev);
5837                 pci_restore_state(pdev);
5838
5839                 pci_wake_from_d3(pdev, false);
5840
5841                 ixgbe_reset(adapter);
5842                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5843                 result = PCI_ERS_RESULT_RECOVERED;
5844         }
5845
5846         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5847         if (err) {
5848                 dev_err(&pdev->dev,
5849                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5850                 /* non-fatal, continue */
5851         }
5852
5853         return result;
5854 }
5855
5856 /**
5857  * ixgbe_io_resume - called when traffic can start flowing again.
5858  * @pdev: Pointer to PCI device
5859  *
5860  * This callback is called when the error recovery driver tells us that
5861  * its OK to resume normal operation.
5862  */
5863 static void ixgbe_io_resume(struct pci_dev *pdev)
5864 {
5865         struct net_device *netdev = pci_get_drvdata(pdev);
5866         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5867
5868         if (netif_running(netdev)) {
5869                 if (ixgbe_up(adapter)) {
5870                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5871                         return;
5872                 }
5873         }
5874
5875         netif_device_attach(netdev);
5876 }
5877
5878 static struct pci_error_handlers ixgbe_err_handler = {
5879         .error_detected = ixgbe_io_error_detected,
5880         .slot_reset = ixgbe_io_slot_reset,
5881         .resume = ixgbe_io_resume,
5882 };
5883
5884 static struct pci_driver ixgbe_driver = {
5885         .name     = ixgbe_driver_name,
5886         .id_table = ixgbe_pci_tbl,
5887         .probe    = ixgbe_probe,
5888         .remove   = __devexit_p(ixgbe_remove),
5889 #ifdef CONFIG_PM
5890         .suspend  = ixgbe_suspend,
5891         .resume   = ixgbe_resume,
5892 #endif
5893         .shutdown = ixgbe_shutdown,
5894         .err_handler = &ixgbe_err_handler
5895 };
5896
5897 /**
5898  * ixgbe_init_module - Driver Registration Routine
5899  *
5900  * ixgbe_init_module is the first routine called when the driver is
5901  * loaded. All it does is register with the PCI subsystem.
5902  **/
5903 static int __init ixgbe_init_module(void)
5904 {
5905         int ret;
5906         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5907                ixgbe_driver_string, ixgbe_driver_version);
5908
5909         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5910
5911 #ifdef CONFIG_IXGBE_DCA
5912         dca_register_notify(&dca_notifier);
5913 #endif
5914
5915         ret = pci_register_driver(&ixgbe_driver);
5916         return ret;
5917 }
5918
5919 module_init(ixgbe_init_module);
5920
5921 /**
5922  * ixgbe_exit_module - Driver Exit Cleanup Routine
5923  *
5924  * ixgbe_exit_module is called just before the driver is removed
5925  * from memory.
5926  **/
5927 static void __exit ixgbe_exit_module(void)
5928 {
5929 #ifdef CONFIG_IXGBE_DCA
5930         dca_unregister_notify(&dca_notifier);
5931 #endif
5932         pci_unregister_driver(&ixgbe_driver);
5933 }
5934
5935 #ifdef CONFIG_IXGBE_DCA
5936 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5937                             void *p)
5938 {
5939         int ret_val;
5940
5941         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5942                                          __ixgbe_notify_dca);
5943
5944         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5945 }
5946
5947 #endif /* CONFIG_IXGBE_DCA */
5948 #ifdef DEBUG
5949 /**
5950  * ixgbe_get_hw_dev_name - return device name string
5951  * used by hardware layer to print debugging information
5952  **/
5953 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5954 {
5955         struct ixgbe_adapter *adapter = hw->back;
5956         return adapter->netdev->name;
5957 }
5958
5959 #endif
5960 module_exit(ixgbe_exit_module);
5961
5962 /* ixgbe_main.c */