Merge branch 'misc' into release
[linux-2.6] / arch / powerpc / sysdev / ipic.c
1 /*
2  * arch/powerpc/sysdev/ipic.c
3  *
4  * IPIC routines implementations.
5  *
6  * Copyright 2005 Freescale Semiconductor, Inc.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <linux/fsl_devices.h>
26 #include <asm/irq.h>
27 #include <asm/io.h>
28 #include <asm/prom.h>
29 #include <asm/ipic.h>
30
31 #include "ipic.h"
32
33 static struct ipic * primary_ipic;
34 static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
35 static DEFINE_SPINLOCK(ipic_lock);
36
37 static struct ipic_info ipic_info[] = {
38         [1] = {
39                 .mask   = IPIC_SIMSR_H,
40                 .prio   = IPIC_SIPRR_C,
41                 .force  = IPIC_SIFCR_H,
42                 .bit    = 16,
43                 .prio_mask = 0,
44         },
45         [2] = {
46                 .mask   = IPIC_SIMSR_H,
47                 .prio   = IPIC_SIPRR_C,
48                 .force  = IPIC_SIFCR_H,
49                 .bit    = 17,
50                 .prio_mask = 1,
51         },
52         [3] = {
53                 .mask   = IPIC_SIMSR_H,
54                 .prio   = IPIC_SIPRR_C,
55                 .force  = IPIC_SIFCR_H,
56                 .bit    = 18,
57                 .prio_mask = 2,
58         },
59         [4] = {
60                 .mask   = IPIC_SIMSR_H,
61                 .prio   = IPIC_SIPRR_C,
62                 .force  = IPIC_SIFCR_H,
63                 .bit    = 19,
64                 .prio_mask = 3,
65         },
66         [5] = {
67                 .mask   = IPIC_SIMSR_H,
68                 .prio   = IPIC_SIPRR_C,
69                 .force  = IPIC_SIFCR_H,
70                 .bit    = 20,
71                 .prio_mask = 4,
72         },
73         [6] = {
74                 .mask   = IPIC_SIMSR_H,
75                 .prio   = IPIC_SIPRR_C,
76                 .force  = IPIC_SIFCR_H,
77                 .bit    = 21,
78                 .prio_mask = 5,
79         },
80         [7] = {
81                 .mask   = IPIC_SIMSR_H,
82                 .prio   = IPIC_SIPRR_C,
83                 .force  = IPIC_SIFCR_H,
84                 .bit    = 22,
85                 .prio_mask = 6,
86         },
87         [8] = {
88                 .mask   = IPIC_SIMSR_H,
89                 .prio   = IPIC_SIPRR_C,
90                 .force  = IPIC_SIFCR_H,
91                 .bit    = 23,
92                 .prio_mask = 7,
93         },
94         [9] = {
95                 .mask   = IPIC_SIMSR_H,
96                 .prio   = IPIC_SIPRR_D,
97                 .force  = IPIC_SIFCR_H,
98                 .bit    = 24,
99                 .prio_mask = 0,
100         },
101         [10] = {
102                 .mask   = IPIC_SIMSR_H,
103                 .prio   = IPIC_SIPRR_D,
104                 .force  = IPIC_SIFCR_H,
105                 .bit    = 25,
106                 .prio_mask = 1,
107         },
108         [11] = {
109                 .mask   = IPIC_SIMSR_H,
110                 .prio   = IPIC_SIPRR_D,
111                 .force  = IPIC_SIFCR_H,
112                 .bit    = 26,
113                 .prio_mask = 2,
114         },
115         [12] = {
116                 .mask   = IPIC_SIMSR_H,
117                 .prio   = IPIC_SIPRR_D,
118                 .force  = IPIC_SIFCR_H,
119                 .bit    = 27,
120                 .prio_mask = 3,
121         },
122         [13] = {
123                 .mask   = IPIC_SIMSR_H,
124                 .prio   = IPIC_SIPRR_D,
125                 .force  = IPIC_SIFCR_H,
126                 .bit    = 28,
127                 .prio_mask = 4,
128         },
129         [14] = {
130                 .mask   = IPIC_SIMSR_H,
131                 .prio   = IPIC_SIPRR_D,
132                 .force  = IPIC_SIFCR_H,
133                 .bit    = 29,
134                 .prio_mask = 5,
135         },
136         [15] = {
137                 .mask   = IPIC_SIMSR_H,
138                 .prio   = IPIC_SIPRR_D,
139                 .force  = IPIC_SIFCR_H,
140                 .bit    = 30,
141                 .prio_mask = 6,
142         },
143         [16] = {
144                 .mask   = IPIC_SIMSR_H,
145                 .prio   = IPIC_SIPRR_D,
146                 .force  = IPIC_SIFCR_H,
147                 .bit    = 31,
148                 .prio_mask = 7,
149         },
150         [17] = {
151                 .ack    = IPIC_SEPNR,
152                 .mask   = IPIC_SEMSR,
153                 .prio   = IPIC_SMPRR_A,
154                 .force  = IPIC_SEFCR,
155                 .bit    = 1,
156                 .prio_mask = 5,
157         },
158         [18] = {
159                 .ack    = IPIC_SEPNR,
160                 .mask   = IPIC_SEMSR,
161                 .prio   = IPIC_SMPRR_A,
162                 .force  = IPIC_SEFCR,
163                 .bit    = 2,
164                 .prio_mask = 6,
165         },
166         [19] = {
167                 .ack    = IPIC_SEPNR,
168                 .mask   = IPIC_SEMSR,
169                 .prio   = IPIC_SMPRR_A,
170                 .force  = IPIC_SEFCR,
171                 .bit    = 3,
172                 .prio_mask = 7,
173         },
174         [20] = {
175                 .ack    = IPIC_SEPNR,
176                 .mask   = IPIC_SEMSR,
177                 .prio   = IPIC_SMPRR_B,
178                 .force  = IPIC_SEFCR,
179                 .bit    = 4,
180                 .prio_mask = 4,
181         },
182         [21] = {
183                 .ack    = IPIC_SEPNR,
184                 .mask   = IPIC_SEMSR,
185                 .prio   = IPIC_SMPRR_B,
186                 .force  = IPIC_SEFCR,
187                 .bit    = 5,
188                 .prio_mask = 5,
189         },
190         [22] = {
191                 .ack    = IPIC_SEPNR,
192                 .mask   = IPIC_SEMSR,
193                 .prio   = IPIC_SMPRR_B,
194                 .force  = IPIC_SEFCR,
195                 .bit    = 6,
196                 .prio_mask = 6,
197         },
198         [23] = {
199                 .ack    = IPIC_SEPNR,
200                 .mask   = IPIC_SEMSR,
201                 .prio   = IPIC_SMPRR_B,
202                 .force  = IPIC_SEFCR,
203                 .bit    = 7,
204                 .prio_mask = 7,
205         },
206         [32] = {
207                 .mask   = IPIC_SIMSR_H,
208                 .prio   = IPIC_SIPRR_A,
209                 .force  = IPIC_SIFCR_H,
210                 .bit    = 0,
211                 .prio_mask = 0,
212         },
213         [33] = {
214                 .mask   = IPIC_SIMSR_H,
215                 .prio   = IPIC_SIPRR_A,
216                 .force  = IPIC_SIFCR_H,
217                 .bit    = 1,
218                 .prio_mask = 1,
219         },
220         [34] = {
221                 .mask   = IPIC_SIMSR_H,
222                 .prio   = IPIC_SIPRR_A,
223                 .force  = IPIC_SIFCR_H,
224                 .bit    = 2,
225                 .prio_mask = 2,
226         },
227         [35] = {
228                 .mask   = IPIC_SIMSR_H,
229                 .prio   = IPIC_SIPRR_A,
230                 .force  = IPIC_SIFCR_H,
231                 .bit    = 3,
232                 .prio_mask = 3,
233         },
234         [36] = {
235                 .mask   = IPIC_SIMSR_H,
236                 .prio   = IPIC_SIPRR_A,
237                 .force  = IPIC_SIFCR_H,
238                 .bit    = 4,
239                 .prio_mask = 4,
240         },
241         [37] = {
242                 .mask   = IPIC_SIMSR_H,
243                 .prio   = IPIC_SIPRR_A,
244                 .force  = IPIC_SIFCR_H,
245                 .bit    = 5,
246                 .prio_mask = 5,
247         },
248         [38] = {
249                 .mask   = IPIC_SIMSR_H,
250                 .prio   = IPIC_SIPRR_A,
251                 .force  = IPIC_SIFCR_H,
252                 .bit    = 6,
253                 .prio_mask = 6,
254         },
255         [39] = {
256                 .mask   = IPIC_SIMSR_H,
257                 .prio   = IPIC_SIPRR_A,
258                 .force  = IPIC_SIFCR_H,
259                 .bit    = 7,
260                 .prio_mask = 7,
261         },
262         [40] = {
263                 .mask   = IPIC_SIMSR_H,
264                 .prio   = IPIC_SIPRR_B,
265                 .force  = IPIC_SIFCR_H,
266                 .bit    = 8,
267                 .prio_mask = 0,
268         },
269         [41] = {
270                 .mask   = IPIC_SIMSR_H,
271                 .prio   = IPIC_SIPRR_B,
272                 .force  = IPIC_SIFCR_H,
273                 .bit    = 9,
274                 .prio_mask = 1,
275         },
276         [42] = {
277                 .mask   = IPIC_SIMSR_H,
278                 .prio   = IPIC_SIPRR_B,
279                 .force  = IPIC_SIFCR_H,
280                 .bit    = 10,
281                 .prio_mask = 2,
282         },
283         [43] = {
284                 .mask   = IPIC_SIMSR_H,
285                 .prio   = IPIC_SIPRR_B,
286                 .force  = IPIC_SIFCR_H,
287                 .bit    = 11,
288                 .prio_mask = 3,
289         },
290         [44] = {
291                 .mask   = IPIC_SIMSR_H,
292                 .prio   = IPIC_SIPRR_B,
293                 .force  = IPIC_SIFCR_H,
294                 .bit    = 12,
295                 .prio_mask = 4,
296         },
297         [45] = {
298                 .mask   = IPIC_SIMSR_H,
299                 .prio   = IPIC_SIPRR_B,
300                 .force  = IPIC_SIFCR_H,
301                 .bit    = 13,
302                 .prio_mask = 5,
303         },
304         [46] = {
305                 .mask   = IPIC_SIMSR_H,
306                 .prio   = IPIC_SIPRR_B,
307                 .force  = IPIC_SIFCR_H,
308                 .bit    = 14,
309                 .prio_mask = 6,
310         },
311         [47] = {
312                 .mask   = IPIC_SIMSR_H,
313                 .prio   = IPIC_SIPRR_B,
314                 .force  = IPIC_SIFCR_H,
315                 .bit    = 15,
316                 .prio_mask = 7,
317         },
318         [48] = {
319                 .mask   = IPIC_SEMSR,
320                 .prio   = IPIC_SMPRR_A,
321                 .force  = IPIC_SEFCR,
322                 .bit    = 0,
323                 .prio_mask = 4,
324         },
325         [64] = {
326                 .mask   = IPIC_SIMSR_L,
327                 .prio   = IPIC_SMPRR_A,
328                 .force  = IPIC_SIFCR_L,
329                 .bit    = 0,
330                 .prio_mask = 0,
331         },
332         [65] = {
333                 .mask   = IPIC_SIMSR_L,
334                 .prio   = IPIC_SMPRR_A,
335                 .force  = IPIC_SIFCR_L,
336                 .bit    = 1,
337                 .prio_mask = 1,
338         },
339         [66] = {
340                 .mask   = IPIC_SIMSR_L,
341                 .prio   = IPIC_SMPRR_A,
342                 .force  = IPIC_SIFCR_L,
343                 .bit    = 2,
344                 .prio_mask = 2,
345         },
346         [67] = {
347                 .mask   = IPIC_SIMSR_L,
348                 .prio   = IPIC_SMPRR_A,
349                 .force  = IPIC_SIFCR_L,
350                 .bit    = 3,
351                 .prio_mask = 3,
352         },
353         [68] = {
354                 .mask   = IPIC_SIMSR_L,
355                 .prio   = IPIC_SMPRR_B,
356                 .force  = IPIC_SIFCR_L,
357                 .bit    = 4,
358                 .prio_mask = 0,
359         },
360         [69] = {
361                 .mask   = IPIC_SIMSR_L,
362                 .prio   = IPIC_SMPRR_B,
363                 .force  = IPIC_SIFCR_L,
364                 .bit    = 5,
365                 .prio_mask = 1,
366         },
367         [70] = {
368                 .mask   = IPIC_SIMSR_L,
369                 .prio   = IPIC_SMPRR_B,
370                 .force  = IPIC_SIFCR_L,
371                 .bit    = 6,
372                 .prio_mask = 2,
373         },
374         [71] = {
375                 .mask   = IPIC_SIMSR_L,
376                 .prio   = IPIC_SMPRR_B,
377                 .force  = IPIC_SIFCR_L,
378                 .bit    = 7,
379                 .prio_mask = 3,
380         },
381         [72] = {
382                 .mask   = IPIC_SIMSR_L,
383                 .prio   = 0,
384                 .force  = IPIC_SIFCR_L,
385                 .bit    = 8,
386         },
387         [73] = {
388                 .mask   = IPIC_SIMSR_L,
389                 .prio   = 0,
390                 .force  = IPIC_SIFCR_L,
391                 .bit    = 9,
392         },
393         [74] = {
394                 .mask   = IPIC_SIMSR_L,
395                 .prio   = 0,
396                 .force  = IPIC_SIFCR_L,
397                 .bit    = 10,
398         },
399         [75] = {
400                 .mask   = IPIC_SIMSR_L,
401                 .prio   = 0,
402                 .force  = IPIC_SIFCR_L,
403                 .bit    = 11,
404         },
405         [76] = {
406                 .mask   = IPIC_SIMSR_L,
407                 .prio   = 0,
408                 .force  = IPIC_SIFCR_L,
409                 .bit    = 12,
410         },
411         [77] = {
412                 .mask   = IPIC_SIMSR_L,
413                 .prio   = 0,
414                 .force  = IPIC_SIFCR_L,
415                 .bit    = 13,
416         },
417         [78] = {
418                 .mask   = IPIC_SIMSR_L,
419                 .prio   = 0,
420                 .force  = IPIC_SIFCR_L,
421                 .bit    = 14,
422         },
423         [79] = {
424                 .mask   = IPIC_SIMSR_L,
425                 .prio   = 0,
426                 .force  = IPIC_SIFCR_L,
427                 .bit    = 15,
428         },
429         [80] = {
430                 .mask   = IPIC_SIMSR_L,
431                 .prio   = 0,
432                 .force  = IPIC_SIFCR_L,
433                 .bit    = 16,
434         },
435         [81] = {
436                 .mask   = IPIC_SIMSR_L,
437                 .prio   = 0,
438                 .force  = IPIC_SIFCR_L,
439                 .bit    = 17,
440         },
441         [82] = {
442                 .mask   = IPIC_SIMSR_L,
443                 .prio   = 0,
444                 .force  = IPIC_SIFCR_L,
445                 .bit    = 18,
446         },
447         [83] = {
448                 .mask   = IPIC_SIMSR_L,
449                 .prio   = 0,
450                 .force  = IPIC_SIFCR_L,
451                 .bit    = 19,
452         },
453         [84] = {
454                 .mask   = IPIC_SIMSR_L,
455                 .prio   = 0,
456                 .force  = IPIC_SIFCR_L,
457                 .bit    = 20,
458         },
459         [85] = {
460                 .mask   = IPIC_SIMSR_L,
461                 .prio   = 0,
462                 .force  = IPIC_SIFCR_L,
463                 .bit    = 21,
464         },
465         [86] = {
466                 .mask   = IPIC_SIMSR_L,
467                 .prio   = 0,
468                 .force  = IPIC_SIFCR_L,
469                 .bit    = 22,
470         },
471         [87] = {
472                 .mask   = IPIC_SIMSR_L,
473                 .prio   = 0,
474                 .force  = IPIC_SIFCR_L,
475                 .bit    = 23,
476         },
477         [88] = {
478                 .mask   = IPIC_SIMSR_L,
479                 .prio   = 0,
480                 .force  = IPIC_SIFCR_L,
481                 .bit    = 24,
482         },
483         [89] = {
484                 .mask   = IPIC_SIMSR_L,
485                 .prio   = 0,
486                 .force  = IPIC_SIFCR_L,
487                 .bit    = 25,
488         },
489         [90] = {
490                 .mask   = IPIC_SIMSR_L,
491                 .prio   = 0,
492                 .force  = IPIC_SIFCR_L,
493                 .bit    = 26,
494         },
495         [91] = {
496                 .mask   = IPIC_SIMSR_L,
497                 .prio   = 0,
498                 .force  = IPIC_SIFCR_L,
499                 .bit    = 27,
500         },
501         [94] = {
502                 .mask   = IPIC_SIMSR_L,
503                 .prio   = 0,
504                 .force  = IPIC_SIFCR_L,
505                 .bit    = 30,
506         },
507 };
508
509 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
510 {
511         return in_be32(base + (reg >> 2));
512 }
513
514 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
515 {
516         out_be32(base + (reg >> 2), value);
517 }
518
519 static inline struct ipic * ipic_from_irq(unsigned int virq)
520 {
521         return primary_ipic;
522 }
523
524 #define ipic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
525
526 static void ipic_unmask_irq(unsigned int virq)
527 {
528         struct ipic *ipic = ipic_from_irq(virq);
529         unsigned int src = ipic_irq_to_hw(virq);
530         unsigned long flags;
531         u32 temp;
532
533         spin_lock_irqsave(&ipic_lock, flags);
534
535         temp = ipic_read(ipic->regs, ipic_info[src].mask);
536         temp |= (1 << (31 - ipic_info[src].bit));
537         ipic_write(ipic->regs, ipic_info[src].mask, temp);
538
539         spin_unlock_irqrestore(&ipic_lock, flags);
540 }
541
542 static void ipic_mask_irq(unsigned int virq)
543 {
544         struct ipic *ipic = ipic_from_irq(virq);
545         unsigned int src = ipic_irq_to_hw(virq);
546         unsigned long flags;
547         u32 temp;
548
549         spin_lock_irqsave(&ipic_lock, flags);
550
551         temp = ipic_read(ipic->regs, ipic_info[src].mask);
552         temp &= ~(1 << (31 - ipic_info[src].bit));
553         ipic_write(ipic->regs, ipic_info[src].mask, temp);
554
555         /* mb() can't guarantee that masking is finished.  But it does finish
556          * for nearly all cases. */
557         mb();
558
559         spin_unlock_irqrestore(&ipic_lock, flags);
560 }
561
562 static void ipic_ack_irq(unsigned int virq)
563 {
564         struct ipic *ipic = ipic_from_irq(virq);
565         unsigned int src = ipic_irq_to_hw(virq);
566         unsigned long flags;
567         u32 temp;
568
569         spin_lock_irqsave(&ipic_lock, flags);
570
571         temp = ipic_read(ipic->regs, ipic_info[src].ack);
572         temp |= (1 << (31 - ipic_info[src].bit));
573         ipic_write(ipic->regs, ipic_info[src].ack, temp);
574
575         /* mb() can't guarantee that ack is finished.  But it does finish
576          * for nearly all cases. */
577         mb();
578
579         spin_unlock_irqrestore(&ipic_lock, flags);
580 }
581
582 static void ipic_mask_irq_and_ack(unsigned int virq)
583 {
584         struct ipic *ipic = ipic_from_irq(virq);
585         unsigned int src = ipic_irq_to_hw(virq);
586         unsigned long flags;
587         u32 temp;
588
589         spin_lock_irqsave(&ipic_lock, flags);
590
591         temp = ipic_read(ipic->regs, ipic_info[src].mask);
592         temp &= ~(1 << (31 - ipic_info[src].bit));
593         ipic_write(ipic->regs, ipic_info[src].mask, temp);
594
595         temp = ipic_read(ipic->regs, ipic_info[src].ack);
596         temp |= (1 << (31 - ipic_info[src].bit));
597         ipic_write(ipic->regs, ipic_info[src].ack, temp);
598
599         /* mb() can't guarantee that ack is finished.  But it does finish
600          * for nearly all cases. */
601         mb();
602
603         spin_unlock_irqrestore(&ipic_lock, flags);
604 }
605
606 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
607 {
608         struct ipic *ipic = ipic_from_irq(virq);
609         unsigned int src = ipic_irq_to_hw(virq);
610         struct irq_desc *desc = get_irq_desc(virq);
611         unsigned int vold, vnew, edibit;
612
613         if (flow_type == IRQ_TYPE_NONE)
614                 flow_type = IRQ_TYPE_LEVEL_LOW;
615
616         /* ipic supports only low assertion and high-to-low change senses
617          */
618         if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
619                 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
620                         flow_type);
621                 return -EINVAL;
622         }
623         /* ipic supports only edge mode on external interrupts */
624         if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
625                 printk(KERN_ERR "ipic: edge sense not supported on internal "
626                                 "interrupts\n");
627                 return -EINVAL;
628         }
629
630         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
631         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
632         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
633                 desc->status |= IRQ_LEVEL;
634                 desc->handle_irq = handle_level_irq;
635                 desc->chip = &ipic_level_irq_chip;
636         } else {
637                 desc->handle_irq = handle_edge_irq;
638                 desc->chip = &ipic_edge_irq_chip;
639         }
640
641         /* only EXT IRQ senses are programmable on ipic
642          * internal IRQ senses are LEVEL_LOW
643          */
644         if (src == IPIC_IRQ_EXT0)
645                 edibit = 15;
646         else
647                 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
648                         edibit = (14 - (src - IPIC_IRQ_EXT1));
649                 else
650                         return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
651
652         vold = ipic_read(ipic->regs, IPIC_SECNR);
653         if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
654                 vnew = vold | (1 << edibit);
655         } else {
656                 vnew = vold & ~(1 << edibit);
657         }
658         if (vold != vnew)
659                 ipic_write(ipic->regs, IPIC_SECNR, vnew);
660         return 0;
661 }
662
663 /* level interrupts and edge interrupts have different ack operations */
664 static struct irq_chip ipic_level_irq_chip = {
665         .typename       = " IPIC  ",
666         .unmask         = ipic_unmask_irq,
667         .mask           = ipic_mask_irq,
668         .mask_ack       = ipic_mask_irq,
669         .set_type       = ipic_set_irq_type,
670 };
671
672 static struct irq_chip ipic_edge_irq_chip = {
673         .typename       = " IPIC  ",
674         .unmask         = ipic_unmask_irq,
675         .mask           = ipic_mask_irq,
676         .mask_ack       = ipic_mask_irq_and_ack,
677         .ack            = ipic_ack_irq,
678         .set_type       = ipic_set_irq_type,
679 };
680
681 static int ipic_host_match(struct irq_host *h, struct device_node *node)
682 {
683         /* Exact match, unless ipic node is NULL */
684         return h->of_node == NULL || h->of_node == node;
685 }
686
687 static int ipic_host_map(struct irq_host *h, unsigned int virq,
688                          irq_hw_number_t hw)
689 {
690         struct ipic *ipic = h->host_data;
691
692         set_irq_chip_data(virq, ipic);
693         set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
694
695         /* Set default irq type */
696         set_irq_type(virq, IRQ_TYPE_NONE);
697
698         return 0;
699 }
700
701 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
702                            u32 *intspec, unsigned int intsize,
703                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
704
705 {
706         /* interrupt sense values coming from the device tree equal either
707          * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
708          */
709         *out_hwirq = intspec[0];
710         if (intsize > 1)
711                 *out_flags = intspec[1];
712         else
713                 *out_flags = IRQ_TYPE_NONE;
714         return 0;
715 }
716
717 static struct irq_host_ops ipic_host_ops = {
718         .match  = ipic_host_match,
719         .map    = ipic_host_map,
720         .xlate  = ipic_host_xlate,
721 };
722
723 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
724 {
725         struct ipic     *ipic;
726         struct resource res;
727         u32 temp = 0, ret;
728
729         ret = of_address_to_resource(node, 0, &res);
730         if (ret)
731                 return NULL;
732
733         ipic = alloc_bootmem(sizeof(struct ipic));
734         if (ipic == NULL)
735                 return NULL;
736
737         memset(ipic, 0, sizeof(struct ipic));
738
739         ipic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
740                                        NR_IPIC_INTS,
741                                        &ipic_host_ops, 0);
742         if (ipic->irqhost == NULL)
743                 return NULL;
744
745         ipic->regs = ioremap(res.start, res.end - res.start + 1);
746
747         ipic->irqhost->host_data = ipic;
748
749         /* init hw */
750         ipic_write(ipic->regs, IPIC_SICNR, 0x0);
751
752         /* default priority scheme is grouped. If spread mode is required
753          * configure SICFR accordingly */
754         if (flags & IPIC_SPREADMODE_GRP_A)
755                 temp |= SICFR_IPSA;
756         if (flags & IPIC_SPREADMODE_GRP_B)
757                 temp |= SICFR_IPSB;
758         if (flags & IPIC_SPREADMODE_GRP_C)
759                 temp |= SICFR_IPSC;
760         if (flags & IPIC_SPREADMODE_GRP_D)
761                 temp |= SICFR_IPSD;
762         if (flags & IPIC_SPREADMODE_MIX_A)
763                 temp |= SICFR_MPSA;
764         if (flags & IPIC_SPREADMODE_MIX_B)
765                 temp |= SICFR_MPSB;
766
767         ipic_write(ipic->regs, IPIC_SICFR, temp);
768
769         /* handle MCP route */
770         temp = 0;
771         if (flags & IPIC_DISABLE_MCP_OUT)
772                 temp = SERCR_MCPR;
773         ipic_write(ipic->regs, IPIC_SERCR, temp);
774
775         /* handle routing of IRQ0 to MCP */
776         temp = ipic_read(ipic->regs, IPIC_SEMSR);
777
778         if (flags & IPIC_IRQ0_MCP)
779                 temp |= SEMSR_SIRQ0;
780         else
781                 temp &= ~SEMSR_SIRQ0;
782
783         ipic_write(ipic->regs, IPIC_SEMSR, temp);
784
785         primary_ipic = ipic;
786         irq_set_default_host(primary_ipic->irqhost);
787
788         printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
789                         primary_ipic->regs);
790
791         return ipic;
792 }
793
794 int ipic_set_priority(unsigned int virq, unsigned int priority)
795 {
796         struct ipic *ipic = ipic_from_irq(virq);
797         unsigned int src = ipic_irq_to_hw(virq);
798         u32 temp;
799
800         if (priority > 7)
801                 return -EINVAL;
802         if (src > 127)
803                 return -EINVAL;
804         if (ipic_info[src].prio == 0)
805                 return -EINVAL;
806
807         temp = ipic_read(ipic->regs, ipic_info[src].prio);
808
809         if (priority < 4) {
810                 temp &= ~(0x7 << (20 + (3 - priority) * 3));
811                 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
812         } else {
813                 temp &= ~(0x7 << (4 + (7 - priority) * 3));
814                 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
815         }
816
817         ipic_write(ipic->regs, ipic_info[src].prio, temp);
818
819         return 0;
820 }
821
822 void ipic_set_highest_priority(unsigned int virq)
823 {
824         struct ipic *ipic = ipic_from_irq(virq);
825         unsigned int src = ipic_irq_to_hw(virq);
826         u32 temp;
827
828         temp = ipic_read(ipic->regs, IPIC_SICFR);
829
830         /* clear and set HPI */
831         temp &= 0x7f000000;
832         temp |= (src & 0x7f) << 24;
833
834         ipic_write(ipic->regs, IPIC_SICFR, temp);
835 }
836
837 void ipic_set_default_priority(void)
838 {
839         ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
840         ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
841         ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
842         ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
843         ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
844         ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
845 }
846
847 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
848 {
849         struct ipic *ipic = primary_ipic;
850         u32 temp;
851
852         temp = ipic_read(ipic->regs, IPIC_SERMR);
853         temp |= (1 << (31 - mcp_irq));
854         ipic_write(ipic->regs, IPIC_SERMR, temp);
855 }
856
857 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
858 {
859         struct ipic *ipic = primary_ipic;
860         u32 temp;
861
862         temp = ipic_read(ipic->regs, IPIC_SERMR);
863         temp &= (1 << (31 - mcp_irq));
864         ipic_write(ipic->regs, IPIC_SERMR, temp);
865 }
866
867 u32 ipic_get_mcp_status(void)
868 {
869         return ipic_read(primary_ipic->regs, IPIC_SERMR);
870 }
871
872 void ipic_clear_mcp_status(u32 mask)
873 {
874         ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
875 }
876
877 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
878 unsigned int ipic_get_irq(void)
879 {
880         int irq;
881
882         BUG_ON(primary_ipic == NULL);
883
884 #define IPIC_SIVCR_VECTOR_MASK  0x7f
885         irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
886
887         if (irq == 0)    /* 0 --> no irq is pending */
888                 return NO_IRQ;
889
890         return irq_linear_revmap(primary_ipic->irqhost, irq);
891 }
892
893 #ifdef CONFIG_PM
894 static struct {
895         u32 sicfr;
896         u32 siprr[2];
897         u32 simsr[2];
898         u32 sicnr;
899         u32 smprr[2];
900         u32 semsr;
901         u32 secnr;
902         u32 sermr;
903         u32 sercr;
904 } ipic_saved_state;
905
906 static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
907 {
908         struct ipic *ipic = primary_ipic;
909
910         ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
911         ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
912         ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
913         ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
914         ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
915         ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
916         ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
917         ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
918         ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
919         ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
920         ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
921         ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
922
923         if (fsl_deep_sleep()) {
924                 /* In deep sleep, make sure there can be no
925                  * pending interrupts, as this can cause
926                  * problems on 831x.
927                  */
928                 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
929                 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
930                 ipic_write(ipic->regs, IPIC_SEMSR, 0);
931                 ipic_write(ipic->regs, IPIC_SERMR, 0);
932         }
933
934         return 0;
935 }
936
937 static int ipic_resume(struct sys_device *sdev)
938 {
939         struct ipic *ipic = primary_ipic;
940
941         ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
942         ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
943         ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
944         ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
945         ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
946         ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
947         ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
948         ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
949         ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
950         ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
951         ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
952         ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
953
954         return 0;
955 }
956 #else
957 #define ipic_suspend NULL
958 #define ipic_resume NULL
959 #endif
960
961 static struct sysdev_class ipic_sysclass = {
962         .name = "ipic",
963         .suspend = ipic_suspend,
964         .resume = ipic_resume,
965 };
966
967 static struct sys_device device_ipic = {
968         .id             = 0,
969         .cls            = &ipic_sysclass,
970 };
971
972 static int __init init_ipic_sysfs(void)
973 {
974         int rc;
975
976         if (!primary_ipic || !primary_ipic->regs)
977                 return -ENODEV;
978         printk(KERN_DEBUG "Registering ipic with sysfs...\n");
979
980         rc = sysdev_class_register(&ipic_sysclass);
981         if (rc) {
982                 printk(KERN_ERR "Failed registering ipic sys class\n");
983                 return -ENODEV;
984         }
985         rc = sysdev_register(&device_ipic);
986         if (rc) {
987                 printk(KERN_ERR "Failed registering ipic sys device\n");
988                 return -ENODEV;
989         }
990         return 0;
991 }
992
993 subsys_initcall(init_ipic_sysfs);