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   1 /*
   2  * arch/arm/mach-kirkwood/addr-map.c
   3  *
   4  * Address map functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/mbus.h>
  14 #include <linux/io.h>
  15 #include <mach/hardware.h>
  16 #include "common.h"
  17
  18 /*
  19  * Generic Address Decode Windows bit settings
  20  */
  21 #define TARGET_DDR              0
  22 #define TARGET_DEV_BUS          1
  23 #define TARGET_PCIE             4
  24 #define ATTR_DEV_SPI_ROM        0x1e
  25 #define ATTR_DEV_BOOT           0x1d
  26 #define ATTR_DEV_NAND           0x2f
  27 #define ATTR_DEV_CS3            0x37
  28 #define ATTR_DEV_CS2            0x3b
  29 #define ATTR_DEV_CS1            0x3d
  30 #define ATTR_DEV_CS0            0x3e
  31 #define ATTR_PCIE_IO            0xe0
  32 #define ATTR_PCIE_MEM           0xe8
  33
  34 /*
  35  * Helpers to get DDR bank info
  36  */
  37 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  38 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  39
  40 /*
  41  * CPU Address Decode Windows registers
  42  */
  43 #define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
  44 #define WIN_CTRL_OFF            0x0000
  45 #define WIN_BASE_OFF            0x0004
  46 #define WIN_REMAP_LO_OFF        0x0008
  47 #define WIN_REMAP_HI_OFF        0x000c
  48
  49
  50 struct mbus_dram_target_info kirkwood_mbus_dram_info;
  51 static int __initdata win_alloc_count;
  52
  53 static int __init cpu_win_can_remap(int win)
  54 {
  55         if (win < 4)
  56                 return 1;
  57
  58         return 0;
  59 }
  60
  61 static void __init setup_cpu_win(int win, u32 base, u32 size,
  62                                  u8 target, u8 attr, int remap)
  63 {
  64         void __iomem *addr = (void __iomem *)WIN_OFF(win);
  65         u32 ctrl;
  66
  67         base &= 0xffff0000;
  68         ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
  69
  70         writel(base, addr + WIN_BASE_OFF);
  71         writel(ctrl, addr + WIN_CTRL_OFF);
  72         if (cpu_win_can_remap(win)) {
  73                 if (remap < 0)
  74                         remap = base;
  75
  76                 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
  77                 writel(0, addr + WIN_REMAP_HI_OFF);
  78         }
  79 }
  80
  81 void __init kirkwood_setup_cpu_mbus(void)
  82 {
  83         void __iomem *addr;
  84         int i;
  85         int cs;
  86
  87         /*
  88          * First, disable and clear windows.
  89          */
  90         for (i = 0; i < 8; i++) {
  91                 addr = (void __iomem *)WIN_OFF(i);
  92
  93                 writel(0, addr + WIN_BASE_OFF);
  94                 writel(0, addr + WIN_CTRL_OFF);
  95                 if (cpu_win_can_remap(i)) {
  96                         writel(0, addr + WIN_REMAP_LO_OFF);
  97                         writel(0, addr + WIN_REMAP_HI_OFF);
  98                 }
  99         }
 100
 101         /*
 102          * Setup windows for PCIe IO+MEM space.
 103          */
 104         setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
 105                       TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 106         setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 107                       TARGET_PCIE, ATTR_PCIE_MEM, -1);
 108
 109         /*
 110          * Setup window for NAND controller.
 111          */
 112         setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 113                       TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 114
 115         win_alloc_count = 3;
 116
 117         /*
 118          * Setup MBUS dram target info.
 119          */
 120         kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 121
 122         addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
 123
 124         for (i = 0, cs = 0; i < 4; i++) {
 125                 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
 126                 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
 127
 128                 /*
 129                  * Chip select enabled?
 130                  */
 131                 if (size & 1) {
 132                         struct mbus_dram_window *w;
 133
 134                         w = &kirkwood_mbus_dram_info.cs[cs++];
 135                         w->cs_index = i;
 136                         w->mbus_attr = 0xf & ~(1 << i);
 137                         w->base = base & 0xffff0000;
 138                         w->size = (size | 0x0000ffff) + 1;
 139                 }
 140         }
 141         kirkwood_mbus_dram_info.num_cs = cs;
 142 }
 143
 144 void __init kirkwood_setup_sram_win(u32 base, u32 size)
 145 {
 146         setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1);
 147 }