1 /* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Eric Anholt <anholt@FreeBSD.org>
38 irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
40 drm_device_t *dev = (drm_device_t *) arg;
41 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
45 status = MGA_READ(MGA_STATUS);
47 /* VBLANK interrupt */
48 if (status & MGA_VLINEPEN) {
49 MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
50 atomic_inc(&dev->vbl_received);
51 DRM_WAKEUP(&dev->vbl_queue);
52 drm_vbl_send_signals(dev);
56 /* SOFTRAP interrupt */
57 if (status & MGA_SOFTRAPEN) {
58 const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
59 const u32 prim_end = MGA_READ(MGA_PRIMEND);
61 MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
63 /* In addition to clearing the interrupt-pending bit, we
64 * have to write to MGA_PRIMEND to re-start the DMA operation.
66 if ((prim_start & ~0x03) != (prim_end & ~0x03)) {
67 MGA_WRITE(MGA_PRIMEND, prim_end);
70 atomic_inc(&dev_priv->last_fence_retired);
71 DRM_WAKEUP(&dev_priv->fence_queue);
81 int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
83 unsigned int cur_vblank;
86 /* Assume that the user has missed the current sequence number
87 * by about a day rather than she wants to wait for years
88 * using vertical blanks...
90 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
91 (((cur_vblank = atomic_read(&dev->vbl_received))
92 - *sequence) <= (1 << 23)));
94 *sequence = cur_vblank;
99 int mga_driver_fence_wait(drm_device_t * dev, unsigned int *sequence)
101 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
102 unsigned int cur_fence;
105 /* Assume that the user has missed the current sequence number
106 * by about a day rather than she wants to wait for years
109 DRM_WAIT_ON(ret, dev_priv->fence_queue, 3 * DRM_HZ,
110 (((cur_fence = atomic_read(&dev_priv->last_fence_retired))
111 - *sequence) <= (1 << 23)));
113 *sequence = cur_fence;
118 void mga_driver_irq_preinstall(drm_device_t * dev)
120 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
122 /* Disable *all* interrupts */
123 MGA_WRITE(MGA_IEN, 0);
124 /* Clear bits if they're already high */
125 MGA_WRITE(MGA_ICLEAR, ~0);
128 void mga_driver_irq_postinstall(drm_device_t * dev)
130 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
132 DRM_INIT_WAITQUEUE(&dev_priv->fence_queue);
134 /* Turn on vertical blank interrupt and soft trap interrupt. */
135 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
138 void mga_driver_irq_uninstall(drm_device_t * dev)
140 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
144 /* Disable *all* interrupts */
145 MGA_WRITE(MGA_IEN, 0);
147 dev->irq_enabled = 0;