1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
15 1) Entry point for arch/powerpc
18 II - The DT block format
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
33 d) the /memory node(s)
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
45 b) Interrupt controllers
46 c) CFI or JEDEC memory-mapped NOR flash
47 d) 4xx/Axon EMAC ethernet nodes
49 f) USB EHCI controllers
51 VII - Marvell Discovery mv64[345]6x System Controller chips
52 1) The /system-controller node
53 2) Child nodes of /system-controller
54 a) Marvell Discovery MDIO bus
55 b) Marvell Discovery ethernet controller
56 c) Marvell Discovery PHY nodes
57 d) Marvell Discovery SDMA nodes
58 e) Marvell Discovery BRG nodes
59 f) Marvell Discovery CUNIT nodes
60 g) Marvell Discovery MPSCROUTING nodes
61 h) Marvell Discovery MPSCINTR nodes
62 i) Marvell Discovery MPSC nodes
63 j) Marvell Discovery Watch Dog Timer nodes
64 k) Marvell Discovery I2C nodes
65 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
66 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
67 n) Marvell Discovery GPP (General Purpose Pins) nodes
68 o) Marvell Discovery PCI host bridge node
69 p) Marvell Discovery CPU Error nodes
70 q) Marvell Discovery SRAM Controller nodes
71 r) Marvell Discovery PCI Error Handler nodes
72 s) Marvell Discovery Memory Controller nodes
74 VIII - Specifying interrupt information for devices
75 1) interrupts property
76 2) interrupt-parent property
77 3) OpenPIC Interrupt Controllers
78 4) ISA Interrupt Controllers
80 IX - Specifying GPIO information for devices
82 2) gpio-controller nodes
84 X - Specifying device power management information (sleep property)
86 Appendix A - Sample SOC node for MPC8540
92 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
94 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
95 clarifies the fact that a lot of things are
96 optional, the kernel only requires a very
97 small device tree, though it is encouraged
98 to provide an as complete one as possible.
100 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
102 - Define version 3 and new format version 16
103 for the DT block (version 16 needs kernel
104 patches, will be fwd separately).
105 String block now has a size, and full path
106 is replaced by unit name for more
108 linux,phandle is made optional, only nodes
109 that are referenced by other nodes need it.
110 "name" property is now automatically
111 deduced from the unit name
113 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
114 OF_DT_END_NODE in structure definition.
115 - Change version 16 format to always align
116 property data to 4 bytes. Since tokens are
117 already aligned, that means no specific
118 required alignment between property size
119 and property data. The old style variable
120 alignment would make it impossible to do
121 "simple" insertion of properties using
122 memmove (thanks Milton for
123 noticing). Updated kernel patch as well
124 - Correct a few more alignment constraints
125 - Add a chapter about the device-tree
126 compiler and the textural representation of
127 the tree that can be "compiled" by dtc.
129 November 21, 2005: Rev 0.5
130 - Additions/generalizations for 32-bit
131 - Changed to reflect the new arch/powerpc
137 - Add some definitions of interrupt tree (simple/complex)
138 - Add some definitions for PCI host bridges
139 - Add some common address format examples
140 - Add definitions for standard properties and "compatible"
141 names for cells that are not already defined by the existing
143 - Compare FSL SOC use of PCI to standard and make sure no new
144 node definition required.
145 - Add more information about node definitions for SOC devices
146 that currently have no standard, like the FSL CPM.
152 During the recent development of the Linux/ppc64 kernel, and more
153 specifically, the addition of new platform types outside of the old
154 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
155 regarding the kernel entry and bootloader <-> kernel interfaces, in
156 order to avoid the degeneration that had become the ppc32 kernel entry
157 point and the way a new platform should be added to the kernel. The
158 legacy iSeries platform breaks those rules as it predates this scheme,
159 but no new board support will be accepted in the main tree that
160 doesn't follows them properly. In addition, since the advent of the
161 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
162 platforms and 32-bit platforms which move into arch/powerpc will be
163 required to use these rules as well.
165 The main requirement that will be defined in more detail below is
166 the presence of a device-tree whose format is defined after Open
167 Firmware specification. However, in order to make life easier
168 to embedded board vendors, the kernel doesn't require the device-tree
169 to represent every device in the system and only requires some nodes
170 and properties to be present. This will be described in detail in
171 section III, but, for example, the kernel does not require you to
172 create a node for every PCI device in the system. It is a requirement
173 to have a node for PCI host bridges in order to provide interrupt
174 routing informations and memory/IO ranges, among others. It is also
175 recommended to define nodes for on chip devices and other busses that
176 don't specifically fit in an existing OF specification. This creates a
177 great flexibility in the way the kernel can then probe those and match
178 drivers to device, without having to hard code all sorts of tables. It
179 also makes it more flexible for board vendors to do minor hardware
180 upgrades without significantly impacting the kernel code or cluttering
181 it with special cases.
184 1) Entry point for arch/powerpc
185 -------------------------------
187 There is one and one single entry point to the kernel, at the start
188 of the kernel image. That entry point supports two calling
191 a) Boot from Open Firmware. If your firmware is compatible
192 with Open Firmware (IEEE 1275) or provides an OF compatible
193 client interface API (support for "interpret" callback of
194 forth words isn't required), you can enter the kernel with:
196 r5 : OF callback pointer as defined by IEEE 1275
197 bindings to powerpc. Only the 32-bit client interface
198 is currently supported
200 r3, r4 : address & length of an initrd if any or 0
202 The MMU is either on or off; the kernel will run the
203 trampoline located in arch/powerpc/kernel/prom_init.c to
204 extract the device-tree and other information from open
205 firmware and build a flattened device-tree as described
206 in b). prom_init() will then re-enter the kernel using
207 the second method. This trampoline code runs in the
208 context of the firmware, which is supposed to handle all
209 exceptions during that time.
211 b) Direct entry with a flattened device-tree block. This entry
212 point is called by a) after the OF trampoline and can also be
213 called directly by a bootloader that does not support the Open
214 Firmware client interface. It is also used by "kexec" to
215 implement "hot" booting of a new kernel from a previous
216 running one. This method is what I will describe in more
217 details in this document, as method a) is simply standard Open
218 Firmware, and thus should be implemented according to the
219 various standard documents defining it and its binding to the
220 PowerPC platform. The entry point definition then becomes:
222 r3 : physical pointer to the device-tree block
223 (defined in chapter II) in RAM
225 r4 : physical pointer to the kernel itself. This is
226 used by the assembly code to properly disable the MMU
227 in case you are entering the kernel with MMU enabled
228 and a non-1:1 mapping.
230 r5 : NULL (as to differentiate with method a)
232 Note about SMP entry: Either your firmware puts your other
233 CPUs in some sleep loop or spin loop in ROM where you can get
234 them out via a soft reset or some other means, in which case
235 you don't need to care, or you'll have to enter the kernel
236 with all CPUs. The way to do that with method b) will be
237 described in a later revision of this document.
245 Board supports (platforms) are not exclusive config options. An
246 arbitrary set of board supports can be built in a single kernel
247 image. The kernel will "know" what set of functions to use for a
248 given platform based on the content of the device-tree. Thus, you
251 a) add your platform support as a _boolean_ option in
252 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
253 PPC_PMAC and PPC_MAPLE. The later is probably a good
254 example of a board support to start from.
256 b) create your main platform file as
257 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
258 to the Makefile under the condition of your CONFIG_
259 option. This file will define a structure of type "ppc_md"
260 containing the various callbacks that the generic code will
261 use to get to your platform specific code
263 c) Add a reference to your "ppc_md" structure in the
264 "machines" table in arch/powerpc/kernel/setup_64.c if you are
267 d) request and get assigned a platform number (see PLATFORM_*
268 constants in include/asm-powerpc/processor.h
270 32-bit embedded kernels:
272 Currently, board support is essentially an exclusive config option.
273 The kernel is configured for a single platform. Part of the reason
274 for this is to keep kernels on embedded systems small and efficient;
275 part of this is due to the fact the code is already that way. In the
276 future, a kernel may support multiple platforms, but only if the
277 platforms feature the same core architecture. A single kernel build
278 cannot support both configurations with Book E and configurations
279 with classic Powerpc architectures.
281 32-bit embedded platforms that are moved into arch/powerpc using a
282 flattened device tree should adopt the merged tree practice of
283 setting ppc_md up dynamically, even though the kernel is currently
284 built with support for only a single platform at a time. This allows
285 unification of the setup code, and will make it easier to go to a
286 multiple-platform-support model in the future.
288 NOTE: I believe the above will be true once Ben's done with the merge
289 of the boot sequences.... someone speak up if this is wrong!
291 To add a 32-bit embedded platform support, follow the instructions
292 for 64-bit platforms above, with the exception that the Kconfig
293 option should be set up such that the kernel builds exclusively for
294 the platform selected. The processor type for the platform should
295 enable another config option to select the specific board
298 NOTE: If Ben doesn't merge the setup files, may need to change this to
302 I will describe later the boot process and various callbacks that
303 your platform should implement.
306 II - The DT block format
307 ========================
310 This chapter defines the actual format of the flattened device-tree
311 passed to the kernel. The actual content of it and kernel requirements
312 are described later. You can find example of code manipulating that
313 format in various places, including arch/powerpc/kernel/prom_init.c
314 which will generate a flattened device-tree from the Open Firmware
315 representation, or the fs2dt utility which is part of the kexec tools
316 which will generate one from a filesystem representation. It is
317 expected that a bootloader like uboot provides a bit more support,
318 that will be discussed later as well.
320 Note: The block has to be in main memory. It has to be accessible in
321 both real mode and virtual mode with no mapping other than main
322 memory. If you are writing a simple flash bootloader, it should copy
323 the block to RAM before passing it to the kernel.
329 The kernel is entered with r3 pointing to an area of memory that is
330 roughly described in include/asm-powerpc/prom.h by the structure
333 struct boot_param_header {
334 u32 magic; /* magic word OF_DT_HEADER */
335 u32 totalsize; /* total size of DT block */
336 u32 off_dt_struct; /* offset to structure */
337 u32 off_dt_strings; /* offset to strings */
338 u32 off_mem_rsvmap; /* offset to memory reserve map
340 u32 version; /* format version */
341 u32 last_comp_version; /* last compatible version */
343 /* version 2 fields below */
344 u32 boot_cpuid_phys; /* Which physical CPU id we're
346 /* version 3 fields below */
347 u32 size_dt_strings; /* size of the strings block */
349 /* version 17 fields below */
350 u32 size_dt_struct; /* size of the DT structure block */
353 Along with the constants:
355 /* Definitions used by the flattened device tree */
356 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
358 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
360 #define OF_DT_END_NODE 0x2 /* End node */
361 #define OF_DT_PROP 0x3 /* Property: name off,
363 #define OF_DT_END 0x9
365 All values in this header are in big endian format, the various
366 fields in this header are defined more precisely below. All
367 "offset" values are in bytes from the start of the header; that is
368 from the value of r3.
372 This is a magic value that "marks" the beginning of the
373 device-tree block header. It contains the value 0xd00dfeed and is
374 defined by the constant OF_DT_HEADER
378 This is the total size of the DT block including the header. The
379 "DT" block should enclose all data structures defined in this
380 chapter (who are pointed to by offsets in this header). That is,
381 the device-tree structure, strings, and the memory reserve map.
385 This is an offset from the beginning of the header to the start
386 of the "structure" part the device tree. (see 2) device tree)
390 This is an offset from the beginning of the header to the start
391 of the "strings" part of the device-tree
395 This is an offset from the beginning of the header to the start
396 of the reserved memory map. This map is a list of pairs of 64-
397 bit integers. Each pair is a physical address and a size. The
398 list is terminated by an entry of size 0. This map provides the
399 kernel with a list of physical memory areas that are "reserved"
400 and thus not to be used for memory allocations, especially during
401 early initialization. The kernel needs to allocate memory during
402 boot for things like un-flattening the device-tree, allocating an
403 MMU hash table, etc... Those allocations must be done in such a
404 way to avoid overriding critical things like, on Open Firmware
405 capable machines, the RTAS instance, or on some pSeries, the TCE
406 tables used for the iommu. Typically, the reserve map should
407 contain _at least_ this DT block itself (header,total_size). If
408 you are passing an initrd to the kernel, you should reserve it as
409 well. You do not need to reserve the kernel image itself. The map
410 should be 64-bit aligned.
414 This is the version of this structure. Version 1 stops
415 here. Version 2 adds an additional field boot_cpuid_phys.
416 Version 3 adds the size of the strings block, allowing the kernel
417 to reallocate it easily at boot and free up the unused flattened
418 structure after expansion. Version 16 introduces a new more
419 "compact" format for the tree itself that is however not backward
420 compatible. Version 17 adds an additional field, size_dt_struct,
421 allowing it to be reallocated or moved more easily (this is
422 particularly useful for bootloaders which need to make
423 adjustments to a device tree based on probed information). You
424 should always generate a structure of the highest version defined
425 at the time of your implementation. Currently that is version 17,
426 unless you explicitly aim at being backward compatible.
430 Last compatible version. This indicates down to what version of
431 the DT block you are backward compatible. For example, version 2
432 is backward compatible with version 1 (that is, a kernel build
433 for version 1 will be able to boot with a version 2 format). You
434 should put a 1 in this field if you generate a device tree of
435 version 1 to 3, or 16 if you generate a tree of version 16 or 17
436 using the new unit name format.
440 This field only exist on version 2 headers. It indicate which
441 physical CPU ID is calling the kernel entry point. This is used,
442 among others, by kexec. If you are on an SMP system, this value
443 should match the content of the "reg" property of the CPU node in
444 the device-tree corresponding to the CPU calling the kernel entry
445 point (see further chapters for more informations on the required
446 device-tree contents)
450 This field only exists on version 3 and later headers. It
451 gives the size of the "strings" section of the device tree (which
452 starts at the offset given by off_dt_strings).
456 This field only exists on version 17 and later headers. It gives
457 the size of the "structure" section of the device tree (which
458 starts at the offset given by off_dt_struct).
460 So the typical layout of a DT block (though the various parts don't
461 need to be in that order) looks like this (addresses go from top to
465 ------------------------------
466 r3 -> | struct boot_param_header |
467 ------------------------------
468 | (alignment gap) (*) |
469 ------------------------------
470 | memory reserve map |
471 ------------------------------
473 ------------------------------
475 | device-tree structure |
477 ------------------------------
479 ------------------------------
481 | device-tree strings |
483 -----> ------------------------------
488 (*) The alignment gaps are not necessarily present; their presence
489 and size are dependent on the various alignment requirements of
490 the individual data blocks.
493 2) Device tree generalities
494 ---------------------------
496 This device-tree itself is separated in two different blocks, a
497 structure block and a strings block. Both need to be aligned to a 4
500 First, let's quickly describe the device-tree concept before detailing
501 the storage format. This chapter does _not_ describe the detail of the
502 required types of nodes & properties for the kernel, this is done
503 later in chapter III.
505 The device-tree layout is strongly inherited from the definition of
506 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
507 nodes, each node having two or more named properties. A property can
510 It is a tree, so each node has one and only one parent except for the
511 root node who has no parent.
513 A node has 2 names. The actual node name is generally contained in a
514 property of type "name" in the node property list whose value is a
515 zero terminated string and is mandatory for version 1 to 3 of the
516 format definition (as it is in Open Firmware). Version 16 makes it
517 optional as it can generate it from the unit name defined below.
519 There is also a "unit name" that is used to differentiate nodes with
520 the same name at the same level, it is usually made of the node
521 names, the "@" sign, and a "unit address", which definition is
522 specific to the bus type the node sits on.
524 The unit name doesn't exist as a property per-se but is included in
525 the device-tree structure. It is typically used to represent "path" in
526 the device-tree. More details about the actual format of these will be
529 The kernel powerpc generic code does not make any formal use of the
530 unit address (though some board support code may do) so the only real
531 requirement here for the unit address is to ensure uniqueness of
532 the node unit name at a given level of the tree. Nodes with no notion
533 of address and no possible sibling of the same name (like /memory or
534 /cpus) may omit the unit address in the context of this specification,
535 or use the "@0" default unit address. The unit name is used to define
536 a node "full path", which is the concatenation of all parent node
537 unit names separated with "/".
539 The root node doesn't have a defined name, and isn't required to have
540 a name property either if you are using version 3 or earlier of the
541 format. It also has no unit address (no @ symbol followed by a unit
542 address). The root node unit name is thus an empty string. The full
543 path to the root node is "/".
545 Every node which actually represents an actual device (that is, a node
546 which isn't only a virtual "container" for more nodes, like "/cpus"
547 is) is also required to have a "device_type" property indicating the
550 Finally, every node that can be referenced from a property in another
551 node is required to have a "linux,phandle" property. Real open
552 firmware implementations provide a unique "phandle" value for every
553 node that the "prom_init()" trampoline code turns into
554 "linux,phandle" properties. However, this is made optional if the
555 flattened device tree is used directly. An example of a node
556 referencing another node via "phandle" is when laying out the
557 interrupt tree which will be described in a further version of this
560 This "linux, phandle" property is a 32-bit value that uniquely
561 identifies a node. You are free to use whatever values or system of
562 values, internal pointers, or whatever to generate these, the only
563 requirement is that every node for which you provide that property has
564 a unique value for it.
566 Here is an example of a simple device-tree. In this example, an "o"
567 designates a node followed by the node unit name. Properties are
568 presented with their name followed by their content. "content"
569 represents an ASCII string (zero terminated) value, while <content>
570 represents a 32-bit hexadecimal value. The various nodes in this
571 example will be discussed in a later chapter. At this point, it is
572 only meant to give you a idea of what a device-tree looks like. I have
573 purposefully kept the "name" and "linux,phandle" properties which
574 aren't necessary in order to give you a better idea of what the tree
575 looks like in practice.
578 |- name = "device-tree"
579 |- model = "MyBoardName"
580 |- compatible = "MyBoardFamilyName"
581 |- #address-cells = <2>
583 |- linux,phandle = <0>
587 | | - linux,phandle = <1>
588 | | - #address-cells = <1>
589 | | - #size-cells = <0>
592 | |- name = "PowerPC,970"
593 | |- device_type = "cpu"
595 | |- clock-frequency = <5f5e1000>
597 | |- linux,phandle = <2>
601 | |- device_type = "memory"
602 | |- reg = <00000000 00000000 00000000 20000000>
603 | |- linux,phandle = <3>
607 |- bootargs = "root=/dev/sda2"
608 |- linux,phandle = <4>
610 This tree is almost a minimal tree. It pretty much contains the
611 minimal set of required nodes and properties to boot a linux kernel;
612 that is, some basic model informations at the root, the CPUs, and the
613 physical memory layout. It also includes misc information passed
614 through /chosen, like in this example, the platform type (mandatory)
615 and the kernel command line arguments (optional).
617 The /cpus/PowerPC,970@0/64-bit property is an example of a
618 property without a value. All other properties have a value. The
619 significance of the #address-cells and #size-cells properties will be
620 explained in chapter IV which defines precisely the required nodes and
621 properties and their content.
624 3) Device tree "structure" block
626 The structure of the device tree is a linearized tree structure. The
627 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
628 ends that node definition. Child nodes are simply defined before
629 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
630 bit value. The tree has to be "finished" with a OF_DT_END token
632 Here's the basic structure of a single node:
634 * token OF_DT_BEGIN_NODE (that is 0x00000001)
635 * for version 1 to 3, this is the node full path as a zero
636 terminated string, starting with "/". For version 16 and later,
637 this is the node unit name only (or an empty string for the
639 * [align gap to next 4 bytes boundary]
641 * token OF_DT_PROP (that is 0x00000003)
642 * 32-bit value of property value size in bytes (or 0 if no
644 * 32-bit value of offset in string block of property name
645 * property value data if any
646 * [align gap to next 4 bytes boundary]
647 * [child nodes if any]
648 * token OF_DT_END_NODE (that is 0x00000002)
650 So the node content can be summarized as a start token, a full path,
651 a list of properties, a list of child nodes, and an end token. Every
652 child node is a full node structure itself as defined above.
654 NOTE: The above definition requires that all property definitions for
655 a particular node MUST precede any subnode definitions for that node.
656 Although the structure would not be ambiguous if properties and
657 subnodes were intermingled, the kernel parser requires that the
658 properties come first (up until at least 2.6.22). Any tools
659 manipulating a flattened tree must take care to preserve this
662 4) Device tree "strings" block
664 In order to save space, property names, which are generally redundant,
665 are stored separately in the "strings" block. This block is simply the
666 whole bunch of zero terminated strings for all property names
667 concatenated together. The device-tree property definitions in the
668 structure block will contain offset values from the beginning of the
672 III - Required content of the device tree
673 =========================================
675 WARNING: All "linux,*" properties defined in this document apply only
676 to a flattened device-tree. If your platform uses a real
677 implementation of Open Firmware or an implementation compatible with
678 the Open Firmware client interface, those properties will be created
679 by the trampoline code in the kernel's prom_init() file. For example,
680 that's where you'll have to add code to detect your board model and
681 set the platform number. However, when using the flattened device-tree
682 entry point, there is no prom_init() pass, and thus you have to
683 provide those properties yourself.
686 1) Note about cells and address representation
687 ----------------------------------------------
689 The general rule is documented in the various Open Firmware
690 documentations. If you choose to describe a bus with the device-tree
691 and there exist an OF bus binding, then you should follow the
692 specification. However, the kernel does not require every single
693 device or bus to be described by the device tree.
695 In general, the format of an address for a device is defined by the
696 parent bus type, based on the #address-cells and #size-cells
697 properties. Note that the parent's parent definitions of #address-cells
698 and #size-cells are not inhereted so every node with children must specify
699 them. The kernel requires the root node to have those properties defining
700 addresses format for devices directly mapped on the processor bus.
702 Those 2 properties define 'cells' for representing an address and a
703 size. A "cell" is a 32-bit number. For example, if both contain 2
704 like the example tree given above, then an address and a size are both
705 composed of 2 cells, and each is a 64-bit number (cells are
706 concatenated and expected to be in big endian format). Another example
707 is the way Apple firmware defines them, with 2 cells for an address
708 and one cell for a size. Most 32-bit implementations should define
709 #address-cells and #size-cells to 1, which represents a 32-bit value.
710 Some 32-bit processors allow for physical addresses greater than 32
711 bits; these processors should define #address-cells as 2.
713 "reg" properties are always a tuple of the type "address size" where
714 the number of cells of address and size is specified by the bus
715 #address-cells and #size-cells. When a bus supports various address
716 spaces and other flags relative to a given address allocation (like
717 prefetchable, etc...) those flags are usually added to the top level
718 bits of the physical address. For example, a PCI physical address is
719 made of 3 cells, the bottom two containing the actual address itself
720 while the top cell contains address space indication, flags, and pci
721 bus & device numbers.
723 For busses that support dynamic allocation, it's the accepted practice
724 to then not provide the address in "reg" (keep it 0) though while
725 providing a flag indicating the address is dynamically allocated, and
726 then, to provide a separate "assigned-addresses" property that
727 contains the fully allocated addresses. See the PCI OF bindings for
730 In general, a simple bus with no address space bits and no dynamic
731 allocation is preferred if it reflects your hardware, as the existing
732 kernel address parsing functions will work out of the box. If you
733 define a bus type with a more complex address format, including things
734 like address space bits, you'll have to add a bus translator to the
735 prom_parse.c file of the recent kernels for your bus type.
737 The "reg" property only defines addresses and sizes (if #size-cells is
738 non-0) within a given bus. In order to translate addresses upward
739 (that is into parent bus addresses, and possibly into CPU physical
740 addresses), all busses must contain a "ranges" property. If the
741 "ranges" property is missing at a given level, it's assumed that
742 translation isn't possible, i.e., the registers are not visible on the
743 parent bus. The format of the "ranges" property for a bus is a list
746 bus address, parent bus address, size
748 "bus address" is in the format of the bus this bus node is defining,
749 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
750 address, size) defines a range of addresses for child devices. "parent
751 bus address" is in the format of the parent bus of this bus. For
752 example, for a PCI host controller, that would be a CPU address. For a
753 PCI<->ISA bridge, that would be a PCI address. It defines the base
754 address in the parent bus where the beginning of that range is mapped.
756 For a new 64-bit powerpc board, I recommend either the 2/2 format or
757 Apple's 2/1 format which is slightly more compact since sizes usually
758 fit in a single 32-bit word. New 32-bit powerpc boards should use a
759 1/1 format, unless the processor supports physical addresses greater
760 than 32-bits, in which case a 2/1 format is recommended.
762 Alternatively, the "ranges" property may be empty, indicating that the
763 registers are visible on the parent bus using an identity mapping
764 translation. In other words, the parent bus address space is the same
765 as the child bus address space.
767 2) Note about "compatible" properties
768 -------------------------------------
770 These properties are optional, but recommended in devices and the root
771 node. The format of a "compatible" property is a list of concatenated
772 zero terminated strings. They allow a device to express its
773 compatibility with a family of similar devices, in some cases,
774 allowing a single driver to match against several devices regardless
775 of their actual names.
777 3) Note about "name" properties
778 -------------------------------
780 While earlier users of Open Firmware like OldWorld macintoshes tended
781 to use the actual device name for the "name" property, it's nowadays
782 considered a good practice to use a name that is closer to the device
783 class (often equal to device_type). For example, nowadays, ethernet
784 controllers are named "ethernet", an additional "model" property
785 defining precisely the chip type/model, and "compatible" property
786 defining the family in case a single driver can driver more than one
787 of these chips. However, the kernel doesn't generally put any
788 restriction on the "name" property; it is simply considered good
789 practice to follow the standard and its evolutions as closely as
792 Note also that the new format version 16 makes the "name" property
793 optional. If it's absent for a node, then the node's unit name is then
794 used to reconstruct the name. That is, the part of the unit name
795 before the "@" sign is used (or the entire unit name if no "@" sign
798 4) Note about node and property names and character set
799 -------------------------------------------------------
801 While open firmware provides more flexible usage of 8859-1, this
802 specification enforces more strict rules. Nodes and properties should
803 be comprised only of ASCII characters 'a' to 'z', '0' to
804 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
805 allow uppercase characters 'A' to 'Z' (property names should be
806 lowercase. The fact that vendors like Apple don't respect this rule is
807 irrelevant here). Additionally, node and property names should always
808 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
811 The maximum number of characters for both nodes and property names
812 is 31. In the case of node names, this is only the leftmost part of
813 a unit name (the pure "name" property), it doesn't include the unit
814 address which can extend beyond that limit.
817 5) Required nodes and properties
818 --------------------------------
819 These are all that are currently required. However, it is strongly
820 recommended that you expose PCI host bridges as documented in the
821 PCI binding to open firmware, and your interrupt tree as documented
822 in OF interrupt tree specification.
826 The root node requires some properties to be present:
828 - model : this is your board name/model
829 - #address-cells : address representation for "root" devices
830 - #size-cells: the size representation for "root" devices
831 - device_type : This property shouldn't be necessary. However, if
832 you decide to create a device_type for your root node, make sure it
833 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
834 one for 64-bit, or a CHRP-type machine for 32-bit as this will
835 matched by the kernel this way.
837 Additionally, some recommended properties are:
839 - compatible : the board "family" generally finds its way here,
840 for example, if you have 2 board models with a similar layout,
841 that typically get driven by the same platform code in the
842 kernel, you would use a different "model" property but put a
843 value in "compatible". The kernel doesn't directly use that
844 value but it is generally useful.
846 The root node is also generally where you add additional properties
847 specific to your board like the serial number if any, that sort of
848 thing. It is recommended that if you add any "custom" property whose
849 name may clash with standard defined ones, you prefix them with your
850 vendor name and a comma.
854 This node is the parent of all individual CPU nodes. It doesn't
855 have any specific requirements, though it's generally good practice
858 #address-cells = <00000001>
859 #size-cells = <00000000>
861 This defines that the "address" for a CPU is a single cell, and has
862 no meaningful size. This is not necessary but the kernel will assume
863 that format when reading the "reg" properties of a CPU node, see
868 So under /cpus, you are supposed to create a node for every CPU on
869 the machine. There is no specific restriction on the name of the
870 CPU, though It's common practice to call it PowerPC,<name>. For
871 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
875 - device_type : has to be "cpu"
876 - reg : This is the physical CPU number, it's a single 32-bit cell
877 and is also used as-is as the unit number for constructing the
878 unit name in the full path. For example, with 2 CPUs, you would
880 /cpus/PowerPC,970FX@0
881 /cpus/PowerPC,970FX@1
882 (unit addresses do not require leading zeroes)
883 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
884 - i-cache-block-size : one cell, L1 instruction cache block size in
886 - d-cache-size : one cell, size of L1 data cache in bytes
887 - i-cache-size : one cell, size of L1 instruction cache in bytes
889 (*) The cache "block" size is the size on which the cache management
890 instructions operate. Historically, this document used the cache
891 "line" size here which is incorrect. The kernel will prefer the cache
892 block size and will fallback to cache line size for backward
895 Recommended properties:
897 - timebase-frequency : a cell indicating the frequency of the
898 timebase in Hz. This is not directly used by the generic code,
899 but you are welcome to copy/paste the pSeries code for setting
900 the kernel timebase/decrementer calibration based on this
902 - clock-frequency : a cell indicating the CPU core clock frequency
903 in Hz. A new property will be defined for 64-bit values, but if
904 your frequency is < 4Ghz, one cell is enough. Here as well as
905 for the above, the common code doesn't use that property, but
906 you are welcome to re-use the pSeries or Maple one. A future
907 kernel version might provide a common function for this.
908 - d-cache-line-size : one cell, L1 data cache line size in bytes
909 if different from the block size
910 - i-cache-line-size : one cell, L1 instruction cache line size in
911 bytes if different from the block size
913 You are welcome to add any property you find relevant to your board,
914 like some information about the mechanism used to soft-reset the
915 CPUs. For example, Apple puts the GPIO number for CPU soft reset
916 lines in there as a "soft-reset" property since they start secondary
917 CPUs by soft-resetting them.
920 d) the /memory node(s)
922 To define the physical memory layout of your board, you should
923 create one or more memory node(s). You can either create a single
924 node with all memory ranges in its reg property, or you can create
925 several nodes, as you wish. The unit address (@ part) used for the
926 full path is the address of the first range of memory defined by a
927 given node. If you use a single memory node, this will typically be
932 - device_type : has to be "memory"
933 - reg : This property contains all the physical memory ranges of
934 your board. It's a list of addresses/sizes concatenated
935 together, with the number of cells of each defined by the
936 #address-cells and #size-cells of the root node. For example,
937 with both of these properties being 2 like in the example given
938 earlier, a 970 based machine with 6Gb of RAM could typically
939 have a "reg" property here that looks like:
941 00000000 00000000 00000000 80000000
942 00000001 00000000 00000001 00000000
944 That is a range starting at 0 of 0x80000000 bytes and a range
945 starting at 0x100000000 and of 0x100000000 bytes. You can see
946 that there is no memory covering the IO hole between 2Gb and
947 4Gb. Some vendors prefer splitting those ranges into smaller
948 segments, but the kernel doesn't care.
952 This node is a bit "special". Normally, that's where open firmware
953 puts some variable environment information, like the arguments, or
954 the default input/output devices.
956 This specification makes a few of these mandatory, but also defines
957 some linux-specific properties that would be normally constructed by
958 the prom_init() trampoline when booting with an OF client interface,
959 but that you have to provide yourself when using the flattened format.
961 Recommended properties:
963 - bootargs : This zero-terminated string is passed as the kernel
965 - linux,stdout-path : This is the full path to your standard
966 console device if any. Typically, if you have serial devices on
967 your board, you may want to put the full path to the one set as
968 the default console in the firmware here, for the kernel to pick
969 it up as its own default console. If you look at the function
970 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
971 that the kernel tries to find out the default console and has
972 knowledge of various types like 8250 serial ports. You may want
973 to extend this function to add your own.
975 Note that u-boot creates and fills in the chosen node for platforms
978 (Note: a practice that is now obsolete was to include a property
979 under /chosen called interrupt-controller which had a phandle value
980 that pointed to the main interrupt controller)
982 f) the /soc<SOCname> node
984 This node is used to represent a system-on-a-chip (SOC) and must be
985 present if the processor is a SOC. The top-level soc node contains
986 information that is global to all devices on the SOC. The node name
987 should contain a unit address for the SOC, which is the base address
988 of the memory-mapped register set for the SOC. The name of an soc
989 node should start with "soc", and the remainder of the name should
990 represent the part number for the soc. For example, the MPC8540's
991 soc node would be called "soc8540".
995 - device_type : Should be "soc"
996 - ranges : Should be defined as specified in 1) to describe the
997 translation of SOC addresses for memory mapped SOC registers.
998 - bus-frequency: Contains the bus frequency for the SOC node.
999 Typically, the value of this field is filled in by the boot
1003 Recommended properties:
1005 - reg : This property defines the address and size of the
1006 memory-mapped registers that are used for the SOC node itself.
1007 It does not include the child device registers - these will be
1008 defined inside each child node. The address specified in the
1009 "reg" property should match the unit address of the SOC node.
1010 - #address-cells : Address representation for "soc" devices. The
1011 format of this field may vary depending on whether or not the
1012 device registers are memory mapped. For memory mapped
1013 registers, this field represents the number of cells needed to
1014 represent the address of the registers. For SOCs that do not
1015 use MMIO, a special address format should be defined that
1016 contains enough cells to represent the required information.
1017 See 1) above for more details on defining #address-cells.
1018 - #size-cells : Size representation for "soc" devices
1019 - #interrupt-cells : Defines the width of cells used to represent
1020 interrupts. Typically this value is <2>, which includes a
1021 32-bit number that represents the interrupt number, and a
1022 32-bit number that represents the interrupt sense and level.
1023 This field is only needed if the SOC contains an interrupt
1026 The SOC node may contain child nodes for each SOC device that the
1027 platform uses. Nodes should not be created for devices which exist
1028 on the SOC but are not used by a particular platform. See chapter VI
1029 for more information on how to specify devices that are part of a SOC.
1031 Example SOC node for the MPC8540:
1034 #address-cells = <1>;
1036 #interrupt-cells = <2>;
1037 device_type = "soc";
1038 ranges = <00000000 e0000000 00100000>
1039 reg = <e0000000 00003000>;
1040 bus-frequency = <0>;
1045 IV - "dtc", the device tree compiler
1046 ====================================
1049 dtc source code can be found at
1050 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1052 WARNING: This version is still in early development stage; the
1053 resulting device-tree "blobs" have not yet been validated with the
1054 kernel. The current generated bloc lacks a useful reserve map (it will
1055 be fixed to generate an empty one, it's up to the bootloader to fill
1056 it up) among others. The error handling needs work, bugs are lurking,
1059 dtc basically takes a device-tree in a given format and outputs a
1060 device-tree in another format. The currently supported formats are:
1065 - "dtb": "blob" format, that is a flattened device-tree block
1067 header all in a binary blob.
1068 - "dts": "source" format. This is a text file containing a
1069 "source" for a device-tree. The format is defined later in this
1071 - "fs" format. This is a representation equivalent to the
1072 output of /proc/device-tree, that is nodes are directories and
1073 properties are files
1078 - "dtb": "blob" format
1079 - "dts": "source" format
1080 - "asm": assembly language file. This is a file that can be
1081 sourced by gas to generate a device-tree "blob". That file can
1082 then simply be added to your Makefile. Additionally, the
1083 assembly file exports some symbols that can be used.
1086 The syntax of the dtc tool is
1088 dtc [-I <input-format>] [-O <output-format>]
1089 [-o output-filename] [-V output_version] input_filename
1092 The "output_version" defines what version of the "blob" format will be
1093 generated. Supported versions are 1,2,3 and 16. The default is
1094 currently version 3 but that may change in the future to version 16.
1096 Additionally, dtc performs various sanity checks on the tree, like the
1097 uniqueness of linux, phandle properties, validity of strings, etc...
1099 The format of the .dts "source" file is "C" like, supports C and C++
1105 The above is the "device-tree" definition. It's the only statement
1106 supported currently at the toplevel.
1109 property1 = "string_value"; /* define a property containing a 0
1113 property2 = <1234abcd>; /* define a property containing a
1114 * numerical 32-bit value (hexadecimal)
1117 property3 = <12345678 12345678 deadbeef>;
1118 /* define a property containing 3
1119 * numerical 32-bit values (cells) in
1122 property4 = [0a 0b 0c 0d de ea ad be ef];
1123 /* define a property whose content is
1124 * an arbitrary array of bytes
1127 childnode@addresss { /* define a child node named "childnode"
1128 * whose unit name is "childnode at
1132 childprop = "hello\n"; /* define a property "childprop" of
1133 * childnode (in this case, a string)
1138 Nodes can contain other nodes etc... thus defining the hierarchical
1139 structure of the tree.
1141 Strings support common escape sequences from C: "\n", "\t", "\r",
1142 "\(octal value)", "\x(hex value)".
1144 It is also suggested that you pipe your source file through cpp (gcc
1145 preprocessor) so you can use #include's, #define for constants, etc...
1147 Finally, various options are planned but not yet implemented, like
1148 automatic generation of phandles, labels (exported to the asm file so
1149 you can point to a property content and change it easily from whatever
1150 you link the device-tree with), label or path instead of numeric value
1151 in some cells to "point" to a node (replaced by a phandle at compile
1152 time), export of reserve map address to the asm file, ability to
1153 specify reserve map content at compile time, etc...
1155 We may provide a .h include file with common definitions of that
1156 proves useful for some properties (like building PCI properties or
1157 interrupt maps) though it may be better to add a notion of struct
1158 definitions to the compiler...
1161 V - Recommendations for a bootloader
1162 ====================================
1165 Here are some various ideas/recommendations that have been proposed
1166 while all this has been defined and implemented.
1168 - The bootloader may want to be able to use the device-tree itself
1169 and may want to manipulate it (to add/edit some properties,
1170 like physical memory size or kernel arguments). At this point, 2
1171 choices can be made. Either the bootloader works directly on the
1172 flattened format, or the bootloader has its own internal tree
1173 representation with pointers (similar to the kernel one) and
1174 re-flattens the tree when booting the kernel. The former is a bit
1175 more difficult to edit/modify, the later requires probably a bit
1176 more code to handle the tree structure. Note that the structure
1177 format has been designed so it's relatively easy to "insert"
1178 properties or nodes or delete them by just memmoving things
1179 around. It contains no internal offsets or pointers for this
1182 - An example of code for iterating nodes & retrieving properties
1183 directly from the flattened tree format can be found in the kernel
1184 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1185 its usage in early_init_devtree(), and the corresponding various
1186 early_init_dt_scan_*() callbacks. That code can be re-used in a
1187 GPL bootloader, and as the author of that code, I would be happy
1188 to discuss possible free licensing to any vendor who wishes to
1189 integrate all or part of this code into a non-GPL bootloader.
1193 VI - System-on-a-chip devices and nodes
1194 =======================================
1196 Many companies are now starting to develop system-on-a-chip
1197 processors, where the processor core (CPU) and many peripheral devices
1198 exist on a single piece of silicon. For these SOCs, an SOC node
1199 should be used that defines child nodes for the devices that make
1200 up the SOC. While platforms are not required to use this model in
1201 order to boot the kernel, it is highly encouraged that all SOC
1202 implementations define as complete a flat-device-tree as possible to
1203 describe the devices on the SOC. This will allow for the
1204 genericization of much of the kernel code.
1207 1) Defining child nodes of an SOC
1208 ---------------------------------
1210 Each device that is part of an SOC may have its own node entry inside
1211 the SOC node. For each device that is included in the SOC, the unit
1212 address property represents the address offset for this device's
1213 memory-mapped registers in the parent's address space. The parent's
1214 address space is defined by the "ranges" property in the top-level soc
1215 node. The "reg" property for each node that exists directly under the
1216 SOC node should contain the address mapping from the child address space
1217 to the parent SOC address space and the size of the device's
1218 memory-mapped register file.
1220 For many devices that may exist inside an SOC, there are predefined
1221 specifications for the format of the device tree node. All SOC child
1222 nodes should follow these specifications, except where noted in this
1225 See appendix A for an example partial SOC node definition for the
1229 2) Representing devices without a current OF specification
1230 ----------------------------------------------------------
1232 Currently, there are many devices on SOCs that do not have a standard
1233 representation pre-defined as part of the open firmware
1234 specifications, mainly because the boards that contain these SOCs are
1235 not currently booted using open firmware. This section contains
1236 descriptions for the SOC devices for which new nodes have been
1237 defined; this list will expand as more and more SOC-containing
1238 platforms are moved over to use the flattened-device-tree model.
1242 Required properties:
1244 - device_type : Should be "ethernet-phy"
1245 - interrupts : <a b> where a is the interrupt number and b is a
1246 field that represents an encoding of the sense and level
1247 information for the interrupt. This should be encoded based on
1248 the information in section 2) depending on the type of interrupt
1249 controller you have.
1250 - interrupt-parent : the phandle for the interrupt controller that
1251 services interrupts for this device.
1252 - reg : The ID number for the phy, usually a small integer
1253 - linux,phandle : phandle for this node; likely referenced by an
1254 ethernet controller node.
1260 linux,phandle = <2452000>
1261 interrupt-parent = <40000>;
1262 interrupts = <35 1>;
1264 device_type = "ethernet-phy";
1268 b) Interrupt controllers
1270 Some SOC devices contain interrupt controllers that are different
1271 from the standard Open PIC specification. The SOC device nodes for
1272 these types of controllers should be specified just like a standard
1273 OpenPIC controller. Sense and level information should be encoded
1274 as specified in section 2) of this chapter for each device that
1275 specifies an interrupt.
1280 linux,phandle = <40000>;
1281 interrupt-controller;
1282 #address-cells = <0>;
1283 reg = <40000 40000>;
1284 compatible = "chrp,open-pic";
1285 device_type = "open-pic";
1288 c) CFI or JEDEC memory-mapped NOR flash
1290 Flash chips (Memory Technology Devices) are often used for solid state
1291 file systems on embedded devices.
1293 - compatible : should contain the specific model of flash chip(s)
1294 used, if known, followed by either "cfi-flash" or "jedec-flash"
1295 - reg : Address range of the flash chip
1296 - bank-width : Width (in bytes) of the flash bank. Equal to the
1297 device width times the number of interleaved chips.
1298 - device-width : (optional) Width of a single flash chip. If
1299 omitted, assumed to be equal to 'bank-width'.
1300 - #address-cells, #size-cells : Must be present if the flash has
1301 sub-nodes representing partitions (see below). In this case
1302 both #address-cells and #size-cells must be equal to 1.
1304 For JEDEC compatible devices, the following additional properties
1307 - vendor-id : Contains the flash chip's vendor id (1 byte).
1308 - device-id : Contains the flash chip's device id (1 byte).
1310 In addition to the information on the flash bank itself, the
1311 device tree may optionally contain additional information
1312 describing partitions of the flash address space. This can be
1313 used on platforms which have strong conventions about which
1314 portions of the flash are used for what purposes, but which don't
1315 use an on-flash partition table such as RedBoot.
1317 Each partition is represented as a sub-node of the flash device.
1318 Each node's name represents the name of the corresponding
1319 partition of the flash device.
1322 - reg : The partition's offset and size within the flash bank.
1323 - label : (optional) The label / name for this flash partition.
1324 If omitted, the label is taken from the node name (excluding
1326 - read-only : (optional) This parameter, if present, is a hint to
1327 Linux that this flash partition should only be mounted
1328 read-only. This is usually used for flash partitions
1329 containing early-boot firmware images or data which should not
1335 compatible = "amd,am29lv128ml", "cfi-flash";
1336 reg = <ff000000 01000000>;
1339 #address-cells = <1>;
1347 reg = <f80000 80000>;
1352 d) 4xx/Axon EMAC ethernet nodes
1354 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1355 the Axon bridge. To operate this needs to interact with a ths
1356 special McMAL DMA controller, and sometimes an RGMII or ZMII
1357 interface. In addition to the nodes and properties described
1358 below, the node for the OPB bus on which the EMAC sits must have a
1359 correct clock-frequency property.
1361 i) The EMAC node itself
1363 Required properties:
1364 - device_type : "network"
1366 - compatible : compatible list, contains 2 entries, first is
1367 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1368 405gp, Axon) and second is either "ibm,emac" or
1369 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1371 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1372 - interrupt-parent : optional, if needed for interrupt mapping
1373 - reg : <registers mapping>
1374 - local-mac-address : 6 bytes, MAC address
1375 - mal-device : phandle of the associated McMAL node
1376 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1378 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1380 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1381 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1383 - max-frame-size : 1 cell, maximum frame size supported in bytes
1384 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1387 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1390 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1392 For Axon, 0x00000010
1393 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1395 For Axon, 0x00000100 (I think ...)
1396 - phy-mode : string, mode of operations of the PHY interface.
1397 Supported values are: "mii", "rmii", "smii", "rgmii",
1398 "tbi", "gmii", rtbi", "sgmii".
1399 For Axon on CAB, it is "rgmii"
1400 - mdio-device : 1 cell, required iff using shared MDIO registers
1401 (440EP). phandle of the EMAC to use to drive the
1402 MDIO lines for the PHY used by this EMAC.
1403 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1404 the ZMII device node
1405 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1406 channel or 0xffffffff if ZMII is only used for MDIO.
1407 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1408 of the RGMII device node.
1409 For Axon: phandle of plb5/plb4/opb/rgmii
1410 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1411 RGMII channel is used by this EMAC.
1412 Fox Axon: present, whatever value is appropriate for each
1413 EMAC, that is the content of the current (bogus) "phy-port"
1416 Optional properties:
1417 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1418 a search is performed.
1419 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1420 for, used if phy-address is absent. bit 0x00000001 is
1422 For Axon it can be absent, thouugh my current driver
1423 doesn't handle phy-address yet so for now, keep
1425 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1426 operations (if absent the value is the same as
1427 rx-fifo-size). For Axon, either absent or 2048.
1428 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1429 operations (if absent the value is the same as
1430 tx-fifo-size). For Axon, either absent or 2048.
1431 - tah-device : 1 cell, optional. If connected to a TAH engine for
1432 offload, phandle of the TAH device node.
1433 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1438 EMAC0: ethernet@40000800 {
1439 device_type = "network";
1440 compatible = "ibm,emac-440gp", "ibm,emac";
1441 interrupt-parent = <&UIC1>;
1442 interrupts = <1c 4 1d 4>;
1443 reg = <40000800 70>;
1444 local-mac-address = [00 04 AC E3 1B 1E];
1445 mal-device = <&MAL0>;
1446 mal-tx-channel = <0 1>;
1447 mal-rx-channel = <0>;
1449 max-frame-size = <5dc>;
1450 rx-fifo-size = <1000>;
1451 tx-fifo-size = <800>;
1453 phy-map = <00000001>;
1454 zmii-device = <&ZMII0>;
1460 Required properties:
1461 - device_type : "dma-controller"
1462 - compatible : compatible list, containing 2 entries, first is
1463 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1464 emac) and the second is either "ibm,mcmal" or
1466 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1467 - interrupts : <interrupt mapping for the MAL interrupts sources:
1468 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1469 For Axon: This is _different_ from the current
1470 firmware. We use the "delayed" interrupts for txeob
1471 and rxeob. Thus we end up with mapping those 5 MPIC
1472 interrupts, all level positive sensitive: 10, 11, 32,
1474 - dcr-reg : < DCR registers range >
1475 - dcr-parent : if needed for dcr-reg
1476 - num-tx-chans : 1 cell, number of Tx channels
1477 - num-rx-chans : 1 cell, number of Rx channels
1481 Required properties:
1482 - compatible : compatible list, containing 2 entries, first is
1483 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1484 EMAC) and the second is "ibm,zmii".
1485 For Axon, there is no ZMII node.
1486 - reg : <registers mapping>
1490 Required properties:
1491 - compatible : compatible list, containing 2 entries, first is
1492 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1493 EMAC) and the second is "ibm,rgmii".
1494 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1495 - reg : <registers mapping>
1496 - revision : as provided by the RGMII new version register if
1498 For Axon: 0x0000012a
1502 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1503 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1504 of standard device types (network, serial, etc.) and miscellanious
1505 devices (gpio, LCD, spi, etc). Also, since these devices are
1506 implemented within the fpga fabric every instance of the device can be
1507 synthesised with different options that change the behaviour.
1509 Each IP-core has a set of parameters which the FPGA designer can use to
1510 control how the core is synthesized. Historically, the EDK tool would
1511 extract the device parameters relevant to device drivers and copy them
1512 into an 'xparameters.h' in the form of #define symbols. This tells the
1513 device drivers how the IP cores are configured, but it requres the kernel
1514 to be recompiled every time the FPGA bitstream is resynthesized.
1516 The new approach is to export the parameters into the device tree and
1517 generate a new device tree each time the FPGA bitstream changes. The
1518 parameters which used to be exported as #defines will now become
1519 properties of the device node. In general, device nodes for IP-cores
1520 will take the following form:
1522 (name): (generic-name)@(base-address) {
1523 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1524 [, (list of compatible devices), ...];
1525 reg = <(baseaddr) (size)>;
1526 interrupt-parent = <&interrupt-controller-phandle>;
1527 interrupts = < ... >;
1528 xlnx,(parameter1) = "(string-value)";
1529 xlnx,(parameter2) = <(int-value)>;
1532 (generic-name): an open firmware-style name that describes the
1533 generic class of device. Preferably, this is one word, such
1534 as 'serial' or 'ethernet'.
1535 (ip-core-name): the name of the ip block (given after the BEGIN
1536 directive in system.mhs). Should be in lowercase
1537 and all underscores '_' converted to dashes '-'.
1538 (name): is derived from the "PARAMETER INSTANCE" value.
1539 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1540 dropped from the parameter name, the name is converted
1541 to lowercase and all underscore '_' characters are
1542 converted to dashes '-'.
1543 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1544 (HW_VER): from the HW_VER parameter.
1545 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1547 Typically, the compatible list will include the exact IP core version
1548 followed by an older IP core version which implements the same
1549 interface or any other device with the same interface.
1551 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1553 For example, the following block from system.mhs:
1556 PARAMETER INSTANCE = opb_uartlite_0
1557 PARAMETER HW_VER = 1.00.b
1558 PARAMETER C_BAUDRATE = 115200
1559 PARAMETER C_DATA_BITS = 8
1560 PARAMETER C_ODD_PARITY = 0
1561 PARAMETER C_USE_PARITY = 0
1562 PARAMETER C_CLK_FREQ = 50000000
1563 PARAMETER C_BASEADDR = 0xEC100000
1564 PARAMETER C_HIGHADDR = 0xEC10FFFF
1565 BUS_INTERFACE SOPB = opb_7
1566 PORT OPB_Clk = CLK_50MHz
1567 PORT Interrupt = opb_uartlite_0_Interrupt
1568 PORT RX = opb_uartlite_0_RX
1569 PORT TX = opb_uartlite_0_TX
1570 PORT OPB_Rst = sys_bus_reset_0
1573 becomes the following device tree node:
1575 opb_uartlite_0: serial@ec100000 {
1576 device_type = "serial";
1577 compatible = "xlnx,opb-uartlite-1.00.b";
1578 reg = <ec100000 10000>;
1579 interrupt-parent = <&opb_intc_0>;
1580 interrupts = <1 0>; // got this from the opb_intc parameters
1581 current-speed = <d#115200>; // standard serial device prop
1582 clock-frequency = <d#50000000>; // standard serial device prop
1583 xlnx,data-bits = <8>;
1584 xlnx,odd-parity = <0>;
1585 xlnx,use-parity = <0>;
1588 Some IP cores actually implement 2 or more logical devices. In
1589 this case, the device should still describe the whole IP core with
1590 a single node and add a child node for each logical device. The
1591 ranges property can be used to translate from parent IP-core to the
1592 registers of each device. In addition, the parent node should be
1593 compatible with the bus type 'xlnx,compound', and should contain
1594 #address-cells and #size-cells, as with any other bus. (Note: this
1595 makes the assumption that both logical devices have the same bus
1596 binding. If this is not true, then separate nodes should be used
1597 for each logical device). The 'cell-index' property can be used to
1598 enumerate logical devices within an IP core. For example, the
1599 following is the system.mhs entry for the dual ps2 controller found
1600 on the ml403 reference design.
1602 BEGIN opb_ps2_dual_ref
1603 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1604 PARAMETER HW_VER = 1.00.a
1605 PARAMETER C_BASEADDR = 0xA9000000
1606 PARAMETER C_HIGHADDR = 0xA9001FFF
1607 BUS_INTERFACE SOPB = opb_v20_0
1608 PORT Sys_Intr1 = ps2_1_intr
1609 PORT Sys_Intr2 = ps2_2_intr
1610 PORT Clkin1 = ps2_clk_rx_1
1611 PORT Clkin2 = ps2_clk_rx_2
1612 PORT Clkpd1 = ps2_clk_tx_1
1613 PORT Clkpd2 = ps2_clk_tx_2
1614 PORT Rx1 = ps2_d_rx_1
1615 PORT Rx2 = ps2_d_rx_2
1616 PORT Txpd1 = ps2_d_tx_1
1617 PORT Txpd2 = ps2_d_tx_2
1620 It would result in the following device tree nodes:
1622 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1623 #address-cells = <1>;
1625 compatible = "xlnx,compound";
1626 ranges = <0 a9000000 2000>;
1627 // If this device had extra parameters, then they would
1630 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1632 interrupt-parent = <&opb_intc_0>;
1637 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1639 interrupt-parent = <&opb_intc_0>;
1645 Also, the system.mhs file defines bus attachments from the processor
1646 to the devices. The device tree structure should reflect the bus
1647 attachments. Again an example; this system.mhs fragment:
1649 BEGIN ppc405_virtex4
1650 PARAMETER INSTANCE = ppc405_0
1651 PARAMETER HW_VER = 1.01.a
1652 BUS_INTERFACE DPLB = plb_v34_0
1653 BUS_INTERFACE IPLB = plb_v34_0
1657 PARAMETER INSTANCE = opb_intc_0
1658 PARAMETER HW_VER = 1.00.c
1659 PARAMETER C_BASEADDR = 0xD1000FC0
1660 PARAMETER C_HIGHADDR = 0xD1000FDF
1661 BUS_INTERFACE SOPB = opb_v20_0
1665 PARAMETER INSTANCE = opb_uart16550_0
1666 PARAMETER HW_VER = 1.00.d
1667 PARAMETER C_BASEADDR = 0xa0000000
1668 PARAMETER C_HIGHADDR = 0xa0001FFF
1669 BUS_INTERFACE SOPB = opb_v20_0
1673 PARAMETER INSTANCE = plb_v34_0
1674 PARAMETER HW_VER = 1.02.a
1677 BEGIN plb_bram_if_cntlr
1678 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1679 PARAMETER HW_VER = 1.00.b
1680 PARAMETER C_BASEADDR = 0xFFFF0000
1681 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1682 BUS_INTERFACE SPLB = plb_v34_0
1685 BEGIN plb2opb_bridge
1686 PARAMETER INSTANCE = plb2opb_bridge_0
1687 PARAMETER HW_VER = 1.01.a
1688 PARAMETER C_RNG0_BASEADDR = 0x20000000
1689 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1690 PARAMETER C_RNG1_BASEADDR = 0x60000000
1691 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1692 PARAMETER C_RNG2_BASEADDR = 0x80000000
1693 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1694 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1695 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1696 BUS_INTERFACE SPLB = plb_v34_0
1697 BUS_INTERFACE MOPB = opb_v20_0
1700 Gives this device tree (some properties removed for clarity):
1703 #address-cells = <1>;
1705 compatible = "xlnx,plb-v34-1.02.a";
1706 device_type = "ibm,plb";
1707 ranges; // 1:1 translation
1709 plb_bram_if_cntrl_0: bram@ffff0000 {
1710 reg = <ffff0000 10000>;
1714 #address-cells = <1>;
1716 ranges = <20000000 20000000 20000000
1717 60000000 60000000 20000000
1718 80000000 80000000 40000000
1719 c0000000 c0000000 20000000>;
1721 opb_uart16550_0: serial@a0000000 {
1722 reg = <a00000000 2000>;
1725 opb_intc_0: interrupt-controller@d1000fc0 {
1726 reg = <d1000fc0 20>;
1731 That covers the general approach to binding xilinx IP cores into the
1732 device tree. The following are bindings for specific devices:
1734 i) Xilinx ML300 Framebuffer
1736 Simple framebuffer device from the ML300 reference design (also on the
1737 ML403 reference design as well as others).
1739 Optional properties:
1740 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1741 implementations use a different resolution.
1742 Default is <d#640 d#480>
1743 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1744 Default is <d#1024 d#480>.
1745 - rotate-display (empty) : rotate display 180 degrees.
1747 ii) Xilinx SystemACE
1749 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1750 bitstream stored on a CF card. It can also be used as a generic CF
1753 Optional properties:
1754 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1756 iii) Xilinx EMAC and Xilinx TEMAC
1758 Xilinx Ethernet devices. In addition to general xilinx properties
1759 listed above, nodes for these devices should include a phy-handle
1760 property, and may include other common network device properties
1761 like local-mac-address.
1765 Xilinx uartlite devices are simple fixed speed serial ports.
1768 - current-speed : Baud rate of uartlite
1772 Xilinx hwicap devices provide access to the configuration logic
1773 of the FPGA through the Internal Configuration Access Port
1774 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1775 readback of the configuration information, and some control over
1776 'warm boots' of the FPGA fabric.
1778 Required properties:
1779 - xlnx,family : The family of the FPGA, necessary since the
1780 capabilities of the underlying ICAP hardware
1781 differ between different families. May be
1782 'virtex2p', 'virtex4', or 'virtex5'.
1784 vi) Xilinx Uart 16550
1786 Xilinx UART 16550 devices are very similar to the NS16550 but with
1787 different register spacing and an offset from the base address.
1790 - clock-frequency : Frequency of the clock input
1791 - reg-offset : A value of 3 is required
1792 - reg-shift : A value of 2 is required
1794 f) USB EHCI controllers
1796 Required properties:
1797 - compatible : should be "usb-ehci".
1798 - reg : should contain at least address and length of the standard EHCI
1799 register set for the device. Optional platform-dependent registers
1800 (debug-port or other) can be also specified here, but only after
1801 definition of standard EHCI registers.
1802 - interrupts : one EHCI interrupt should be described here.
1803 If device registers are implemented in big endian mode, the device
1804 node should have "big-endian-regs" property.
1805 If controller implementation operates with big endian descriptors,
1806 "big-endian-desc" property should be specified.
1807 If both big endian registers and descriptors are used by the controller
1808 implementation, "big-endian" property can be specified instead of having
1809 both "big-endian-regs" and "big-endian-desc".
1811 Example (Sequoia 440EPx):
1813 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1814 interrupt-parent = <&UIC0>;
1815 interrupts = <1a 4>;
1816 reg = <0 e0000300 90 0 e0000390 70>;
1820 VII - Marvell Discovery mv64[345]6x System Controller chips
1821 ===========================================================
1823 The Marvell mv64[345]60 series of system controller chips contain
1824 many of the peripherals needed to implement a complete computer
1825 system. In this section, we define device tree nodes to describe
1826 the system controller chip itself and each of the peripherals
1827 which it contains. Compatible string values for each node are
1828 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1830 1) The /system-controller node
1832 This node is used to represent the system-controller and must be
1833 present when the system uses a system contller chip. The top-level
1834 system-controller node contains information that is global to all
1835 devices within the system controller chip. The node name begins
1836 with "system-controller" followed by the unit address, which is
1837 the base address of the memory-mapped register set for the system
1840 Required properties:
1842 - ranges : Describes the translation of system controller addresses
1843 for memory mapped registers.
1844 - clock-frequency: Contains the main clock frequency for the system
1846 - reg : This property defines the address and size of the
1847 memory-mapped registers contained within the system controller
1848 chip. The address specified in the "reg" property should match
1849 the unit address of the system-controller node.
1850 - #address-cells : Address representation for system controller
1851 devices. This field represents the number of cells needed to
1852 represent the address of the memory-mapped registers of devices
1853 within the system controller chip.
1854 - #size-cells : Size representation for for the memory-mapped
1855 registers within the system controller chip.
1856 - #interrupt-cells : Defines the width of cells used to represent
1859 Optional properties:
1861 - model : The specific model of the system controller chip. Such
1862 as, "mv64360", "mv64460", or "mv64560".
1863 - compatible : A string identifying the compatibility identifiers
1864 of the system controller chip.
1866 The system-controller node contains child nodes for each system
1867 controller device that the platform uses. Nodes should not be created
1868 for devices which exist on the system controller chip but are not used
1870 Example Marvell Discovery mv64360 system-controller node:
1872 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1873 #address-cells = <1>;
1875 model = "mv64360"; /* Default */
1876 compatible = "marvell,mv64360";
1877 clock-frequency = <133333333>;
1878 reg = <0xf1000000 0x10000>;
1879 virtual-reg = <0xf1000000>;
1880 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1881 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1882 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1883 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1884 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1886 [ child node definitions... ]
1889 2) Child nodes of /system-controller
1891 a) Marvell Discovery MDIO bus
1893 The MDIO is a bus to which the PHY devices are connected. For each
1894 device that exists on this bus, a child node should be created. See
1895 the definition of the PHY node below for an example of how to define
1898 Required properties:
1899 - #address-cells : Should be <1>
1900 - #size-cells : Should be <0>
1901 - device_type : Should be "mdio"
1902 - compatible : Should be "marvell,mv64360-mdio"
1907 #address-cells = <1>;
1909 device_type = "mdio";
1910 compatible = "marvell,mv64360-mdio";
1918 b) Marvell Discovery ethernet controller
1920 The Discover ethernet controller is described with two levels
1921 of nodes. The first level describes an ethernet silicon block
1922 and the second level describes up to 3 ethernet nodes within
1923 that block. The reason for the multiple levels is that the
1924 registers for the node are interleaved within a single set
1925 of registers. The "ethernet-block" level describes the
1926 shared register set, and the "ethernet" nodes describe ethernet
1927 port-specific properties.
1931 Required properties:
1932 - #address-cells : <1>
1934 - compatible : "marvell,mv64360-eth-block"
1935 - reg : Offset and length of the register set for this block
1937 Example Discovery Ethernet block node:
1938 ethernet-block@2000 {
1939 #address-cells = <1>;
1941 compatible = "marvell,mv64360-eth-block";
1942 reg = <0x2000 0x2000>;
1950 Required properties:
1951 - device_type : Should be "network".
1952 - compatible : Should be "marvell,mv64360-eth".
1953 - reg : Should be <0>, <1>, or <2>, according to which registers
1954 within the silicon block the device uses.
1955 - interrupts : <a> where a is the interrupt number for the port.
1956 - interrupt-parent : the phandle for the interrupt controller
1957 that services interrupts for this device.
1958 - phy : the phandle for the PHY connected to this ethernet
1960 - local-mac-address : 6 bytes, MAC address
1962 Example Discovery Ethernet port node:
1964 device_type = "network";
1965 compatible = "marvell,mv64360-eth";
1968 interrupt-parent = <&PIC>;
1970 local-mac-address = [ 00 00 00 00 00 00 ];
1975 c) Marvell Discovery PHY nodes
1977 Required properties:
1978 - device_type : Should be "ethernet-phy"
1979 - interrupts : <a> where a is the interrupt number for this phy.
1980 - interrupt-parent : the phandle for the interrupt controller that
1981 services interrupts for this device.
1982 - reg : The ID number for the phy, usually a small integer
1984 Example Discovery PHY node:
1986 device_type = "ethernet-phy";
1987 compatible = "broadcom,bcm5421";
1988 interrupts = <76>; /* GPP 12 */
1989 interrupt-parent = <&PIC>;
1994 d) Marvell Discovery SDMA nodes
1996 Represent DMA hardware associated with the MPSC (multiprotocol
1997 serial controllers).
1999 Required properties:
2000 - compatible : "marvell,mv64360-sdma"
2001 - reg : Offset and length of the register set for this device
2002 - interrupts : <a> where a is the interrupt number for the DMA
2004 - interrupt-parent : the phandle for the interrupt controller
2005 that services interrupts for this device.
2007 Example Discovery SDMA node:
2009 compatible = "marvell,mv64360-sdma";
2010 reg = <0x4000 0xc18>;
2011 virtual-reg = <0xf1004000>;
2013 interrupt-parent = <&PIC>;
2017 e) Marvell Discovery BRG nodes
2019 Represent baud rate generator hardware associated with the MPSC
2020 (multiprotocol serial controllers).
2022 Required properties:
2023 - compatible : "marvell,mv64360-brg"
2024 - reg : Offset and length of the register set for this device
2025 - clock-src : A value from 0 to 15 which selects the clock
2026 source for the baud rate generator. This value corresponds
2027 to the CLKS value in the BRGx configuration register. See
2028 the mv64x60 User's Manual.
2029 - clock-frequence : The frequency (in Hz) of the baud rate
2030 generator's input clock.
2031 - current-speed : The current speed setting (presumably by
2032 firmware) of the baud rate generator.
2034 Example Discovery BRG node:
2036 compatible = "marvell,mv64360-brg";
2039 clock-frequency = <133333333>;
2040 current-speed = <9600>;
2044 f) Marvell Discovery CUNIT nodes
2046 Represent the Serial Communications Unit device hardware.
2048 Required properties:
2049 - reg : Offset and length of the register set for this device
2051 Example Discovery CUNIT node:
2053 reg = <0xf200 0x200>;
2057 g) Marvell Discovery MPSCROUTING nodes
2059 Represent the Discovery's MPSC routing hardware
2061 Required properties:
2062 - reg : Offset and length of the register set for this device
2064 Example Discovery CUNIT node:
2070 h) Marvell Discovery MPSCINTR nodes
2072 Represent the Discovery's MPSC DMA interrupt hardware registers
2073 (SDMA cause and mask registers).
2075 Required properties:
2076 - reg : Offset and length of the register set for this device
2078 Example Discovery MPSCINTR node:
2080 reg = <0xb800 0x100>;
2084 i) Marvell Discovery MPSC nodes
2086 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2089 Required properties:
2090 - device_type : "serial"
2091 - compatible : "marvell,mv64360-mpsc"
2092 - reg : Offset and length of the register set for this device
2093 - sdma : the phandle for the SDMA node used by this port
2094 - brg : the phandle for the BRG node used by this port
2095 - cunit : the phandle for the CUNIT node used by this port
2096 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2097 - mpscintr : the phandle for the MPSCINTR node used by this port
2098 - cell-index : the hardware index of this cell in the MPSC core
2099 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2101 - interrupts : <a> where a is the interrupt number for the MPSC.
2102 - interrupt-parent : the phandle for the interrupt controller
2103 that services interrupts for this device.
2105 Example Discovery MPSCINTR node:
2107 device_type = "serial";
2108 compatible = "marvell,mv64360-mpsc";
2109 reg = <0x8000 0x38>;
2110 virtual-reg = <0xf1008000>;
2114 mpscrouting = <&MPSCROUTING>;
2115 mpscintr = <&MPSCINTR>;
2119 interrupt-parent = <&PIC>;
2123 j) Marvell Discovery Watch Dog Timer nodes
2125 Represent the Discovery's watchdog timer hardware
2127 Required properties:
2128 - compatible : "marvell,mv64360-wdt"
2129 - reg : Offset and length of the register set for this device
2131 Example Discovery Watch Dog Timer node:
2133 compatible = "marvell,mv64360-wdt";
2138 k) Marvell Discovery I2C nodes
2140 Represent the Discovery's I2C hardware
2142 Required properties:
2143 - device_type : "i2c"
2144 - compatible : "marvell,mv64360-i2c"
2145 - reg : Offset and length of the register set for this device
2146 - interrupts : <a> where a is the interrupt number for the I2C.
2147 - interrupt-parent : the phandle for the interrupt controller
2148 that services interrupts for this device.
2150 Example Discovery I2C node:
2151 compatible = "marvell,mv64360-i2c";
2152 reg = <0xc000 0x20>;
2153 virtual-reg = <0xf100c000>;
2155 interrupt-parent = <&PIC>;
2159 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2161 Represent the Discovery's PIC hardware
2163 Required properties:
2164 - #interrupt-cells : <1>
2165 - #address-cells : <0>
2166 - compatible : "marvell,mv64360-pic"
2167 - reg : Offset and length of the register set for this device
2168 - interrupt-controller
2170 Example Discovery PIC node:
2172 #interrupt-cells = <1>;
2173 #address-cells = <0>;
2174 compatible = "marvell,mv64360-pic";
2176 interrupt-controller;
2180 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2182 Represent the Discovery's MPP hardware
2184 Required properties:
2185 - compatible : "marvell,mv64360-mpp"
2186 - reg : Offset and length of the register set for this device
2188 Example Discovery MPP node:
2190 compatible = "marvell,mv64360-mpp";
2191 reg = <0xf000 0x10>;
2195 n) Marvell Discovery GPP (General Purpose Pins) nodes
2197 Represent the Discovery's GPP hardware
2199 Required properties:
2200 - compatible : "marvell,mv64360-gpp"
2201 - reg : Offset and length of the register set for this device
2203 Example Discovery GPP node:
2205 compatible = "marvell,mv64360-gpp";
2206 reg = <0xf100 0x20>;
2210 o) Marvell Discovery PCI host bridge node
2212 Represents the Discovery's PCI host bridge device. The properties
2213 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2214 1275-1994. A typical value for the compatible property is
2215 "marvell,mv64360-pci".
2217 Example Discovery PCI host bridge node
2219 #address-cells = <3>;
2221 #interrupt-cells = <1>;
2222 device_type = "pci";
2223 compatible = "marvell,mv64360-pci";
2225 ranges = <0x01000000 0x0 0x0
2226 0x88000000 0x0 0x01000000
2227 0x02000000 0x0 0x80000000
2228 0x80000000 0x0 0x08000000>;
2229 bus-range = <0 255>;
2230 clock-frequency = <66000000>;
2231 interrupt-parent = <&PIC>;
2232 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2235 0x5000 0 0 1 &PIC 80
2236 0x5000 0 0 2 &PIC 81
2237 0x5000 0 0 3 &PIC 91
2238 0x5000 0 0 4 &PIC 93
2241 0x5800 0 0 1 &PIC 91
2242 0x5800 0 0 2 &PIC 93
2243 0x5800 0 0 3 &PIC 80
2244 0x5800 0 0 4 &PIC 81
2247 0x6000 0 0 1 &PIC 91
2248 0x6000 0 0 2 &PIC 93
2249 0x6000 0 0 3 &PIC 80
2250 0x6000 0 0 4 &PIC 81
2253 0x6800 0 0 1 &PIC 93
2254 0x6800 0 0 2 &PIC 80
2255 0x6800 0 0 3 &PIC 81
2256 0x6800 0 0 4 &PIC 91
2261 p) Marvell Discovery CPU Error nodes
2263 Represent the Discovery's CPU error handler device.
2265 Required properties:
2266 - compatible : "marvell,mv64360-cpu-error"
2267 - reg : Offset and length of the register set for this device
2268 - interrupts : the interrupt number for this device
2269 - interrupt-parent : the phandle for the interrupt controller
2270 that services interrupts for this device.
2272 Example Discovery CPU Error node:
2274 compatible = "marvell,mv64360-cpu-error";
2275 reg = <0x70 0x10 0x128 0x28>;
2277 interrupt-parent = <&PIC>;
2281 q) Marvell Discovery SRAM Controller nodes
2283 Represent the Discovery's SRAM controller device.
2285 Required properties:
2286 - compatible : "marvell,mv64360-sram-ctrl"
2287 - reg : Offset and length of the register set for this device
2288 - interrupts : the interrupt number for this device
2289 - interrupt-parent : the phandle for the interrupt controller
2290 that services interrupts for this device.
2292 Example Discovery SRAM Controller node:
2294 compatible = "marvell,mv64360-sram-ctrl";
2297 interrupt-parent = <&PIC>;
2301 r) Marvell Discovery PCI Error Handler nodes
2303 Represent the Discovery's PCI error handler device.
2305 Required properties:
2306 - compatible : "marvell,mv64360-pci-error"
2307 - reg : Offset and length of the register set for this device
2308 - interrupts : the interrupt number for this device
2309 - interrupt-parent : the phandle for the interrupt controller
2310 that services interrupts for this device.
2312 Example Discovery PCI Error Handler node:
2314 compatible = "marvell,mv64360-pci-error";
2315 reg = <0x1d40 0x40 0xc28 0x4>;
2317 interrupt-parent = <&PIC>;
2321 s) Marvell Discovery Memory Controller nodes
2323 Represent the Discovery's memory controller device.
2325 Required properties:
2326 - compatible : "marvell,mv64360-mem-ctrl"
2327 - reg : Offset and length of the register set for this device
2328 - interrupts : the interrupt number for this device
2329 - interrupt-parent : the phandle for the interrupt controller
2330 that services interrupts for this device.
2332 Example Discovery Memory Controller node:
2334 compatible = "marvell,mv64360-mem-ctrl";
2335 reg = <0x1400 0x60>;
2337 interrupt-parent = <&PIC>;
2341 VIII - Specifying interrupt information for devices
2342 ===================================================
2344 The device tree represents the busses and devices of a hardware
2345 system in a form similar to the physical bus topology of the
2348 In addition, a logical 'interrupt tree' exists which represents the
2349 hierarchy and routing of interrupts in the hardware.
2351 The interrupt tree model is fully described in the
2352 document "Open Firmware Recommended Practice: Interrupt
2353 Mapping Version 0.9". The document is available at:
2354 <http://playground.sun.com/1275/practice>.
2356 1) interrupts property
2357 ----------------------
2359 Devices that generate interrupts to a single interrupt controller
2360 should use the conventional OF representation described in the
2361 OF interrupt mapping documentation.
2363 Each device which generates interrupts must have an 'interrupt'
2364 property. The interrupt property value is an arbitrary number of
2365 of 'interrupt specifier' values which describe the interrupt or
2366 interrupts for the device.
2368 The encoding of an interrupt specifier is determined by the
2369 interrupt domain in which the device is located in the
2370 interrupt tree. The root of an interrupt domain specifies in
2371 its #interrupt-cells property the number of 32-bit cells
2372 required to encode an interrupt specifier. See the OF interrupt
2373 mapping documentation for a detailed description of domains.
2375 For example, the binding for the OpenPIC interrupt controller
2376 specifies an #interrupt-cells value of 2 to encode the interrupt
2377 number and level/sense information. All interrupt children in an
2378 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2381 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2382 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2384 2) interrupt-parent property
2385 ----------------------------
2387 The interrupt-parent property is specified to define an explicit
2388 link between a device node and its interrupt parent in
2389 the interrupt tree. The value of interrupt-parent is the
2390 phandle of the parent node.
2392 If the interrupt-parent property is not defined for a node, it's
2393 interrupt parent is assumed to be an ancestor in the node's
2394 _device tree_ hierarchy.
2396 3) OpenPIC Interrupt Controllers
2397 --------------------------------
2399 OpenPIC interrupt controllers require 2 cells to encode
2400 interrupt information. The first cell defines the interrupt
2401 number. The second cell defines the sense and level
2404 Sense and level information should be encoded as follows:
2406 0 = low to high edge sensitive type enabled
2407 1 = active low level sensitive type enabled
2408 2 = active high level sensitive type enabled
2409 3 = high to low edge sensitive type enabled
2411 4) ISA Interrupt Controllers
2412 ----------------------------
2414 ISA PIC interrupt controllers require 2 cells to encode
2415 interrupt information. The first cell defines the interrupt
2416 number. The second cell defines the sense and level
2419 ISA PIC interrupt controllers should adhere to the ISA PIC
2420 encodings listed below:
2422 0 = active low level sensitive type enabled
2423 1 = active high level sensitive type enabled
2424 2 = high to low edge sensitive type enabled
2425 3 = low to high edge sensitive type enabled
2427 IX - Specifying GPIO information for devices
2428 ============================================
2433 Nodes that makes use of GPIOs should define them using `gpios' property,
2434 format of which is: <&gpio-controller1-phandle gpio1-specifier
2435 &gpio-controller2-phandle gpio2-specifier
2436 0 /* holes are permitted, means no GPIO 3 */
2437 &gpio-controller4-phandle gpio4-specifier
2440 Note that gpio-specifier length is controller dependent.
2442 gpio-specifier may encode: bank, pin position inside the bank,
2443 whether pin is open-drain and whether pin is logically inverted.
2445 Example of the node using GPIOs:
2448 gpios = <&qe_pio_e 18 0>;
2451 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2452 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2454 2) gpio-controller nodes
2455 ------------------------
2457 Every GPIO controller node must have #gpio-cells property defined,
2458 this information will be used to translate gpio-specifiers.
2460 Example of two SOC GPIO banks defined as gpio-controller nodes:
2462 qe_pio_a: gpio-controller@1400 {
2464 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2465 reg = <0x1400 0x18>;
2469 qe_pio_e: gpio-controller@1460 {
2471 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2472 reg = <0x1460 0x18>;
2476 X - Specifying Device Power Management Information (sleep property)
2477 ===================================================================
2479 Devices on SOCs often have mechanisms for placing devices into low-power
2480 states that are decoupled from the devices' own register blocks. Sometimes,
2481 this information is more complicated than a cell-index property can
2482 reasonably describe. Thus, each device controlled in such a manner
2483 may contain a "sleep" property which describes these connections.
2485 The sleep property consists of one or more sleep resources, each of
2486 which consists of a phandle to a sleep controller, followed by a
2487 controller-specific sleep specifier of zero or more cells.
2489 The semantics of what type of low power modes are possible are defined
2490 by the sleep controller. Some examples of the types of low power modes
2491 that may be supported are:
2493 - Dynamic: The device may be disabled or enabled at any time.
2494 - System Suspend: The device may request to be disabled or remain
2495 awake during system suspend, but will not be disabled until then.
2496 - Permanent: The device is disabled permanently (until the next hard
2499 Some devices may share a clock domain with each other, such that they should
2500 only be suspended when none of the devices are in use. Where reasonable,
2501 such nodes should be placed on a virtual bus, where the bus has the sleep
2502 property. If the clock domain is shared among devices that cannot be
2503 reasonably grouped in this manner, then create a virtual sleep controller
2504 (similar to an interrupt nexus, except that defining a standardized
2505 sleep-map should wait until its necessity is demonstrated).
2507 Appendix A - Sample SOC node for MPC8540
2508 ========================================
2511 #address-cells = <1>;
2513 compatible = "fsl,mpc8540-ccsr", "simple-bus";
2514 device_type = "soc";
2515 ranges = <0x00000000 0xe0000000 0x00100000>
2516 bus-frequency = <0>;
2517 interrupt-parent = <&pic>;
2520 #address-cells = <1>;
2522 device_type = "network";
2524 compatible = "gianfar", "simple-bus";
2525 reg = <0x24000 0x1000>;
2526 local-mac-address = [ 00 E0 0C 00 73 00 ];
2527 interrupts = <29 2 30 2 34 2>;
2528 phy-handle = <&phy0>;
2529 sleep = <&pmc 00000080>;
2533 reg = <0x24520 0x20>;
2534 compatible = "fsl,gianfar-mdio";
2536 phy0: ethernet-phy@0 {
2539 device_type = "ethernet-phy";
2542 phy1: ethernet-phy@1 {
2545 device_type = "ethernet-phy";
2548 phy3: ethernet-phy@3 {
2551 device_type = "ethernet-phy";
2557 device_type = "network";
2559 compatible = "gianfar";
2560 reg = <0x25000 0x1000>;
2561 local-mac-address = [ 00 E0 0C 00 73 01 ];
2562 interrupts = <13 2 14 2 18 2>;
2563 phy-handle = <&phy1>;
2564 sleep = <&pmc 00000040>;
2568 device_type = "network";
2570 compatible = "gianfar";
2571 reg = <0x26000 0x1000>;
2572 local-mac-address = [ 00 E0 0C 00 73 02 ];
2573 interrupts = <41 2>;
2574 phy-handle = <&phy3>;
2575 sleep = <&pmc 00000020>;
2579 #address-cells = <1>;
2581 compatible = "fsl,mpc8540-duart", "simple-bus";
2582 sleep = <&pmc 00000002>;
2586 device_type = "serial";
2587 compatible = "ns16550";
2588 reg = <0x4500 0x100>;
2589 clock-frequency = <0>;
2590 interrupts = <42 2>;
2594 device_type = "serial";
2595 compatible = "ns16550";
2596 reg = <0x4600 0x100>;
2597 clock-frequency = <0>;
2598 interrupts = <42 2>;
2603 interrupt-controller;
2604 #address-cells = <0>;
2605 #interrupt-cells = <2>;
2606 reg = <0x40000 0x40000>;
2607 compatible = "chrp,open-pic";
2608 device_type = "open-pic";
2612 interrupts = <43 2>;
2613 reg = <0x3000 0x100>;
2614 compatible = "fsl-i2c";
2616 sleep = <&pmc 00000004>;
2620 compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
2621 reg = <0xe0070 0x20>;