git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/sched.h>
  41 #include <linux/device.h>
  42 #include <scsi/scsi_host.h>
  43 #include <scsi/scsi_cmnd.h>
  44 #include <linux/libata.h>
  45 #include <asm/io.h>
  46 #include "sata_promise.h"
  47
  48 #define DRV_NAME        "sata_sx4"
  49 #define DRV_VERSION     "0.9"
  50
  51
  52 enum {
  53         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  54
  55         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  56         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  57         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  58         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  59
  60         PDC_20621_SEQCTL        = 0x400,
  61         PDC_20621_SEQMASK       = 0x480,
  62         PDC_20621_GENERAL_CTL   = 0x484,
  63         PDC_20621_PAGE_SIZE     = (32 * 1024),
  64
  65         /* chosen, not constant, values; we design our own DIMM mem map */
  66         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  67         PDC_20621_DIMM_BASE     = 0x00200000,
  68         PDC_20621_DIMM_DATA     = (64 * 1024),
  69         PDC_DIMM_DATA_STEP      = (256 * 1024),
  70         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  71         PDC_DIMM_HOST_PRD       = (6 * 1024),
  72         PDC_DIMM_HOST_PKT       = (128 * 0),
  73         PDC_DIMM_HPKT_PRD       = (128 * 1),
  74         PDC_DIMM_ATA_PKT        = (128 * 2),
  75         PDC_DIMM_APKT_PRD       = (128 * 3),
  76         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  77         PDC_PAGE_WINDOW         = 0x40,
  78         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  79                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  80         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  81
  82         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  83
  84         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  85                                   (1<<23),
  86
  87         board_20621             = 0,    /* FastTrak S150 SX4 */
  88
  89         PDC_RESET               = (1 << 11), /* HDMA reset */
  90
  91         PDC_MAX_HDMA            = 32,
  92         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  93
  94         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  95         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  96         PDC_MAX_DIMM_MODULE           = 0x02,
  97         PDC_I2C_CONTROL_OFFSET        = 0x48,
  98         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  99         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
 100         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
 101         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
 102         PDC_I2C_WRITE                 = 0x00000000,
 103         PDC_I2C_READ                  = 0x00000040,
 104         PDC_I2C_START                 = 0x00000080,
 105         PDC_I2C_MASK_INT              = 0x00000020,
 106         PDC_I2C_COMPLETE              = 0x00010000,
 107         PDC_I2C_NO_ACK                = 0x00100000,
 108         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 109         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 110         PDC_DIMM_SPD_ROW_NUM          = 3,
 111         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 112         PDC_DIMM_SPD_MODULE_ROW       = 5,
 113         PDC_DIMM_SPD_TYPE             = 11,
 114         PDC_DIMM_SPD_FRESH_RATE       = 12,
 115         PDC_DIMM_SPD_BANK_NUM         = 17,
 116         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 117         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 118         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 119         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 120         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 121         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 122         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 123         PDC_CTL_STATUS                = 0x08,
 124         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 125         PDC_TIME_CONTROL              = 0x3C,
 126         PDC_TIME_PERIOD               = 0x40,
 127         PDC_TIME_COUNTER              = 0x44,
 128         PDC_GENERAL_CTLR              = 0x484,
 129         PCI_PLL_INIT                  = 0x8A531824,
 130         PCI_X_TCOUNT                  = 0xEE1E5CFF
 131 };
 132
 133
 134 struct pdc_port_priv {
 135         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 136         u8                      *pkt;
 137         dma_addr_t              pkt_dma;
 138 };
 139
 140 struct pdc_host_priv {
 141         void                    __iomem *dimm_mmio;
 142
 143         unsigned int            doing_hdma;
 144         unsigned int            hdma_prod;
 145         unsigned int            hdma_cons;
 146         struct {
 147                 struct ata_queued_cmd *qc;
 148                 unsigned int    seq;
 149                 unsigned long   pkt_ofs;
 150         } hdma[32];
 151 };
 152
 153
 154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 156 static void pdc_eng_timeout(struct ata_port *ap);
 157 static void pdc_20621_phy_reset (struct ata_port *ap);
 158 static int pdc_port_start(struct ata_port *ap);
 159 static void pdc_port_stop(struct ata_port *ap);
 160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 163 static void pdc20621_host_stop(struct ata_host_set *host_set);
 164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 167                                       u32 device, u32 subaddr, u32 *pdata);
 168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 170 #ifdef ATA_VERBOSE_DEBUG
 171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 172                                    void *psource, u32 offset, u32 size);
 173 #endif
 174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 175                                  void *psource, u32 offset, u32 size);
 176 static void pdc20621_irq_clear(struct ata_port *ap);
 177 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 178
 179
 180 static struct scsi_host_template pdc_sata_sht = {
 181         .module                 = THIS_MODULE,
 182         .name                   = DRV_NAME,
 183         .ioctl                  = ata_scsi_ioctl,
 184         .queuecommand           = ata_scsi_queuecmd,
 185         .can_queue              = ATA_DEF_QUEUE,
 186         .this_id                = ATA_SHT_THIS_ID,
 187         .sg_tablesize           = LIBATA_MAX_PRD,
 188         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 189         .emulated               = ATA_SHT_EMULATED,
 190         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 191         .proc_name              = DRV_NAME,
 192         .dma_boundary           = ATA_DMA_BOUNDARY,
 193         .slave_configure        = ata_scsi_slave_config,
 194         .bios_param             = ata_std_bios_param,
 195 };
 196
 197 static const struct ata_port_operations pdc_20621_ops = {
 198         .port_disable           = ata_port_disable,
 199         .tf_load                = pdc_tf_load_mmio,
 200         .tf_read                = ata_tf_read,
 201         .check_status           = ata_check_status,
 202         .exec_command           = pdc_exec_command_mmio,
 203         .dev_select             = ata_std_dev_select,
 204         .phy_reset              = pdc_20621_phy_reset,
 205         .qc_prep                = pdc20621_qc_prep,
 206         .qc_issue               = pdc20621_qc_issue_prot,
 207         .data_xfer              = ata_mmio_data_xfer,
 208         .eng_timeout            = pdc_eng_timeout,
 209         .irq_handler            = pdc20621_interrupt,
 210         .irq_clear              = pdc20621_irq_clear,
 211         .port_start             = pdc_port_start,
 212         .port_stop              = pdc_port_stop,
 213         .host_stop              = pdc20621_host_stop,
 214 };
 215
 216 static const struct ata_port_info pdc_port_info[] = {
 217         /* board_20621 */
 218         {
 219                 .sht            = &pdc_sata_sht,
 220                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 221                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 222                                   ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
 223                 .pio_mask       = 0x1f, /* pio0-4 */
 224                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 225                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 226                 .port_ops       = &pdc_20621_ops,
 227         },
 228
 229 };
 230
 231 static const struct pci_device_id pdc_sata_pci_tbl[] = {
 232         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 233           board_20621 },
 234         { }     /* terminate list */
 235 };
 236
 237
 238 static struct pci_driver pdc_sata_pci_driver = {
 239         .name                   = DRV_NAME,
 240         .id_table               = pdc_sata_pci_tbl,
 241         .probe                  = pdc_sata_init_one,
 242         .remove                 = ata_pci_remove_one,
 243 };
 244
 245
 246 static void pdc20621_host_stop(struct ata_host_set *host_set)
 247 {
 248         struct pci_dev *pdev = to_pci_dev(host_set->dev);
 249         struct pdc_host_priv *hpriv = host_set->private_data;
 250         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 251
 252         pci_iounmap(pdev, dimm_mmio);
 253         kfree(hpriv);
 254
 255         pci_iounmap(pdev, host_set->mmio_base);
 256 }
 257
 258 static int pdc_port_start(struct ata_port *ap)
 259 {
 260         struct device *dev = ap->host_set->dev;
 261         struct pdc_port_priv *pp;
 262         int rc;
 263
 264         rc = ata_port_start(ap);
 265         if (rc)
 266                 return rc;
 267
 268         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 269         if (!pp) {
 270                 rc = -ENOMEM;
 271                 goto err_out;
 272         }
 273         memset(pp, 0, sizeof(*pp));
 274
 275         pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 276         if (!pp->pkt) {
 277                 rc = -ENOMEM;
 278                 goto err_out_kfree;
 279         }
 280
 281         ap->private_data = pp;
 282
 283         return 0;
 284
 285 err_out_kfree:
 286         kfree(pp);
 287 err_out:
 288         ata_port_stop(ap);
 289         return rc;
 290 }
 291
 292
 293 static void pdc_port_stop(struct ata_port *ap)
 294 {
 295         struct device *dev = ap->host_set->dev;
 296         struct pdc_port_priv *pp = ap->private_data;
 297
 298         ap->private_data = NULL;
 299         dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
 300         kfree(pp);
 301         ata_port_stop(ap);
 302 }
 303
 304
 305 static void pdc_20621_phy_reset (struct ata_port *ap)
 306 {
 307         VPRINTK("ENTER\n");
 308         ap->cbl = ATA_CBL_SATA;
 309         ata_port_probe(ap);
 310         ata_bus_reset(ap);
 311 }
 312
 313 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 314                                            unsigned int portno,
 315                                            unsigned int total_len)
 316 {
 317         u32 addr;
 318         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 319         u32 *buf32 = (u32 *) buf;
 320
 321         /* output ATA packet S/G table */
 322         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 323                (PDC_DIMM_DATA_STEP * portno);
 324         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 325         buf32[dw] = cpu_to_le32(addr);
 326         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 327
 328         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 329                 PDC_20621_DIMM_BASE +
 330                        (PDC_DIMM_WINDOW_STEP * portno) +
 331                        PDC_DIMM_APKT_PRD,
 332                 buf32[dw], buf32[dw + 1]);
 333 }
 334
 335 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 336                                             unsigned int portno,
 337                                             unsigned int total_len)
 338 {
 339         u32 addr;
 340         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 341         u32 *buf32 = (u32 *) buf;
 342
 343         /* output Host DMA packet S/G table */
 344         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 345                (PDC_DIMM_DATA_STEP * portno);
 346
 347         buf32[dw] = cpu_to_le32(addr);
 348         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 349
 350         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 351                 PDC_20621_DIMM_BASE +
 352                        (PDC_DIMM_WINDOW_STEP * portno) +
 353                        PDC_DIMM_HPKT_PRD,
 354                 buf32[dw], buf32[dw + 1]);
 355 }
 356
 357 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 358                                             unsigned int devno, u8 *buf,
 359                                             unsigned int portno)
 360 {
 361         unsigned int i, dw;
 362         u32 *buf32 = (u32 *) buf;
 363         u8 dev_reg;
 364
 365         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 366                                (PDC_DIMM_WINDOW_STEP * portno) +
 367                                PDC_DIMM_APKT_PRD;
 368         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 369
 370         i = PDC_DIMM_ATA_PKT;
 371
 372         /*
 373          * Set up ATA packet
 374          */
 375         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 376                 buf[i++] = PDC_PKT_READ;
 377         else if (tf->protocol == ATA_PROT_NODATA)
 378                 buf[i++] = PDC_PKT_NODATA;
 379         else
 380                 buf[i++] = 0;
 381         buf[i++] = 0;                   /* reserved */
 382         buf[i++] = portno + 1;          /* seq. id */
 383         buf[i++] = 0xff;                /* delay seq. id */
 384
 385         /* dimm dma S/G, and next-pkt */
 386         dw = i >> 2;
 387         if (tf->protocol == ATA_PROT_NODATA)
 388                 buf32[dw] = 0;
 389         else
 390                 buf32[dw] = cpu_to_le32(dimm_sg);
 391         buf32[dw + 1] = 0;
 392         i += 8;
 393
 394         if (devno == 0)
 395                 dev_reg = ATA_DEVICE_OBS;
 396         else
 397                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 398
 399         /* select device */
 400         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 401         buf[i++] = dev_reg;
 402
 403         /* device control register */
 404         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 405         buf[i++] = tf->ctl;
 406
 407         return i;
 408 }
 409
 410 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 411                                      unsigned int portno)
 412 {
 413         unsigned int dw;
 414         u32 tmp, *buf32 = (u32 *) buf;
 415
 416         unsigned int host_sg = PDC_20621_DIMM_BASE +
 417                                (PDC_DIMM_WINDOW_STEP * portno) +
 418                                PDC_DIMM_HOST_PRD;
 419         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 420                                (PDC_DIMM_WINDOW_STEP * portno) +
 421                                PDC_DIMM_HPKT_PRD;
 422         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 423         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 424
 425         dw = PDC_DIMM_HOST_PKT >> 2;
 426
 427         /*
 428          * Set up Host DMA packet
 429          */
 430         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 431                 tmp = PDC_PKT_READ;
 432         else
 433                 tmp = 0;
 434         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 435         tmp |= (0xff << 24);                    /* delay seq. id */
 436         buf32[dw + 0] = cpu_to_le32(tmp);
 437         buf32[dw + 1] = cpu_to_le32(host_sg);
 438         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 439         buf32[dw + 3] = 0;
 440
 441         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 442                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 443                         PDC_DIMM_HOST_PKT,
 444                 buf32[dw + 0],
 445                 buf32[dw + 1],
 446                 buf32[dw + 2],
 447                 buf32[dw + 3]);
 448 }
 449
 450 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 451 {
 452         struct scatterlist *sg;
 453         struct ata_port *ap = qc->ap;
 454         struct pdc_port_priv *pp = ap->private_data;
 455         void __iomem *mmio = ap->host_set->mmio_base;
 456         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 457         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 458         unsigned int portno = ap->port_no;
 459         unsigned int i, idx, total_len = 0, sgt_len;
 460         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 461
 462         WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
 463
 464         VPRINTK("ata%u: ENTER\n", ap->id);
 465
 466         /* hard-code chip #0 */
 467         mmio += PDC_CHIP0_OFS;
 468
 469         /*
 470          * Build S/G table
 471          */
 472         idx = 0;
 473         ata_for_each_sg(sg, qc) {
 474                 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
 475                 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
 476                 total_len += sg_dma_len(sg);
 477         }
 478         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 479         sgt_len = idx * 4;
 480
 481         /*
 482          * Build ATA, host DMA packets
 483          */
 484         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 485         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 486
 487         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 488         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 489
 490         if (qc->tf.flags & ATA_TFLAG_LBA48)
 491                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 492         else
 493                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 494
 495         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 496
 497         /* copy three S/G tables and two packets to DIMM MMIO window */
 498         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 499                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 500         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 501                     PDC_DIMM_HOST_PRD,
 502                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 503
 504         /* force host FIFO dump */
 505         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 506
 507         readl(dimm_mmio);       /* MMIO PCI posting flush */
 508
 509         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 510 }
 511
 512 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 513 {
 514         struct ata_port *ap = qc->ap;
 515         struct pdc_port_priv *pp = ap->private_data;
 516         void __iomem *mmio = ap->host_set->mmio_base;
 517         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 518         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 519         unsigned int portno = ap->port_no;
 520         unsigned int i;
 521
 522         VPRINTK("ata%u: ENTER\n", ap->id);
 523
 524         /* hard-code chip #0 */
 525         mmio += PDC_CHIP0_OFS;
 526
 527         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 528
 529         if (qc->tf.flags & ATA_TFLAG_LBA48)
 530                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 531         else
 532                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 533
 534         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 535
 536         /* copy three S/G tables and two packets to DIMM MMIO window */
 537         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 538                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 539
 540         /* force host FIFO dump */
 541         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 542
 543         readl(dimm_mmio);       /* MMIO PCI posting flush */
 544
 545         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 546 }
 547
 548 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 549 {
 550         switch (qc->tf.protocol) {
 551         case ATA_PROT_DMA:
 552                 pdc20621_dma_prep(qc);
 553                 break;
 554         case ATA_PROT_NODATA:
 555                 pdc20621_nodata_prep(qc);
 556                 break;
 557         default:
 558                 break;
 559         }
 560 }
 561
 562 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 563                                  unsigned int seq,
 564                                  u32 pkt_ofs)
 565 {
 566         struct ata_port *ap = qc->ap;
 567         struct ata_host_set *host_set = ap->host_set;
 568         void __iomem *mmio = host_set->mmio_base;
 569
 570         /* hard-code chip #0 */
 571         mmio += PDC_CHIP0_OFS;
 572
 573         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 574         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 575
 576         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 577         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 578 }
 579
 580 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 581                                 unsigned int seq,
 582                                 u32 pkt_ofs)
 583 {
 584         struct ata_port *ap = qc->ap;
 585         struct pdc_host_priv *pp = ap->host_set->private_data;
 586         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 587
 588         if (!pp->doing_hdma) {
 589                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 590                 pp->doing_hdma = 1;
 591                 return;
 592         }
 593
 594         pp->hdma[idx].qc = qc;
 595         pp->hdma[idx].seq = seq;
 596         pp->hdma[idx].pkt_ofs = pkt_ofs;
 597         pp->hdma_prod++;
 598 }
 599
 600 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 601 {
 602         struct ata_port *ap = qc->ap;
 603         struct pdc_host_priv *pp = ap->host_set->private_data;
 604         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 605
 606         /* if nothing on queue, we're done */
 607         if (pp->hdma_prod == pp->hdma_cons) {
 608                 pp->doing_hdma = 0;
 609                 return;
 610         }
 611
 612         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 613                              pp->hdma[idx].pkt_ofs);
 614         pp->hdma_cons++;
 615 }
 616
 617 #ifdef ATA_VERBOSE_DEBUG
 618 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 619 {
 620         struct ata_port *ap = qc->ap;
 621         unsigned int port_no = ap->port_no;
 622         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 623         void *dimm_mmio = hpriv->dimm_mmio;
 624
 625         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 626         dimm_mmio += PDC_DIMM_HOST_PKT;
 627
 628         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 629         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 630         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 631         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 632 }
 633 #else
 634 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 635 #endif /* ATA_VERBOSE_DEBUG */
 636
 637 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 638 {
 639         struct ata_port *ap = qc->ap;
 640         struct ata_host_set *host_set = ap->host_set;
 641         unsigned int port_no = ap->port_no;
 642         void __iomem *mmio = host_set->mmio_base;
 643         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 644         u8 seq = (u8) (port_no + 1);
 645         unsigned int port_ofs;
 646
 647         /* hard-code chip #0 */
 648         mmio += PDC_CHIP0_OFS;
 649
 650         VPRINTK("ata%u: ENTER\n", ap->id);
 651
 652         wmb();                  /* flush PRD, pkt writes */
 653
 654         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 655
 656         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 657         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 658                 seq += 4;
 659
 660                 pdc20621_dump_hdma(qc);
 661                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 662                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 663                         port_ofs + PDC_DIMM_HOST_PKT,
 664                         port_ofs + PDC_DIMM_HOST_PKT,
 665                         seq);
 666         } else {
 667                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 668                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 669
 670                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 671                        (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 672                 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 673                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 674                         port_ofs + PDC_DIMM_ATA_PKT,
 675                         port_ofs + PDC_DIMM_ATA_PKT,
 676                         seq);
 677         }
 678 }
 679
 680 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 681 {
 682         switch (qc->tf.protocol) {
 683         case ATA_PROT_DMA:
 684         case ATA_PROT_NODATA:
 685                 pdc20621_packet_start(qc);
 686                 return 0;
 687
 688         case ATA_PROT_ATAPI_DMA:
 689                 BUG();
 690                 break;
 691
 692         default:
 693                 break;
 694         }
 695
 696         return ata_qc_issue_prot(qc);
 697 }
 698
 699 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 700                                           struct ata_queued_cmd *qc,
 701                                           unsigned int doing_hdma,
 702                                           void __iomem *mmio)
 703 {
 704         unsigned int port_no = ap->port_no;
 705         unsigned int port_ofs =
 706                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 707         u8 status;
 708         unsigned int handled = 0;
 709
 710         VPRINTK("ENTER\n");
 711
 712         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 713             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 714
 715                 /* step two - DMA from DIMM to host */
 716                 if (doing_hdma) {
 717                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 718                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 719                         /* get drive status; clear intr; complete txn */
 720                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 721                         ata_qc_complete(qc);
 722                         pdc20621_pop_hdma(qc);
 723                 }
 724
 725                 /* step one - exec ATA command */
 726                 else {
 727                         u8 seq = (u8) (port_no + 1 + 4);
 728                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 729                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 730
 731                         /* submit hdma pkt */
 732                         pdc20621_dump_hdma(qc);
 733                         pdc20621_push_hdma(qc, seq,
 734                                            port_ofs + PDC_DIMM_HOST_PKT);
 735                 }
 736                 handled = 1;
 737
 738         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 739
 740                 /* step one - DMA from host to DIMM */
 741                 if (doing_hdma) {
 742                         u8 seq = (u8) (port_no + 1);
 743                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 744                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 745
 746                         /* submit ata pkt */
 747                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 748                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 749                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 750                                (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 751                         readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 752                 }
 753
 754                 /* step two - execute ATA command */
 755                 else {
 756                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 757                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 758                         /* get drive status; clear intr; complete txn */
 759                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 760                         ata_qc_complete(qc);
 761                         pdc20621_pop_hdma(qc);
 762                 }
 763                 handled = 1;
 764
 765         /* command completion, but no data xfer */
 766         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 767
 768                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 769                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 770                 qc->err_mask |= ac_err_mask(status);
 771                 ata_qc_complete(qc);
 772                 handled = 1;
 773
 774         } else {
 775                 ap->stats.idle_irq++;
 776         }
 777
 778         return handled;
 779 }
 780
 781 static void pdc20621_irq_clear(struct ata_port *ap)
 782 {
 783         struct ata_host_set *host_set = ap->host_set;
 784         void __iomem *mmio = host_set->mmio_base;
 785
 786         mmio += PDC_CHIP0_OFS;
 787
 788         readl(mmio + PDC_20621_SEQMASK);
 789 }
 790
 791 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 792 {
 793         struct ata_host_set *host_set = dev_instance;
 794         struct ata_port *ap;
 795         u32 mask = 0;
 796         unsigned int i, tmp, port_no;
 797         unsigned int handled = 0;
 798         void __iomem *mmio_base;
 799
 800         VPRINTK("ENTER\n");
 801
 802         if (!host_set || !host_set->mmio_base) {
 803                 VPRINTK("QUICK EXIT\n");
 804                 return IRQ_NONE;
 805         }
 806
 807         mmio_base = host_set->mmio_base;
 808
 809         /* reading should also clear interrupts */
 810         mmio_base += PDC_CHIP0_OFS;
 811         mask = readl(mmio_base + PDC_20621_SEQMASK);
 812         VPRINTK("mask == 0x%x\n", mask);
 813
 814         if (mask == 0xffffffff) {
 815                 VPRINTK("QUICK EXIT 2\n");
 816                 return IRQ_NONE;
 817         }
 818         mask &= 0xffff;         /* only 16 tags possible */
 819         if (!mask) {
 820                 VPRINTK("QUICK EXIT 3\n");
 821                 return IRQ_NONE;
 822         }
 823
 824         spin_lock(&host_set->lock);
 825
 826         for (i = 1; i < 9; i++) {
 827                 port_no = i - 1;
 828                 if (port_no > 3)
 829                         port_no -= 4;
 830                 if (port_no >= host_set->n_ports)
 831                         ap = NULL;
 832                 else
 833                         ap = host_set->ports[port_no];
 834                 tmp = mask & (1 << i);
 835                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 836                 if (tmp && ap &&
 837                     !(ap->flags & ATA_FLAG_DISABLED)) {
 838                         struct ata_queued_cmd *qc;
 839
 840                         qc = ata_qc_from_tag(ap, ap->active_tag);
 841                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
 842                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 843                                                               mmio_base);
 844                 }
 845         }
 846
 847         spin_unlock(&host_set->lock);
 848
 849         VPRINTK("mask == 0x%x\n", mask);
 850
 851         VPRINTK("EXIT\n");
 852
 853         return IRQ_RETVAL(handled);
 854 }
 855
 856 static void pdc_eng_timeout(struct ata_port *ap)
 857 {
 858         u8 drv_stat;
 859         struct ata_host_set *host_set = ap->host_set;
 860         struct ata_queued_cmd *qc;
 861         unsigned long flags;
 862
 863         DPRINTK("ENTER\n");
 864
 865         spin_lock_irqsave(&host_set->lock, flags);
 866
 867         qc = ata_qc_from_tag(ap, ap->active_tag);
 868
 869         switch (qc->tf.protocol) {
 870         case ATA_PROT_DMA:
 871         case ATA_PROT_NODATA:
 872                 ata_port_printk(ap, KERN_ERR, "command timeout\n");
 873                 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
 874                 break;
 875
 876         default:
 877                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 878
 879                 ata_port_printk(ap, KERN_ERR,
 880                                 "unknown timeout, cmd 0x%x stat 0x%x\n",
 881                                 qc->tf.command, drv_stat);
 882
 883                 qc->err_mask |= ac_err_mask(drv_stat);
 884                 break;
 885         }
 886
 887         spin_unlock_irqrestore(&host_set->lock, flags);
 888         ata_eh_qc_complete(qc);
 889         DPRINTK("EXIT\n");
 890 }
 891
 892 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 893 {
 894         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 895                  tf->protocol == ATA_PROT_NODATA);
 896         ata_tf_load(ap, tf);
 897 }
 898
 899
 900 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 901 {
 902         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 903                  tf->protocol == ATA_PROT_NODATA);
 904         ata_exec_command(ap, tf);
 905 }
 906
 907
 908 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 909 {
 910         port->cmd_addr          = base;
 911         port->data_addr         = base;
 912         port->feature_addr      =
 913         port->error_addr        = base + 0x4;
 914         port->nsect_addr        = base + 0x8;
 915         port->lbal_addr         = base + 0xc;
 916         port->lbam_addr         = base + 0x10;
 917         port->lbah_addr         = base + 0x14;
 918         port->device_addr       = base + 0x18;
 919         port->command_addr      =
 920         port->status_addr       = base + 0x1c;
 921         port->altstatus_addr    =
 922         port->ctl_addr          = base + 0x38;
 923 }
 924
 925
 926 #ifdef ATA_VERBOSE_DEBUG
 927 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 928                                    u32 offset, u32 size)
 929 {
 930         u32 window_size;
 931         u16 idx;
 932         u8 page_mask;
 933         long dist;
 934         void __iomem *mmio = pe->mmio_base;
 935         struct pdc_host_priv *hpriv = pe->private_data;
 936         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 937
 938         /* hard-code chip #0 */
 939         mmio += PDC_CHIP0_OFS;
 940
 941         page_mask = 0x00;
 942         window_size = 0x2000 * 4; /* 32K byte uchar size */
 943         idx = (u16) (offset / window_size);
 944
 945         writel(0x01, mmio + PDC_GENERAL_CTLR);
 946         readl(mmio + PDC_GENERAL_CTLR);
 947         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 948         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 949
 950         offset -= (idx * window_size);
 951         idx++;
 952         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 953                 (long) (window_size - offset);
 954         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 955                       dist);
 956
 957         psource += dist;
 958         size -= dist;
 959         for (; (long) size >= (long) window_size ;) {
 960                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 961                 readl(mmio + PDC_GENERAL_CTLR);
 962                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 963                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 964                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 965                               window_size / 4);
 966                 psource += window_size;
 967                 size -= window_size;
 968                 idx ++;
 969         }
 970
 971         if (size) {
 972                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 973                 readl(mmio + PDC_GENERAL_CTLR);
 974                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 975                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 976                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 977                               size / 4);
 978         }
 979 }
 980 #endif
 981
 982
 983 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 984                                  u32 offset, u32 size)
 985 {
 986         u32 window_size;
 987         u16 idx;
 988         u8 page_mask;
 989         long dist;
 990         void __iomem *mmio = pe->mmio_base;
 991         struct pdc_host_priv *hpriv = pe->private_data;
 992         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 993
 994         /* hard-code chip #0 */
 995         mmio += PDC_CHIP0_OFS;
 996
 997         page_mask = 0x00;
 998         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 999         idx = (u16) (offset / window_size);
1000
1001         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1002         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1003         offset -= (idx * window_size);
1004         idx++;
1005         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1006                 (long) (window_size - offset);
1007         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1008         writel(0x01, mmio + PDC_GENERAL_CTLR);
1009         readl(mmio + PDC_GENERAL_CTLR);
1010
1011         psource += dist;
1012         size -= dist;
1013         for (; (long) size >= (long) window_size ;) {
1014                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1015                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1016                 memcpy_toio(dimm_mmio, psource, window_size / 4);
1017                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1018                 readl(mmio + PDC_GENERAL_CTLR);
1019                 psource += window_size;
1020                 size -= window_size;
1021                 idx ++;
1022         }
1023
1024         if (size) {
1025                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1026                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1027                 memcpy_toio(dimm_mmio, psource, size / 4);
1028                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1029                 readl(mmio + PDC_GENERAL_CTLR);
1030         }
1031 }
1032
1033
1034 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1035                                       u32 subaddr, u32 *pdata)
1036 {
1037         void __iomem *mmio = pe->mmio_base;
1038         u32 i2creg  = 0;
1039         u32 status;
1040         u32 count =0;
1041
1042         /* hard-code chip #0 */
1043         mmio += PDC_CHIP0_OFS;
1044
1045         i2creg |= device << 24;
1046         i2creg |= subaddr << 16;
1047
1048         /* Set the device and subaddress */
1049         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1050         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1051
1052         /* Write Control to perform read operation, mask int */
1053         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1054                mmio + PDC_I2C_CONTROL_OFFSET);
1055
1056         for (count = 0; count <= 1000; count ++) {
1057                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1058                 if (status & PDC_I2C_COMPLETE) {
1059                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1060                         break;
1061                 } else if (count == 1000)
1062                         return 0;
1063         }
1064
1065         *pdata = (status >> 8) & 0x000000ff;
1066         return 1;
1067 }
1068
1069
1070 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1071 {
1072         u32 data=0 ;
1073         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1074                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1075                 if (data == 100)
1076                         return 100;
1077         } else
1078                 return 0;
1079
1080         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1081                 if(data <= 0x75)
1082                         return 133;
1083         } else
1084                 return 0;
1085
1086         return 0;
1087 }
1088
1089
1090 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1091 {
1092         u32 spd0[50];
1093         u32 data = 0;
1094         int size, i;
1095         u8 bdimmsize;
1096         void __iomem *mmio = pe->mmio_base;
1097         static const struct {
1098                 unsigned int reg;
1099                 unsigned int ofs;
1100         } pdc_i2c_read_data [] = {
1101                 { PDC_DIMM_SPD_TYPE, 11 },
1102                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1103                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1104                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1105                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1106                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1107                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1108                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1109                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1110                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1111                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1112                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1113         };
1114
1115         /* hard-code chip #0 */
1116         mmio += PDC_CHIP0_OFS;
1117
1118         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1119                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1120                                   pdc_i2c_read_data[i].reg,
1121                                   &spd0[pdc_i2c_read_data[i].ofs]);
1122
1123         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1124         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1125                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1126         data |= (((((spd0[29] > spd0[28])
1127                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1128         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1129
1130         if (spd0[18] & 0x08)
1131                 data |= ((0x03) << 14);
1132         else if (spd0[18] & 0x04)
1133                 data |= ((0x02) << 14);
1134         else if (spd0[18] & 0x01)
1135                 data |= ((0x01) << 14);
1136         else
1137                 data |= (0 << 14);
1138
1139         /*
1140            Calculate the size of bDIMMSize (power of 2) and
1141            merge the DIMM size by program start/end address.
1142         */
1143
1144         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1145         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1146         data |= (((size / 16) - 1) << 16);
1147         data |= (0 << 23);
1148         data |= 8;
1149         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1150         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1151         return size;
1152 }
1153
1154
1155 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1156 {
1157         u32 data, spd0;
1158         int error, i;
1159         void __iomem *mmio = pe->mmio_base;
1160
1161         /* hard-code chip #0 */
1162         mmio += PDC_CHIP0_OFS;
1163
1164         /*
1165           Set To Default : DIMM Module Global Control Register (0x022259F1)
1166           DIMM Arbitration Disable (bit 20)
1167           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1168           Refresh Enable (bit 17)
1169         */
1170
1171         data = 0x022259F1;
1172         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1173         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1174
1175         /* Turn on for ECC */
1176         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1177                           PDC_DIMM_SPD_TYPE, &spd0);
1178         if (spd0 == 0x02) {
1179                 data |= (0x01 << 16);
1180                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1181                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1182                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1183         }
1184
1185         /* DIMM Initialization Select/Enable (bit 18/19) */
1186         data &= (~(1<<18));
1187         data |= (1<<19);
1188         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1189
1190         error = 1;
1191         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1192                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1193                 if (!(data & (1<<19))) {
1194                         error = 0;
1195                         break;
1196                 }
1197                 msleep(i*100);
1198         }
1199         return error;
1200 }
1201
1202
1203 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1204 {
1205         int speed, size, length;
1206         u32 addr,spd0,pci_status;
1207         u32 tmp=0;
1208         u32 time_period=0;
1209         u32 tcount=0;
1210         u32 ticks=0;
1211         u32 clock=0;
1212         u32 fparam=0;
1213         void __iomem *mmio = pe->mmio_base;
1214
1215         /* hard-code chip #0 */
1216         mmio += PDC_CHIP0_OFS;
1217
1218         /* Initialize PLL based upon PCI Bus Frequency */
1219
1220         /* Initialize Time Period Register */
1221         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1222         time_period = readl(mmio + PDC_TIME_PERIOD);
1223         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1224
1225         /* Enable timer */
1226         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1227         readl(mmio + PDC_TIME_CONTROL);
1228
1229         /* Wait 3 seconds */
1230         msleep(3000);
1231
1232         /*
1233            When timer is enabled, counter is decreased every internal
1234            clock cycle.
1235         */
1236
1237         tcount = readl(mmio + PDC_TIME_COUNTER);
1238         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1239
1240         /*
1241            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1242            register should be >= (0xffffffff - 3x10^8).
1243         */
1244         if(tcount >= PCI_X_TCOUNT) {
1245                 ticks = (time_period - tcount);
1246                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1247
1248                 clock = (ticks / 300000);
1249                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1250
1251                 clock = (clock * 33);
1252                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1253
1254                 /* PLL F Param (bit 22:16) */
1255                 fparam = (1400000 / clock) - 2;
1256                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1257
1258                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1259                 pci_status = (0x8a001824 | (fparam << 16));
1260         } else
1261                 pci_status = PCI_PLL_INIT;
1262
1263         /* Initialize PLL. */
1264         VPRINTK("pci_status: 0x%x\n", pci_status);
1265         writel(pci_status, mmio + PDC_CTL_STATUS);
1266         readl(mmio + PDC_CTL_STATUS);
1267
1268         /*
1269            Read SPD of DIMM by I2C interface,
1270            and program the DIMM Module Controller.
1271         */
1272         if (!(speed = pdc20621_detect_dimm(pe))) {
1273                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1274                 return 1;       /* DIMM error */
1275         }
1276         VPRINTK("Local DIMM Speed = %d\n", speed);
1277
1278         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1279         size = pdc20621_prog_dimm0(pe);
1280         VPRINTK("Local DIMM Size = %dMB\n",size);
1281
1282         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1283         if (pdc20621_prog_dimm_global(pe)) {
1284                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1285                 return 1;
1286         }
1287
1288 #ifdef ATA_VERBOSE_DEBUG
1289         {
1290                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1291                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1292                                  '1','.','1','0',
1293                                 '9','8','0','3','1','6','1','2',0,0};
1294                 u8 test_parttern2[40] = {0};
1295
1296                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1297                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1298
1299                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1300                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1301                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1302                        test_parttern2[1], &(test_parttern2[2]));
1303                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1304                                        40);
1305                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1306                        test_parttern2[1], &(test_parttern2[2]));
1307
1308                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1309                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1310                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1311                        test_parttern2[1], &(test_parttern2[2]));
1312         }
1313 #endif
1314
1315         /* ECC initiliazation. */
1316
1317         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1318                           PDC_DIMM_SPD_TYPE, &spd0);
1319         if (spd0 == 0x02) {
1320                 VPRINTK("Start ECC initialization\n");
1321                 addr = 0;
1322                 length = size * 1024 * 1024;
1323                 while (addr < length) {
1324                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1325                                              sizeof(u32));
1326                         addr += sizeof(u32);
1327                 }
1328                 VPRINTK("Finish ECC initialization\n");
1329         }
1330         return 0;
1331 }
1332
1333
1334 static void pdc_20621_init(struct ata_probe_ent *pe)
1335 {
1336         u32 tmp;
1337         void __iomem *mmio = pe->mmio_base;
1338
1339         /* hard-code chip #0 */
1340         mmio += PDC_CHIP0_OFS;
1341
1342         /*
1343          * Select page 0x40 for our 32k DIMM window
1344          */
1345         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1346         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1347         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1348
1349         /*
1350          * Reset Host DMA
1351          */
1352         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1353         tmp |= PDC_RESET;
1354         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1355         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1356
1357         udelay(10);
1358
1359         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1360         tmp &= ~PDC_RESET;
1361         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1362         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1363 }
1364
1365 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1366 {
1367         static int printed_version;
1368         struct ata_probe_ent *probe_ent = NULL;
1369         unsigned long base;
1370         void __iomem *mmio_base;
1371         void __iomem *dimm_mmio = NULL;
1372         struct pdc_host_priv *hpriv = NULL;
1373         unsigned int board_idx = (unsigned int) ent->driver_data;
1374         int pci_dev_busy = 0;
1375         int rc;
1376
1377         if (!printed_version++)
1378                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1379
1380         rc = pci_enable_device(pdev);
1381         if (rc)
1382                 return rc;
1383
1384         rc = pci_request_regions(pdev, DRV_NAME);
1385         if (rc) {
1386                 pci_dev_busy = 1;
1387                 goto err_out;
1388         }
1389
1390         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1391         if (rc)
1392                 goto err_out_regions;
1393         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1394         if (rc)
1395                 goto err_out_regions;
1396
1397         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1398         if (probe_ent == NULL) {
1399                 rc = -ENOMEM;
1400                 goto err_out_regions;
1401         }
1402
1403         memset(probe_ent, 0, sizeof(*probe_ent));
1404         probe_ent->dev = pci_dev_to_dev(pdev);
1405         INIT_LIST_HEAD(&probe_ent->node);
1406
1407         mmio_base = pci_iomap(pdev, 3, 0);
1408         if (mmio_base == NULL) {
1409                 rc = -ENOMEM;
1410                 goto err_out_free_ent;
1411         }
1412         base = (unsigned long) mmio_base;
1413
1414         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1415         if (!hpriv) {
1416                 rc = -ENOMEM;
1417                 goto err_out_iounmap;
1418         }
1419         memset(hpriv, 0, sizeof(*hpriv));
1420
1421         dimm_mmio = pci_iomap(pdev, 4, 0);
1422         if (!dimm_mmio) {
1423                 kfree(hpriv);
1424                 rc = -ENOMEM;
1425                 goto err_out_iounmap;
1426         }
1427
1428         hpriv->dimm_mmio = dimm_mmio;
1429
1430         probe_ent->sht          = pdc_port_info[board_idx].sht;
1431         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1432         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1433         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1434         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1435         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1436
1437         probe_ent->irq = pdev->irq;
1438         probe_ent->irq_flags = SA_SHIRQ;
1439         probe_ent->mmio_base = mmio_base;
1440
1441         probe_ent->private_data = hpriv;
1442         base += PDC_CHIP0_OFS;
1443
1444         probe_ent->n_ports = 4;
1445         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1446         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1447         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1448         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1449
1450         pci_set_master(pdev);
1451
1452         /* initialize adapter */
1453         /* initialize local dimm */
1454         if (pdc20621_dimm_init(probe_ent)) {
1455                 rc = -ENOMEM;
1456                 goto err_out_iounmap_dimm;
1457         }
1458         pdc_20621_init(probe_ent);
1459
1460         /* FIXME: check ata_device_add return value */
1461         ata_device_add(probe_ent);
1462         kfree(probe_ent);
1463
1464         return 0;
1465
1466 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1467         kfree(hpriv);
1468         pci_iounmap(pdev, dimm_mmio);
1469 err_out_iounmap:
1470         pci_iounmap(pdev, mmio_base);
1471 err_out_free_ent:
1472         kfree(probe_ent);
1473 err_out_regions:
1474         pci_release_regions(pdev);
1475 err_out:
1476         if (!pci_dev_busy)
1477                 pci_disable_device(pdev);
1478         return rc;
1479 }
1480
1481
1482 static int __init pdc_sata_init(void)
1483 {
1484         return pci_module_init(&pdc_sata_pci_driver);
1485 }
1486
1487
1488 static void __exit pdc_sata_exit(void)
1489 {
1490         pci_unregister_driver(&pdc_sata_pci_driver);
1491 }
1492
1493
1494 MODULE_AUTHOR("Jeff Garzik");
1495 MODULE_DESCRIPTION("Promise SATA low-level driver");
1496 MODULE_LICENSE("GPL");
1497 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1498 MODULE_VERSION(DRV_VERSION);
1499
1500 module_init(pdc_sata_init);
1501 module_exit(pdc_sata_exit);