Merge branch 'for-linus' of git://neil.brown.name/md
[linux-2.6] / drivers / crypto / talitos.c
1 /*
2  * talitos - Freescale Integrated Security Engine (SEC) device driver
3  *
4  * Copyright (c) 2008 Freescale Semiconductor, Inc.
5  *
6  * Scatterlist Crypto API glue code copied from files with the following:
7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8  *
9  * Crypto algorithm registration code copied from hifn driver:
10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11  * All rights reserved.
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
26  */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
33 #include <linux/crypto.h>
34 #include <linux/hw_random.h>
35 #include <linux/of_platform.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/io.h>
38 #include <linux/spinlock.h>
39 #include <linux/rtnetlink.h>
40
41 #include <crypto/algapi.h>
42 #include <crypto/aes.h>
43 #include <crypto/des.h>
44 #include <crypto/sha.h>
45 #include <crypto/aead.h>
46 #include <crypto/authenc.h>
47
48 #include "talitos.h"
49
50 #define TALITOS_TIMEOUT 100000
51 #define TALITOS_MAX_DATA_LEN 65535
52
53 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
54 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
55 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
56
57 /* descriptor pointer entry */
58 struct talitos_ptr {
59         __be16 len;     /* length */
60         u8 j_extent;    /* jump to sg link table and/or extent */
61         u8 eptr;        /* extended address */
62         __be32 ptr;     /* address */
63 };
64
65 /* descriptor */
66 struct talitos_desc {
67         __be32 hdr;                     /* header high bits */
68         __be32 hdr_lo;                  /* header low bits */
69         struct talitos_ptr ptr[7];      /* ptr/len pair array */
70 };
71
72 /**
73  * talitos_request - descriptor submission request
74  * @desc: descriptor pointer (kernel virtual)
75  * @dma_desc: descriptor's physical bus address
76  * @callback: whom to call when descriptor processing is done
77  * @context: caller context (optional)
78  */
79 struct talitos_request {
80         struct talitos_desc *desc;
81         dma_addr_t dma_desc;
82         void (*callback) (struct device *dev, struct talitos_desc *desc,
83                           void *context, int error);
84         void *context;
85 };
86
87 struct talitos_private {
88         struct device *dev;
89         struct of_device *ofdev;
90         void __iomem *reg;
91         int irq;
92
93         /* SEC version geometry (from device tree node) */
94         unsigned int num_channels;
95         unsigned int chfifo_len;
96         unsigned int exec_units;
97         unsigned int desc_types;
98
99         /* next channel to be assigned next incoming descriptor */
100         atomic_t last_chan;
101
102         /* per-channel request fifo */
103         struct talitos_request **fifo;
104
105         /*
106          * length of the request fifo
107          * fifo_len is chfifo_len rounded up to next power of 2
108          * so we can use bitwise ops to wrap
109          */
110         unsigned int fifo_len;
111
112         /* per-channel index to next free descriptor request */
113         int *head;
114
115         /* per-channel index to next in-progress/done descriptor request */
116         int *tail;
117
118         /* per-channel request submission (head) and release (tail) locks */
119         spinlock_t *head_lock;
120         spinlock_t *tail_lock;
121
122         /* request callback tasklet */
123         struct tasklet_struct done_task;
124         struct tasklet_struct error_task;
125
126         /* list of registered algorithms */
127         struct list_head alg_list;
128
129         /* hwrng device */
130         struct hwrng rng;
131 };
132
133 /*
134  * map virtual single (contiguous) pointer to h/w descriptor pointer
135  */
136 static void map_single_talitos_ptr(struct device *dev,
137                                    struct talitos_ptr *talitos_ptr,
138                                    unsigned short len, void *data,
139                                    unsigned char extent,
140                                    enum dma_data_direction dir)
141 {
142         talitos_ptr->len = cpu_to_be16(len);
143         talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
144         talitos_ptr->j_extent = extent;
145 }
146
147 /*
148  * unmap bus single (contiguous) h/w descriptor pointer
149  */
150 static void unmap_single_talitos_ptr(struct device *dev,
151                                      struct talitos_ptr *talitos_ptr,
152                                      enum dma_data_direction dir)
153 {
154         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
155                          be16_to_cpu(talitos_ptr->len), dir);
156 }
157
158 static int reset_channel(struct device *dev, int ch)
159 {
160         struct talitos_private *priv = dev_get_drvdata(dev);
161         unsigned int timeout = TALITOS_TIMEOUT;
162
163         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
164
165         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
166                && --timeout)
167                 cpu_relax();
168
169         if (timeout == 0) {
170                 dev_err(dev, "failed to reset channel %d\n", ch);
171                 return -EIO;
172         }
173
174         /* set done writeback and IRQ */
175         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
176                   TALITOS_CCCR_LO_CDIE);
177
178         return 0;
179 }
180
181 static int reset_device(struct device *dev)
182 {
183         struct talitos_private *priv = dev_get_drvdata(dev);
184         unsigned int timeout = TALITOS_TIMEOUT;
185
186         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
187
188         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
189                && --timeout)
190                 cpu_relax();
191
192         if (timeout == 0) {
193                 dev_err(dev, "failed to reset device\n");
194                 return -EIO;
195         }
196
197         return 0;
198 }
199
200 /*
201  * Reset and initialize the device
202  */
203 static int init_device(struct device *dev)
204 {
205         struct talitos_private *priv = dev_get_drvdata(dev);
206         int ch, err;
207
208         /*
209          * Master reset
210          * errata documentation: warning: certain SEC interrupts
211          * are not fully cleared by writing the MCR:SWR bit,
212          * set bit twice to completely reset
213          */
214         err = reset_device(dev);
215         if (err)
216                 return err;
217
218         err = reset_device(dev);
219         if (err)
220                 return err;
221
222         /* reset channels */
223         for (ch = 0; ch < priv->num_channels; ch++) {
224                 err = reset_channel(dev, ch);
225                 if (err)
226                         return err;
227         }
228
229         /* enable channel done and error interrupts */
230         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
231         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
232
233         return 0;
234 }
235
236 /**
237  * talitos_submit - submits a descriptor to the device for processing
238  * @dev:        the SEC device to be used
239  * @desc:       the descriptor to be processed by the device
240  * @callback:   whom to call when processing is complete
241  * @context:    a handle for use by caller (optional)
242  *
243  * desc must contain valid dma-mapped (bus physical) address pointers.
244  * callback must check err and feedback in descriptor header
245  * for device processing status.
246  */
247 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
248                           void (*callback)(struct device *dev,
249                                            struct talitos_desc *desc,
250                                            void *context, int error),
251                           void *context)
252 {
253         struct talitos_private *priv = dev_get_drvdata(dev);
254         struct talitos_request *request;
255         unsigned long flags, ch;
256         int head;
257
258         /* select done notification */
259         desc->hdr |= DESC_HDR_DONE_NOTIFY;
260
261         /* emulate SEC's round-robin channel fifo polling scheme */
262         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
263
264         spin_lock_irqsave(&priv->head_lock[ch], flags);
265
266         head = priv->head[ch];
267         request = &priv->fifo[ch][head];
268
269         if (request->desc) {
270                 /* request queue is full */
271                 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
272                 return -EAGAIN;
273         }
274
275         /* map descriptor and save caller data */
276         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
277                                            DMA_BIDIRECTIONAL);
278         request->callback = callback;
279         request->context = context;
280
281         /* increment fifo head */
282         priv->head[ch] = (priv->head[ch] + 1) & (priv->fifo_len - 1);
283
284         smp_wmb();
285         request->desc = desc;
286
287         /* GO! */
288         wmb();
289         out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
290
291         spin_unlock_irqrestore(&priv->head_lock[ch], flags);
292
293         return -EINPROGRESS;
294 }
295
296 /*
297  * process what was done, notify callback of error if not
298  */
299 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
300 {
301         struct talitos_private *priv = dev_get_drvdata(dev);
302         struct talitos_request *request, saved_req;
303         unsigned long flags;
304         int tail, status;
305
306         spin_lock_irqsave(&priv->tail_lock[ch], flags);
307
308         tail = priv->tail[ch];
309         while (priv->fifo[ch][tail].desc) {
310                 request = &priv->fifo[ch][tail];
311
312                 /* descriptors with their done bits set don't get the error */
313                 rmb();
314                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
315                         status = 0;
316                 else
317                         if (!error)
318                                 break;
319                         else
320                                 status = error;
321
322                 dma_unmap_single(dev, request->dma_desc,
323                         sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
324
325                 /* copy entries so we can call callback outside lock */
326                 saved_req.desc = request->desc;
327                 saved_req.callback = request->callback;
328                 saved_req.context = request->context;
329
330                 /* release request entry in fifo */
331                 smp_wmb();
332                 request->desc = NULL;
333
334                 /* increment fifo tail */
335                 priv->tail[ch] = (tail + 1) & (priv->fifo_len - 1);
336
337                 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
338                 saved_req.callback(dev, saved_req.desc, saved_req.context,
339                                    status);
340                 /* channel may resume processing in single desc error case */
341                 if (error && !reset_ch && status == error)
342                         return;
343                 spin_lock_irqsave(&priv->tail_lock[ch], flags);
344                 tail = priv->tail[ch];
345         }
346
347         spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
348 }
349
350 /*
351  * process completed requests for channels that have done status
352  */
353 static void talitos_done(unsigned long data)
354 {
355         struct device *dev = (struct device *)data;
356         struct talitos_private *priv = dev_get_drvdata(dev);
357         int ch;
358
359         for (ch = 0; ch < priv->num_channels; ch++)
360                 flush_channel(dev, ch, 0, 0);
361 }
362
363 /*
364  * locate current (offending) descriptor
365  */
366 static struct talitos_desc *current_desc(struct device *dev, int ch)
367 {
368         struct talitos_private *priv = dev_get_drvdata(dev);
369         int tail = priv->tail[ch];
370         dma_addr_t cur_desc;
371
372         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
373
374         while (priv->fifo[ch][tail].dma_desc != cur_desc) {
375                 tail = (tail + 1) & (priv->fifo_len - 1);
376                 if (tail == priv->tail[ch]) {
377                         dev_err(dev, "couldn't locate current descriptor\n");
378                         return NULL;
379                 }
380         }
381
382         return priv->fifo[ch][tail].desc;
383 }
384
385 /*
386  * user diagnostics; report root cause of error based on execution unit status
387  */
388 static void report_eu_error(struct device *dev, int ch, struct talitos_desc *desc)
389 {
390         struct talitos_private *priv = dev_get_drvdata(dev);
391         int i;
392
393         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
394         case DESC_HDR_SEL0_AFEU:
395                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
396                         in_be32(priv->reg + TALITOS_AFEUISR),
397                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
398                 break;
399         case DESC_HDR_SEL0_DEU:
400                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
401                         in_be32(priv->reg + TALITOS_DEUISR),
402                         in_be32(priv->reg + TALITOS_DEUISR_LO));
403                 break;
404         case DESC_HDR_SEL0_MDEUA:
405         case DESC_HDR_SEL0_MDEUB:
406                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
407                         in_be32(priv->reg + TALITOS_MDEUISR),
408                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
409                 break;
410         case DESC_HDR_SEL0_RNG:
411                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
412                         in_be32(priv->reg + TALITOS_RNGUISR),
413                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
414                 break;
415         case DESC_HDR_SEL0_PKEU:
416                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
417                         in_be32(priv->reg + TALITOS_PKEUISR),
418                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
419                 break;
420         case DESC_HDR_SEL0_AESU:
421                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
422                         in_be32(priv->reg + TALITOS_AESUISR),
423                         in_be32(priv->reg + TALITOS_AESUISR_LO));
424                 break;
425         case DESC_HDR_SEL0_CRCU:
426                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
427                         in_be32(priv->reg + TALITOS_CRCUISR),
428                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
429                 break;
430         case DESC_HDR_SEL0_KEU:
431                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
432                         in_be32(priv->reg + TALITOS_KEUISR),
433                         in_be32(priv->reg + TALITOS_KEUISR_LO));
434                 break;
435         }
436
437         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
438         case DESC_HDR_SEL1_MDEUA:
439         case DESC_HDR_SEL1_MDEUB:
440                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
441                         in_be32(priv->reg + TALITOS_MDEUISR),
442                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
443                 break;
444         case DESC_HDR_SEL1_CRCU:
445                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
446                         in_be32(priv->reg + TALITOS_CRCUISR),
447                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
448                 break;
449         }
450
451         for (i = 0; i < 8; i++)
452                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
453                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
454                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
455 }
456
457 /*
458  * recover from error interrupts
459  */
460 static void talitos_error(unsigned long data)
461 {
462         struct device *dev = (struct device *)data;
463         struct talitos_private *priv = dev_get_drvdata(dev);
464         unsigned int timeout = TALITOS_TIMEOUT;
465         int ch, error, reset_dev = 0, reset_ch = 0;
466         u32 isr, isr_lo, v, v_lo;
467
468         isr = in_be32(priv->reg + TALITOS_ISR);
469         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
470
471         for (ch = 0; ch < priv->num_channels; ch++) {
472                 /* skip channels without errors */
473                 if (!(isr & (1 << (ch * 2 + 1))))
474                         continue;
475
476                 error = -EINVAL;
477
478                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
479                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
480
481                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
482                         dev_err(dev, "double fetch fifo overflow error\n");
483                         error = -EAGAIN;
484                         reset_ch = 1;
485                 }
486                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
487                         /* h/w dropped descriptor */
488                         dev_err(dev, "single fetch fifo overflow error\n");
489                         error = -EAGAIN;
490                 }
491                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
492                         dev_err(dev, "master data transfer error\n");
493                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
494                         dev_err(dev, "s/g data length zero error\n");
495                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
496                         dev_err(dev, "fetch pointer zero error\n");
497                 if (v_lo & TALITOS_CCPSR_LO_IDH)
498                         dev_err(dev, "illegal descriptor header error\n");
499                 if (v_lo & TALITOS_CCPSR_LO_IEU)
500                         dev_err(dev, "invalid execution unit error\n");
501                 if (v_lo & TALITOS_CCPSR_LO_EU)
502                         report_eu_error(dev, ch, current_desc(dev, ch));
503                 if (v_lo & TALITOS_CCPSR_LO_GB)
504                         dev_err(dev, "gather boundary error\n");
505                 if (v_lo & TALITOS_CCPSR_LO_GRL)
506                         dev_err(dev, "gather return/length error\n");
507                 if (v_lo & TALITOS_CCPSR_LO_SB)
508                         dev_err(dev, "scatter boundary error\n");
509                 if (v_lo & TALITOS_CCPSR_LO_SRL)
510                         dev_err(dev, "scatter return/length error\n");
511
512                 flush_channel(dev, ch, error, reset_ch);
513
514                 if (reset_ch) {
515                         reset_channel(dev, ch);
516                 } else {
517                         setbits32(priv->reg + TALITOS_CCCR(ch),
518                                   TALITOS_CCCR_CONT);
519                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
520                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
521                                TALITOS_CCCR_CONT) && --timeout)
522                                 cpu_relax();
523                         if (timeout == 0) {
524                                 dev_err(dev, "failed to restart channel %d\n",
525                                         ch);
526                                 reset_dev = 1;
527                         }
528                 }
529         }
530         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
531                 dev_err(dev, "done overflow, internal time out, or rngu error: "
532                         "ISR 0x%08x_%08x\n", isr, isr_lo);
533
534                 /* purge request queues */
535                 for (ch = 0; ch < priv->num_channels; ch++)
536                         flush_channel(dev, ch, -EIO, 1);
537
538                 /* reset and reinitialize the device */
539                 init_device(dev);
540         }
541 }
542
543 static irqreturn_t talitos_interrupt(int irq, void *data)
544 {
545         struct device *dev = data;
546         struct talitos_private *priv = dev_get_drvdata(dev);
547         u32 isr, isr_lo;
548
549         isr = in_be32(priv->reg + TALITOS_ISR);
550         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
551
552         /* ack */
553         out_be32(priv->reg + TALITOS_ICR, isr);
554         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
555
556         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
557                 talitos_error((unsigned long)data);
558         else
559                 if (likely(isr & TALITOS_ISR_CHDONE))
560                         tasklet_schedule(&priv->done_task);
561
562         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
563 }
564
565 /*
566  * hwrng
567  */
568 static int talitos_rng_data_present(struct hwrng *rng, int wait)
569 {
570         struct device *dev = (struct device *)rng->priv;
571         struct talitos_private *priv = dev_get_drvdata(dev);
572         u32 ofl;
573         int i;
574
575         for (i = 0; i < 20; i++) {
576                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
577                       TALITOS_RNGUSR_LO_OFL;
578                 if (ofl || !wait)
579                         break;
580                 udelay(10);
581         }
582
583         return !!ofl;
584 }
585
586 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
587 {
588         struct device *dev = (struct device *)rng->priv;
589         struct talitos_private *priv = dev_get_drvdata(dev);
590
591         /* rng fifo requires 64-bit accesses */
592         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
593         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
594
595         return sizeof(u32);
596 }
597
598 static int talitos_rng_init(struct hwrng *rng)
599 {
600         struct device *dev = (struct device *)rng->priv;
601         struct talitos_private *priv = dev_get_drvdata(dev);
602         unsigned int timeout = TALITOS_TIMEOUT;
603
604         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
605         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
606                && --timeout)
607                 cpu_relax();
608         if (timeout == 0) {
609                 dev_err(dev, "failed to reset rng hw\n");
610                 return -ENODEV;
611         }
612
613         /* start generating */
614         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
615
616         return 0;
617 }
618
619 static int talitos_register_rng(struct device *dev)
620 {
621         struct talitos_private *priv = dev_get_drvdata(dev);
622
623         priv->rng.name          = dev_driver_string(dev),
624         priv->rng.init          = talitos_rng_init,
625         priv->rng.data_present  = talitos_rng_data_present,
626         priv->rng.data_read     = talitos_rng_data_read,
627         priv->rng.priv          = (unsigned long)dev;
628
629         return hwrng_register(&priv->rng);
630 }
631
632 static void talitos_unregister_rng(struct device *dev)
633 {
634         struct talitos_private *priv = dev_get_drvdata(dev);
635
636         hwrng_unregister(&priv->rng);
637 }
638
639 /*
640  * crypto alg
641  */
642 #define TALITOS_CRA_PRIORITY            3000
643 #define TALITOS_MAX_KEY_SIZE            64
644 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
645
646 #define MD5_DIGEST_SIZE   16
647
648 struct talitos_ctx {
649         struct device *dev;
650         __be32 desc_hdr_template;
651         u8 key[TALITOS_MAX_KEY_SIZE];
652         u8 iv[TALITOS_MAX_IV_LENGTH];
653         unsigned int keylen;
654         unsigned int enckeylen;
655         unsigned int authkeylen;
656         unsigned int authsize;
657 };
658
659 static int aead_authenc_setauthsize(struct crypto_aead *authenc,
660                                                  unsigned int authsize)
661 {
662         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
663
664         ctx->authsize = authsize;
665
666         return 0;
667 }
668
669 static int aead_authenc_setkey(struct crypto_aead *authenc,
670                                             const u8 *key, unsigned int keylen)
671 {
672         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
673         struct rtattr *rta = (void *)key;
674         struct crypto_authenc_key_param *param;
675         unsigned int authkeylen;
676         unsigned int enckeylen;
677
678         if (!RTA_OK(rta, keylen))
679                 goto badkey;
680
681         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
682                 goto badkey;
683
684         if (RTA_PAYLOAD(rta) < sizeof(*param))
685                 goto badkey;
686
687         param = RTA_DATA(rta);
688         enckeylen = be32_to_cpu(param->enckeylen);
689
690         key += RTA_ALIGN(rta->rta_len);
691         keylen -= RTA_ALIGN(rta->rta_len);
692
693         if (keylen < enckeylen)
694                 goto badkey;
695
696         authkeylen = keylen - enckeylen;
697
698         if (keylen > TALITOS_MAX_KEY_SIZE)
699                 goto badkey;
700
701         memcpy(&ctx->key, key, keylen);
702
703         ctx->keylen = keylen;
704         ctx->enckeylen = enckeylen;
705         ctx->authkeylen = authkeylen;
706
707         return 0;
708
709 badkey:
710         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
711         return -EINVAL;
712 }
713
714 /*
715  * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor
716  * @src_nents: number of segments in input scatterlist
717  * @dst_nents: number of segments in output scatterlist
718  * @dma_len: length of dma mapped link_tbl space
719  * @dma_link_tbl: bus physical address of link_tbl
720  * @desc: h/w descriptor
721  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
722  *
723  * if decrypting (with authcheck), or either one of src_nents or dst_nents
724  * is greater than 1, an integrity check value is concatenated to the end
725  * of link_tbl data
726  */
727 struct ipsec_esp_edesc {
728         int src_nents;
729         int dst_nents;
730         int dma_len;
731         dma_addr_t dma_link_tbl;
732         struct talitos_desc desc;
733         struct talitos_ptr link_tbl[0];
734 };
735
736 static void ipsec_esp_unmap(struct device *dev,
737                             struct ipsec_esp_edesc *edesc,
738                             struct aead_request *areq)
739 {
740         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
741         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
742         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
743         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
744
745         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
746
747         if (areq->src != areq->dst) {
748                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
749                              DMA_TO_DEVICE);
750                 dma_unmap_sg(dev, areq->dst, edesc->dst_nents ? : 1,
751                              DMA_FROM_DEVICE);
752         } else {
753                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
754                              DMA_BIDIRECTIONAL);
755         }
756
757         if (edesc->dma_len)
758                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
759                                  DMA_BIDIRECTIONAL);
760 }
761
762 /*
763  * ipsec_esp descriptor callbacks
764  */
765 static void ipsec_esp_encrypt_done(struct device *dev,
766                                    struct talitos_desc *desc, void *context,
767                                    int err)
768 {
769         struct aead_request *areq = context;
770         struct ipsec_esp_edesc *edesc =
771                  container_of(desc, struct ipsec_esp_edesc, desc);
772         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
773         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
774         struct scatterlist *sg;
775         void *icvdata;
776
777         ipsec_esp_unmap(dev, edesc, areq);
778
779         /* copy the generated ICV to dst */
780         if (edesc->dma_len) {
781                 icvdata = &edesc->link_tbl[edesc->src_nents +
782                                            edesc->dst_nents + 1];
783                 sg = sg_last(areq->dst, edesc->dst_nents);
784                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
785                        icvdata, ctx->authsize);
786         }
787
788         kfree(edesc);
789
790         aead_request_complete(areq, err);
791 }
792
793 static void ipsec_esp_decrypt_done(struct device *dev,
794                                    struct talitos_desc *desc, void *context,
795                                    int err)
796 {
797         struct aead_request *req = context;
798         struct ipsec_esp_edesc *edesc =
799                  container_of(desc, struct ipsec_esp_edesc, desc);
800         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
801         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
802         struct scatterlist *sg;
803         void *icvdata;
804
805         ipsec_esp_unmap(dev, edesc, req);
806
807         if (!err) {
808                 /* auth check */
809                 if (edesc->dma_len)
810                         icvdata = &edesc->link_tbl[edesc->src_nents +
811                                                    edesc->dst_nents + 1];
812                 else
813                         icvdata = &edesc->link_tbl[0];
814
815                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
816                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
817                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
818         }
819
820         kfree(edesc);
821
822         aead_request_complete(req, err);
823 }
824
825 /*
826  * convert scatterlist to SEC h/w link table format
827  * stop at cryptlen bytes
828  */
829 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
830                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
831 {
832         int n_sg = sg_count;
833
834         while (n_sg--) {
835                 link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
836                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
837                 link_tbl_ptr->j_extent = 0;
838                 link_tbl_ptr++;
839                 cryptlen -= sg_dma_len(sg);
840                 sg = sg_next(sg);
841         }
842
843         /* adjust (decrease) last one (or two) entry's len to cryptlen */
844         link_tbl_ptr--;
845         while (link_tbl_ptr->len <= (-cryptlen)) {
846                 /* Empty this entry, and move to previous one */
847                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
848                 link_tbl_ptr->len = 0;
849                 sg_count--;
850                 link_tbl_ptr--;
851         }
852         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
853                                         + cryptlen);
854
855         /* tag end of link table */
856         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
857
858         return sg_count;
859 }
860
861 /*
862  * fill in and submit ipsec_esp descriptor
863  */
864 static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
865                      u8 *giv, u64 seq,
866                      void (*callback) (struct device *dev,
867                                        struct talitos_desc *desc,
868                                        void *context, int error))
869 {
870         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
871         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
872         struct device *dev = ctx->dev;
873         struct talitos_desc *desc = &edesc->desc;
874         unsigned int cryptlen = areq->cryptlen;
875         unsigned int authsize = ctx->authsize;
876         unsigned int ivsize;
877         int sg_count;
878
879         /* hmac key */
880         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
881                                0, DMA_TO_DEVICE);
882         /* hmac data */
883         map_single_talitos_ptr(dev, &desc->ptr[1], sg_virt(areq->src) -
884                                sg_virt(areq->assoc), sg_virt(areq->assoc), 0,
885                                DMA_TO_DEVICE);
886         /* cipher iv */
887         ivsize = crypto_aead_ivsize(aead);
888         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
889                                DMA_TO_DEVICE);
890
891         /* cipher key */
892         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
893                                (char *)&ctx->key + ctx->authkeylen, 0,
894                                DMA_TO_DEVICE);
895
896         /*
897          * cipher in
898          * map and adjust cipher len to aead request cryptlen.
899          * extent is bytes of HMAC postpended to ciphertext,
900          * typically 12 for ipsec
901          */
902         desc->ptr[4].len = cpu_to_be16(cryptlen);
903         desc->ptr[4].j_extent = authsize;
904
905         if (areq->src == areq->dst)
906                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
907                                       DMA_BIDIRECTIONAL);
908         else
909                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
910                                       DMA_TO_DEVICE);
911
912         if (sg_count == 1) {
913                 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
914         } else {
915                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
916                                           &edesc->link_tbl[0]);
917                 if (sg_count > 1) {
918                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
919                         desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
920                         dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
921                                                    edesc->dma_len, DMA_BIDIRECTIONAL);
922                 } else {
923                         /* Only one segment now, so no link tbl needed */
924                         desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
925                 }
926         }
927
928         /* cipher out */
929         desc->ptr[5].len = cpu_to_be16(cryptlen);
930         desc->ptr[5].j_extent = authsize;
931
932         if (areq->src != areq->dst) {
933                 sg_count = dma_map_sg(dev, areq->dst, edesc->dst_nents ? : 1,
934                                       DMA_FROM_DEVICE);
935         }
936
937         if (sg_count == 1) {
938                 desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
939         } else {
940                 struct talitos_ptr *link_tbl_ptr =
941                         &edesc->link_tbl[edesc->src_nents];
942                 struct scatterlist *sg;
943
944                 desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
945                                                edesc->dma_link_tbl +
946                                                edesc->src_nents);
947                 if (areq->src == areq->dst) {
948                         memcpy(link_tbl_ptr, &edesc->link_tbl[0],
949                                edesc->src_nents * sizeof(struct talitos_ptr));
950                 } else {
951                         sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
952                                                   link_tbl_ptr);
953                 }
954                 link_tbl_ptr += sg_count - 1;
955
956                 /* handle case where sg_last contains the ICV exclusively */
957                 sg = sg_last(areq->dst, edesc->dst_nents);
958                 if (sg->length == ctx->authsize)
959                         link_tbl_ptr--;
960
961                 link_tbl_ptr->j_extent = 0;
962                 link_tbl_ptr++;
963                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
964                 link_tbl_ptr->len = cpu_to_be16(authsize);
965
966                 /* icv data follows link tables */
967                 link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
968                                                 edesc->dma_link_tbl +
969                                                 edesc->src_nents +
970                                                 edesc->dst_nents + 1);
971
972                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
973                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
974                                            edesc->dma_len, DMA_BIDIRECTIONAL);
975         }
976
977         /* iv out */
978         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
979                                DMA_FROM_DEVICE);
980
981         return talitos_submit(dev, desc, callback, areq);
982 }
983
984
985 /*
986  * derive number of elements in scatterlist
987  */
988 static int sg_count(struct scatterlist *sg_list, int nbytes)
989 {
990         struct scatterlist *sg = sg_list;
991         int sg_nents = 0;
992
993         while (nbytes) {
994                 sg_nents++;
995                 nbytes -= sg->length;
996                 sg = sg_next(sg);
997         }
998
999         return sg_nents;
1000 }
1001
1002 /*
1003  * allocate and map the ipsec_esp extended descriptor
1004  */
1005 static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
1006                                                      int icv_stashing)
1007 {
1008         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1009         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1010         struct ipsec_esp_edesc *edesc;
1011         int src_nents, dst_nents, alloc_len, dma_len;
1012
1013         if (areq->cryptlen + ctx->authsize > TALITOS_MAX_DATA_LEN) {
1014                 dev_err(ctx->dev, "cryptlen exceeds h/w max limit\n");
1015                 return ERR_PTR(-EINVAL);
1016         }
1017
1018         src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize);
1019         src_nents = (src_nents == 1) ? 0 : src_nents;
1020
1021         if (areq->dst == areq->src) {
1022                 dst_nents = src_nents;
1023         } else {
1024                 dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize);
1025                 dst_nents = (dst_nents == 1) ? 0 : src_nents;
1026         }
1027
1028         /*
1029          * allocate space for base edesc plus the link tables,
1030          * allowing for a separate entry for the generated ICV (+ 1),
1031          * and the ICV data itself
1032          */
1033         alloc_len = sizeof(struct ipsec_esp_edesc);
1034         if (src_nents || dst_nents) {
1035                 dma_len = (src_nents + dst_nents + 1) *
1036                                  sizeof(struct talitos_ptr) + ctx->authsize;
1037                 alloc_len += dma_len;
1038         } else {
1039                 dma_len = 0;
1040                 alloc_len += icv_stashing ? ctx->authsize : 0;
1041         }
1042
1043         edesc = kmalloc(alloc_len, GFP_DMA);
1044         if (!edesc) {
1045                 dev_err(ctx->dev, "could not allocate edescriptor\n");
1046                 return ERR_PTR(-ENOMEM);
1047         }
1048
1049         edesc->src_nents = src_nents;
1050         edesc->dst_nents = dst_nents;
1051         edesc->dma_len = dma_len;
1052         edesc->dma_link_tbl = dma_map_single(ctx->dev, &edesc->link_tbl[0],
1053                                              edesc->dma_len, DMA_BIDIRECTIONAL);
1054
1055         return edesc;
1056 }
1057
1058 static int aead_authenc_encrypt(struct aead_request *req)
1059 {
1060         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1061         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1062         struct ipsec_esp_edesc *edesc;
1063
1064         /* allocate extended descriptor */
1065         edesc = ipsec_esp_edesc_alloc(req, 0);
1066         if (IS_ERR(edesc))
1067                 return PTR_ERR(edesc);
1068
1069         /* set encrypt */
1070         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1071
1072         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1073 }
1074
1075 static int aead_authenc_decrypt(struct aead_request *req)
1076 {
1077         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1078         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1079         unsigned int authsize = ctx->authsize;
1080         struct ipsec_esp_edesc *edesc;
1081         struct scatterlist *sg;
1082         void *icvdata;
1083
1084         req->cryptlen -= authsize;
1085
1086         /* allocate extended descriptor */
1087         edesc = ipsec_esp_edesc_alloc(req, 1);
1088         if (IS_ERR(edesc))
1089                 return PTR_ERR(edesc);
1090
1091         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1092         if (edesc->dma_len)
1093                 icvdata = &edesc->link_tbl[edesc->src_nents +
1094                                            edesc->dst_nents + 1];
1095         else
1096                 icvdata = &edesc->link_tbl[0];
1097
1098         sg = sg_last(req->src, edesc->src_nents ? : 1);
1099
1100         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1101                ctx->authsize);
1102
1103         /* decrypt */
1104         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1105
1106         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_done);
1107 }
1108
1109 static int aead_authenc_givencrypt(
1110         struct aead_givcrypt_request *req)
1111 {
1112         struct aead_request *areq = &req->areq;
1113         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1114         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1115         struct ipsec_esp_edesc *edesc;
1116
1117         /* allocate extended descriptor */
1118         edesc = ipsec_esp_edesc_alloc(areq, 0);
1119         if (IS_ERR(edesc))
1120                 return PTR_ERR(edesc);
1121
1122         /* set encrypt */
1123         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1124
1125         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1126
1127         return ipsec_esp(edesc, areq, req->giv, req->seq,
1128                          ipsec_esp_encrypt_done);
1129 }
1130
1131 struct talitos_alg_template {
1132         char name[CRYPTO_MAX_ALG_NAME];
1133         char driver_name[CRYPTO_MAX_ALG_NAME];
1134         unsigned int blocksize;
1135         struct aead_alg aead;
1136         struct device *dev;
1137         __be32 desc_hdr_template;
1138 };
1139
1140 static struct talitos_alg_template driver_algs[] = {
1141         /* single-pass ipsec_esp descriptor */
1142         {
1143                 .name = "authenc(hmac(sha1),cbc(aes))",
1144                 .driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1145                 .blocksize = AES_BLOCK_SIZE,
1146                 .aead = {
1147                         .setkey = aead_authenc_setkey,
1148                         .setauthsize = aead_authenc_setauthsize,
1149                         .encrypt = aead_authenc_encrypt,
1150                         .decrypt = aead_authenc_decrypt,
1151                         .givencrypt = aead_authenc_givencrypt,
1152                         .geniv = "<built-in>",
1153                         .ivsize = AES_BLOCK_SIZE,
1154                         .maxauthsize = SHA1_DIGEST_SIZE,
1155                         },
1156                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1157                                      DESC_HDR_SEL0_AESU |
1158                                      DESC_HDR_MODE0_AESU_CBC |
1159                                      DESC_HDR_SEL1_MDEUA |
1160                                      DESC_HDR_MODE1_MDEU_INIT |
1161                                      DESC_HDR_MODE1_MDEU_PAD |
1162                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1163         },
1164         {
1165                 .name = "authenc(hmac(sha1),cbc(des3_ede))",
1166                 .driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1167                 .blocksize = DES3_EDE_BLOCK_SIZE,
1168                 .aead = {
1169                         .setkey = aead_authenc_setkey,
1170                         .setauthsize = aead_authenc_setauthsize,
1171                         .encrypt = aead_authenc_encrypt,
1172                         .decrypt = aead_authenc_decrypt,
1173                         .givencrypt = aead_authenc_givencrypt,
1174                         .geniv = "<built-in>",
1175                         .ivsize = DES3_EDE_BLOCK_SIZE,
1176                         .maxauthsize = SHA1_DIGEST_SIZE,
1177                         },
1178                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1179                                      DESC_HDR_SEL0_DEU |
1180                                      DESC_HDR_MODE0_DEU_CBC |
1181                                      DESC_HDR_MODE0_DEU_3DES |
1182                                      DESC_HDR_SEL1_MDEUA |
1183                                      DESC_HDR_MODE1_MDEU_INIT |
1184                                      DESC_HDR_MODE1_MDEU_PAD |
1185                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1186         },
1187         {
1188                 .name = "authenc(hmac(sha256),cbc(aes))",
1189                 .driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1190                 .blocksize = AES_BLOCK_SIZE,
1191                 .aead = {
1192                         .setkey = aead_authenc_setkey,
1193                         .setauthsize = aead_authenc_setauthsize,
1194                         .encrypt = aead_authenc_encrypt,
1195                         .decrypt = aead_authenc_decrypt,
1196                         .givencrypt = aead_authenc_givencrypt,
1197                         .geniv = "<built-in>",
1198                         .ivsize = AES_BLOCK_SIZE,
1199                         .maxauthsize = SHA256_DIGEST_SIZE,
1200                         },
1201                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1202                                      DESC_HDR_SEL0_AESU |
1203                                      DESC_HDR_MODE0_AESU_CBC |
1204                                      DESC_HDR_SEL1_MDEUA |
1205                                      DESC_HDR_MODE1_MDEU_INIT |
1206                                      DESC_HDR_MODE1_MDEU_PAD |
1207                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1208         },
1209         {
1210                 .name = "authenc(hmac(sha256),cbc(des3_ede))",
1211                 .driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1212                 .blocksize = DES3_EDE_BLOCK_SIZE,
1213                 .aead = {
1214                         .setkey = aead_authenc_setkey,
1215                         .setauthsize = aead_authenc_setauthsize,
1216                         .encrypt = aead_authenc_encrypt,
1217                         .decrypt = aead_authenc_decrypt,
1218                         .givencrypt = aead_authenc_givencrypt,
1219                         .geniv = "<built-in>",
1220                         .ivsize = DES3_EDE_BLOCK_SIZE,
1221                         .maxauthsize = SHA256_DIGEST_SIZE,
1222                         },
1223                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1224                                      DESC_HDR_SEL0_DEU |
1225                                      DESC_HDR_MODE0_DEU_CBC |
1226                                      DESC_HDR_MODE0_DEU_3DES |
1227                                      DESC_HDR_SEL1_MDEUA |
1228                                      DESC_HDR_MODE1_MDEU_INIT |
1229                                      DESC_HDR_MODE1_MDEU_PAD |
1230                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1231         },
1232         {
1233                 .name = "authenc(hmac(md5),cbc(aes))",
1234                 .driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1235                 .blocksize = AES_BLOCK_SIZE,
1236                 .aead = {
1237                         .setkey = aead_authenc_setkey,
1238                         .setauthsize = aead_authenc_setauthsize,
1239                         .encrypt = aead_authenc_encrypt,
1240                         .decrypt = aead_authenc_decrypt,
1241                         .givencrypt = aead_authenc_givencrypt,
1242                         .geniv = "<built-in>",
1243                         .ivsize = AES_BLOCK_SIZE,
1244                         .maxauthsize = MD5_DIGEST_SIZE,
1245                         },
1246                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1247                                      DESC_HDR_SEL0_AESU |
1248                                      DESC_HDR_MODE0_AESU_CBC |
1249                                      DESC_HDR_SEL1_MDEUA |
1250                                      DESC_HDR_MODE1_MDEU_INIT |
1251                                      DESC_HDR_MODE1_MDEU_PAD |
1252                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1253         },
1254         {
1255                 .name = "authenc(hmac(md5),cbc(des3_ede))",
1256                 .driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1257                 .blocksize = DES3_EDE_BLOCK_SIZE,
1258                 .aead = {
1259                         .setkey = aead_authenc_setkey,
1260                         .setauthsize = aead_authenc_setauthsize,
1261                         .encrypt = aead_authenc_encrypt,
1262                         .decrypt = aead_authenc_decrypt,
1263                         .givencrypt = aead_authenc_givencrypt,
1264                         .geniv = "<built-in>",
1265                         .ivsize = DES3_EDE_BLOCK_SIZE,
1266                         .maxauthsize = MD5_DIGEST_SIZE,
1267                         },
1268                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1269                                      DESC_HDR_SEL0_DEU |
1270                                      DESC_HDR_MODE0_DEU_CBC |
1271                                      DESC_HDR_MODE0_DEU_3DES |
1272                                      DESC_HDR_SEL1_MDEUA |
1273                                      DESC_HDR_MODE1_MDEU_INIT |
1274                                      DESC_HDR_MODE1_MDEU_PAD |
1275                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1276         }
1277 };
1278
1279 struct talitos_crypto_alg {
1280         struct list_head entry;
1281         struct device *dev;
1282         __be32 desc_hdr_template;
1283         struct crypto_alg crypto_alg;
1284 };
1285
1286 static int talitos_cra_init(struct crypto_tfm *tfm)
1287 {
1288         struct crypto_alg *alg = tfm->__crt_alg;
1289         struct talitos_crypto_alg *talitos_alg =
1290                  container_of(alg, struct talitos_crypto_alg, crypto_alg);
1291         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1292
1293         /* update context with ptr to dev */
1294         ctx->dev = talitos_alg->dev;
1295         /* copy descriptor header template value */
1296         ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
1297
1298         /* random first IV */
1299         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
1300
1301         return 0;
1302 }
1303
1304 /*
1305  * given the alg's descriptor header template, determine whether descriptor
1306  * type and primary/secondary execution units required match the hw
1307  * capabilities description provided in the device tree node.
1308  */
1309 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1310 {
1311         struct talitos_private *priv = dev_get_drvdata(dev);
1312         int ret;
1313
1314         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1315               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1316
1317         if (SECONDARY_EU(desc_hdr_template))
1318                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1319                               & priv->exec_units);
1320
1321         return ret;
1322 }
1323
1324 static int __devexit talitos_remove(struct of_device *ofdev)
1325 {
1326         struct device *dev = &ofdev->dev;
1327         struct talitos_private *priv = dev_get_drvdata(dev);
1328         struct talitos_crypto_alg *t_alg, *n;
1329         int i;
1330
1331         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1332                 crypto_unregister_alg(&t_alg->crypto_alg);
1333                 list_del(&t_alg->entry);
1334                 kfree(t_alg);
1335         }
1336
1337         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1338                 talitos_unregister_rng(dev);
1339
1340         kfree(priv->tail);
1341         kfree(priv->head);
1342
1343         if (priv->fifo)
1344                 for (i = 0; i < priv->num_channels; i++)
1345                         kfree(priv->fifo[i]);
1346
1347         kfree(priv->fifo);
1348         kfree(priv->head_lock);
1349         kfree(priv->tail_lock);
1350
1351         if (priv->irq != NO_IRQ) {
1352                 free_irq(priv->irq, dev);
1353                 irq_dispose_mapping(priv->irq);
1354         }
1355
1356         tasklet_kill(&priv->done_task);
1357         tasklet_kill(&priv->error_task);
1358
1359         iounmap(priv->reg);
1360
1361         dev_set_drvdata(dev, NULL);
1362
1363         kfree(priv);
1364
1365         return 0;
1366 }
1367
1368 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1369                                                     struct talitos_alg_template
1370                                                            *template)
1371 {
1372         struct talitos_crypto_alg *t_alg;
1373         struct crypto_alg *alg;
1374
1375         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1376         if (!t_alg)
1377                 return ERR_PTR(-ENOMEM);
1378
1379         alg = &t_alg->crypto_alg;
1380
1381         snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
1382         snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1383                  template->driver_name);
1384         alg->cra_module = THIS_MODULE;
1385         alg->cra_init = talitos_cra_init;
1386         alg->cra_priority = TALITOS_CRA_PRIORITY;
1387         alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC;
1388         alg->cra_blocksize = template->blocksize;
1389         alg->cra_alignmask = 0;
1390         alg->cra_type = &crypto_aead_type;
1391         alg->cra_ctxsize = sizeof(struct talitos_ctx);
1392         alg->cra_u.aead = template->aead;
1393
1394         t_alg->desc_hdr_template = template->desc_hdr_template;
1395         t_alg->dev = dev;
1396
1397         return t_alg;
1398 }
1399
1400 static int talitos_probe(struct of_device *ofdev,
1401                          const struct of_device_id *match)
1402 {
1403         struct device *dev = &ofdev->dev;
1404         struct device_node *np = ofdev->node;
1405         struct talitos_private *priv;
1406         const unsigned int *prop;
1407         int i, err;
1408
1409         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1410         if (!priv)
1411                 return -ENOMEM;
1412
1413         dev_set_drvdata(dev, priv);
1414
1415         priv->ofdev = ofdev;
1416
1417         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
1418         tasklet_init(&priv->error_task, talitos_error, (unsigned long)dev);
1419
1420         priv->irq = irq_of_parse_and_map(np, 0);
1421
1422         if (priv->irq == NO_IRQ) {
1423                 dev_err(dev, "failed to map irq\n");
1424                 err = -EINVAL;
1425                 goto err_out;
1426         }
1427
1428         /* get the irq line */
1429         err = request_irq(priv->irq, talitos_interrupt, 0,
1430                           dev_driver_string(dev), dev);
1431         if (err) {
1432                 dev_err(dev, "failed to request irq %d\n", priv->irq);
1433                 irq_dispose_mapping(priv->irq);
1434                 priv->irq = NO_IRQ;
1435                 goto err_out;
1436         }
1437
1438         priv->reg = of_iomap(np, 0);
1439         if (!priv->reg) {
1440                 dev_err(dev, "failed to of_iomap\n");
1441                 err = -ENOMEM;
1442                 goto err_out;
1443         }
1444
1445         /* get SEC version capabilities from device tree */
1446         prop = of_get_property(np, "fsl,num-channels", NULL);
1447         if (prop)
1448                 priv->num_channels = *prop;
1449
1450         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1451         if (prop)
1452                 priv->chfifo_len = *prop;
1453
1454         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1455         if (prop)
1456                 priv->exec_units = *prop;
1457
1458         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1459         if (prop)
1460                 priv->desc_types = *prop;
1461
1462         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1463             !priv->exec_units || !priv->desc_types) {
1464                 dev_err(dev, "invalid property data in device tree node\n");
1465                 err = -EINVAL;
1466                 goto err_out;
1467         }
1468
1469         of_node_put(np);
1470         np = NULL;
1471
1472         priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1473                                   GFP_KERNEL);
1474         priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1475                                   GFP_KERNEL);
1476         if (!priv->head_lock || !priv->tail_lock) {
1477                 dev_err(dev, "failed to allocate fifo locks\n");
1478                 err = -ENOMEM;
1479                 goto err_out;
1480         }
1481
1482         for (i = 0; i < priv->num_channels; i++) {
1483                 spin_lock_init(&priv->head_lock[i]);
1484                 spin_lock_init(&priv->tail_lock[i]);
1485         }
1486
1487         priv->fifo = kmalloc(sizeof(struct talitos_request *) *
1488                              priv->num_channels, GFP_KERNEL);
1489         if (!priv->fifo) {
1490                 dev_err(dev, "failed to allocate request fifo\n");
1491                 err = -ENOMEM;
1492                 goto err_out;
1493         }
1494
1495         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1496
1497         for (i = 0; i < priv->num_channels; i++) {
1498                 priv->fifo[i] = kzalloc(sizeof(struct talitos_request) *
1499                                         priv->fifo_len, GFP_KERNEL);
1500                 if (!priv->fifo[i]) {
1501                         dev_err(dev, "failed to allocate request fifo %d\n", i);
1502                         err = -ENOMEM;
1503                         goto err_out;
1504                 }
1505         }
1506
1507         priv->head = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1508         priv->tail = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1509         if (!priv->head || !priv->tail) {
1510                 dev_err(dev, "failed to allocate request index space\n");
1511                 err = -ENOMEM;
1512                 goto err_out;
1513         }
1514
1515         /* reset and initialize the h/w */
1516         err = init_device(dev);
1517         if (err) {
1518                 dev_err(dev, "failed to initialize device\n");
1519                 goto err_out;
1520         }
1521
1522         /* register the RNG, if available */
1523         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1524                 err = talitos_register_rng(dev);
1525                 if (err) {
1526                         dev_err(dev, "failed to register hwrng: %d\n", err);
1527                         goto err_out;
1528                 } else
1529                         dev_info(dev, "hwrng\n");
1530         }
1531
1532         /* register crypto algorithms the device supports */
1533         INIT_LIST_HEAD(&priv->alg_list);
1534
1535         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1536                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1537                         struct talitos_crypto_alg *t_alg;
1538
1539                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1540                         if (IS_ERR(t_alg)) {
1541                                 err = PTR_ERR(t_alg);
1542                                 goto err_out;
1543                         }
1544
1545                         err = crypto_register_alg(&t_alg->crypto_alg);
1546                         if (err) {
1547                                 dev_err(dev, "%s alg registration failed\n",
1548                                         t_alg->crypto_alg.cra_driver_name);
1549                                 kfree(t_alg);
1550                         } else {
1551                                 list_add_tail(&t_alg->entry, &priv->alg_list);
1552                                 dev_info(dev, "%s\n",
1553                                          t_alg->crypto_alg.cra_driver_name);
1554                         }
1555                 }
1556         }
1557
1558         return 0;
1559
1560 err_out:
1561         talitos_remove(ofdev);
1562         if (np)
1563                 of_node_put(np);
1564
1565         return err;
1566 }
1567
1568 static struct of_device_id talitos_match[] = {
1569         {
1570                 .compatible = "fsl,sec2.0",
1571         },
1572         {},
1573 };
1574 MODULE_DEVICE_TABLE(of, talitos_match);
1575
1576 static struct of_platform_driver talitos_driver = {
1577         .name = "talitos",
1578         .match_table = talitos_match,
1579         .probe = talitos_probe,
1580         .remove = __devexit_p(talitos_remove),
1581 };
1582
1583 static int __init talitos_init(void)
1584 {
1585         return of_register_platform_driver(&talitos_driver);
1586 }
1587 module_init(talitos_init);
1588
1589 static void __exit talitos_exit(void)
1590 {
1591         of_unregister_platform_driver(&talitos_driver);
1592 }
1593 module_exit(talitos_exit);
1594
1595 MODULE_LICENSE("GPL");
1596 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
1597 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");