git.oblomov.eu Git - linux-2.6/blob - arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/config.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/linkage.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/smp.h>
  25 #include <linux/mm.h>
  26 #include <linux/slab.h>
  27 #include <linux/kernel_stat.h>
  28
  29 #include <asm/errno.h>
  30 #include <asm/signal.h>
  31 #include <asm/system.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/io.h>
  34
  35 #include <asm/sibyte/sb1250_regs.h>
  36 #include <asm/sibyte/sb1250_int.h>
  37 #include <asm/sibyte/sb1250_uart.h>
  38 #include <asm/sibyte/sb1250_scd.h>
  39 #include <asm/sibyte/sb1250.h>
  40
  41 /*
  42  * These are the routines that handle all the low level interrupt stuff.
  43  * Actions handled here are: initialization of the interrupt map, requesting of
  44  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  45  * for interrupt lines
  46  */
  47
  48
  49 #define shutdown_sb1250_irq     disable_sb1250_irq
  50 static void end_sb1250_irq(unsigned int irq);
  51 static void enable_sb1250_irq(unsigned int irq);
  52 static void disable_sb1250_irq(unsigned int irq);
  53 static unsigned int startup_sb1250_irq(unsigned int irq);
  54 static void ack_sb1250_irq(unsigned int irq);
  55 #ifdef CONFIG_SMP
  56 static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
  57 #endif
  58
  59 #ifdef CONFIG_SIBYTE_HAS_LDT
  60 extern unsigned long ldt_eoi_space;
  61 #endif
  62
  63 #ifdef CONFIG_KGDB
  64 static int kgdb_irq;
  65
  66 /* Default to UART1 */
  67 int kgdb_port = 1;
  68 #ifdef CONFIG_SIBYTE_SB1250_DUART
  69 extern char sb1250_duart_present[];
  70 #endif
  71 #endif
  72
  73 static struct hw_interrupt_type sb1250_irq_type = {
  74         .typename = "SB1250-IMR",
  75         .startup = startup_sb1250_irq,
  76         .shutdown = shutdown_sb1250_irq,
  77         .enable = enable_sb1250_irq,
  78         .disable = disable_sb1250_irq,
  79         .ack = ack_sb1250_irq,
  80         .end = end_sb1250_irq,
  81 #ifdef CONFIG_SMP
  82         .set_affinity = sb1250_set_affinity
  83 #endif
  84 };
  85
  86 /* Store the CPU id (not the logical number) */
  87 int sb1250_irq_owner[SB1250_NR_IRQS];
  88
  89 DEFINE_SPINLOCK(sb1250_imr_lock);
  90
  91 void sb1250_mask_irq(int cpu, int irq)
  92 {
  93         unsigned long flags;
  94         u64 cur_ints;
  95
  96         spin_lock_irqsave(&sb1250_imr_lock, flags);
  97         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  98                                         R_IMR_INTERRUPT_MASK));
  99         cur_ints |= (((u64) 1) << irq);
 100         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 101                                         R_IMR_INTERRUPT_MASK));
 102         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 103 }
 104
 105 void sb1250_unmask_irq(int cpu, int irq)
 106 {
 107         unsigned long flags;
 108         u64 cur_ints;
 109
 110         spin_lock_irqsave(&sb1250_imr_lock, flags);
 111         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 112                                         R_IMR_INTERRUPT_MASK));
 113         cur_ints &= ~(((u64) 1) << irq);
 114         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 115                                         R_IMR_INTERRUPT_MASK));
 116         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 117 }
 118
 119 #ifdef CONFIG_SMP
 120 static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
 121 {
 122         int i = 0, old_cpu, cpu, int_on;
 123         u64 cur_ints;
 124         irq_desc_t *desc = irq_desc + irq;
 125         unsigned long flags;
 126
 127         while (mask) {
 128                 if (mask & 1) {
 129                         mask >>= 1;
 130                         break;
 131                 }
 132                 mask >>= 1;
 133                 i++;
 134         }
 135
 136         if (mask) {
 137                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 138                 return;
 139         }
 140
 141         /* Convert logical CPU to physical CPU */
 142         cpu = cpu_logical_map(i);
 143
 144         /* Protect against other affinity changers and IMR manipulation */
 145         spin_lock_irqsave(&desc->lock, flags);
 146         spin_lock(&sb1250_imr_lock);
 147
 148         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 149         old_cpu = sb1250_irq_owner[irq];
 150         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 151                                         R_IMR_INTERRUPT_MASK));
 152         int_on = !(cur_ints & (((u64) 1) << irq));
 153         if (int_on) {
 154                 /* If it was on, mask it */
 155                 cur_ints |= (((u64) 1) << irq);
 156                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 157                                         R_IMR_INTERRUPT_MASK));
 158         }
 159         sb1250_irq_owner[irq] = cpu;
 160         if (int_on) {
 161                 /* unmask for the new CPU */
 162                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 163                                         R_IMR_INTERRUPT_MASK));
 164                 cur_ints &= ~(((u64) 1) << irq);
 165                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 166                                         R_IMR_INTERRUPT_MASK));
 167         }
 168         spin_unlock(&sb1250_imr_lock);
 169         spin_unlock_irqrestore(&desc->lock, flags);
 170 }
 171 #endif
 172
 173
 174 /* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
 175 extern void sb1250_irq_handler(void);
 176
 177 /*****************************************************************************/
 178
 179 static unsigned int startup_sb1250_irq(unsigned int irq)
 180 {
 181         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 182
 183         return 0;               /* never anything pending */
 184 }
 185
 186
 187 static void disable_sb1250_irq(unsigned int irq)
 188 {
 189         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 190 }
 191
 192 static void enable_sb1250_irq(unsigned int irq)
 193 {
 194         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 195 }
 196
 197
 198 static void ack_sb1250_irq(unsigned int irq)
 199 {
 200 #ifdef CONFIG_SIBYTE_HAS_LDT
 201         u64 pending;
 202
 203         /*
 204          * If the interrupt was an HT interrupt, now is the time to
 205          * clear it.  NOTE: we assume the HT bridge was set up to
 206          * deliver the interrupts to all CPUs (which makes affinity
 207          * changing easier for us)
 208          */
 209         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 210                                                     R_IMR_LDT_INTERRUPT)));
 211         pending &= ((u64)1 << (irq));
 212         if (pending) {
 213                 int i;
 214                 for (i=0; i<NR_CPUS; i++) {
 215                         int cpu;
 216 #ifdef CONFIG_SMP
 217                         cpu = cpu_logical_map(i);
 218 #else
 219                         cpu = i;
 220 #endif
 221                         /*
 222                          * Clear for all CPUs so an affinity switch
 223                          * doesn't find an old status
 224                          */
 225                         __raw_writeq(pending,
 226                                      IOADDR(A_IMR_REGISTER(cpu,
 227                                                 R_IMR_LDT_INTERRUPT_CLR)));
 228                 }
 229
 230                 /*
 231                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 232                  * Pass 2, the LDT world may be edge-triggered, but
 233                  * this EOI shouldn't hurt.  If they are
 234                  * level-sensitive, the EOI is required.
 235                  */
 236                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 237         }
 238 #endif
 239         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 240 }
 241
 242
 243 static void end_sb1250_irq(unsigned int irq)
 244 {
 245         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 246                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 247         }
 248 }
 249
 250
 251 void __init init_sb1250_irqs(void)
 252 {
 253         int i;
 254
 255         for (i = 0; i < NR_IRQS; i++) {
 256                 irq_desc[i].status = IRQ_DISABLED;
 257                 irq_desc[i].action = 0;
 258                 irq_desc[i].depth = 1;
 259                 if (i < SB1250_NR_IRQS) {
 260                         irq_desc[i].handler = &sb1250_irq_type;
 261                         sb1250_irq_owner[i] = 0;
 262                 } else {
 263                         irq_desc[i].handler = &no_irq_type;
 264                 }
 265         }
 266 }
 267
 268
 269 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id,
 270         struct pt_regs *regs)
 271 {
 272         return IRQ_NONE;
 273 }
 274
 275 static struct irqaction sb1250_dummy_action = {
 276         .handler = sb1250_dummy_handler,
 277         .flags   = 0,
 278         .mask    = CPU_MASK_NONE,
 279         .name    = "sb1250-private",
 280         .next    = NULL,
 281         .dev_id  = 0
 282 };
 283
 284 int sb1250_steal_irq(int irq)
 285 {
 286         irq_desc_t *desc = irq_desc + irq;
 287         unsigned long flags;
 288         int retval = 0;
 289
 290         if (irq >= SB1250_NR_IRQS)
 291                 return -EINVAL;
 292
 293         spin_lock_irqsave(&desc->lock,flags);
 294         /* Don't allow sharing at all for these */
 295         if (desc->action != NULL)
 296                 retval = -EBUSY;
 297         else {
 298                 desc->action = &sb1250_dummy_action;
 299                 desc->depth = 0;
 300         }
 301         spin_unlock_irqrestore(&desc->lock,flags);
 302         return 0;
 303 }
 304
 305 /*
 306  *  arch_init_irq is called early in the boot sequence from init/main.c via
 307  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 308  *  installing the handler that will be responsible for dispatching interrupts
 309  *  to the "right" place.
 310  */
 311 /*
 312  * For now, map all interrupts to IP[2].  We could save
 313  * some cycles by parceling out system interrupts to different
 314  * IP lines, but keep it simple for bringup.  We'll also direct
 315  * all interrupts to a single CPU; we should probably route
 316  * PCI and LDT to one cpu and everything else to the other
 317  * to balance the load a bit.
 318  *
 319  * On the second cpu, everything is set to IP5, which is
 320  * ignored, EXCEPT the mailbox interrupt.  That one is
 321  * set to IP[2] so it is handled.  This is needed so we
 322  * can do cross-cpu function calls, as requred by SMP
 323  */
 324
 325 #define IMR_IP2_VAL     K_INT_MAP_I0
 326 #define IMR_IP3_VAL     K_INT_MAP_I1
 327 #define IMR_IP4_VAL     K_INT_MAP_I2
 328 #define IMR_IP5_VAL     K_INT_MAP_I3
 329 #define IMR_IP6_VAL     K_INT_MAP_I4
 330
 331 void __init arch_init_irq(void)
 332 {
 333
 334         unsigned int i;
 335         u64 tmp;
 336         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 337                 STATUSF_IP1 | STATUSF_IP0;
 338
 339         /* Default everything to IP2 */
 340         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 341                 __raw_writeq(IMR_IP2_VAL,
 342                              IOADDR(A_IMR_REGISTER(0,
 343                                                    R_IMR_INTERRUPT_MAP_BASE) +
 344                                     (i << 3)));
 345                 __raw_writeq(IMR_IP2_VAL,
 346                              IOADDR(A_IMR_REGISTER(1,
 347                                                    R_IMR_INTERRUPT_MAP_BASE) +
 348                                     (i << 3)));
 349         }
 350
 351         init_sb1250_irqs();
 352
 353         /*
 354          * Map the high 16 bits of the mailbox registers to IP[3], for
 355          * inter-cpu messages
 356          */
 357         /* Was I1 */
 358         __raw_writeq(IMR_IP3_VAL,
 359                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 360                             (K_INT_MBOX_0 << 3)));
 361         __raw_writeq(IMR_IP3_VAL,
 362                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 363                             (K_INT_MBOX_0 << 3)));
 364
 365         /* Clear the mailboxes.  The firmware may leave them dirty */
 366         __raw_writeq(0xffffffffffffffffULL,
 367                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 368         __raw_writeq(0xffffffffffffffffULL,
 369                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 370
 371         /* Mask everything except the mailbox registers for both cpus */
 372         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 373         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 374         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 375
 376         sb1250_steal_irq(K_INT_MBOX_0);
 377
 378         /*
 379          * Note that the timer interrupts are also mapped, but this is
 380          * done in sb1250_time_init().  Also, the profiling driver
 381          * does its own management of IP7.
 382          */
 383
 384 #ifdef CONFIG_KGDB
 385         imask |= STATUSF_IP6;
 386 #endif
 387         /* Enable necessary IPs, disable the rest */
 388         change_c0_status(ST0_IM, imask);
 389         set_except_vector(0, sb1250_irq_handler);
 390
 391 #ifdef CONFIG_KGDB
 392         if (kgdb_flag) {
 393                 kgdb_irq = K_INT_UART_0 + kgdb_port;
 394
 395 #ifdef CONFIG_SIBYTE_SB1250_DUART
 396                 sb1250_duart_present[kgdb_port] = 0;
 397 #endif
 398                 /* Setup uart 1 settings, mapper */
 399                 __raw_writeq(M_DUART_IMR_BRK,
 400                              IOADDR(A_DUART_IMRREG(kgdb_port)));
 401
 402                 sb1250_steal_irq(kgdb_irq);
 403                 __raw_writeq(IMR_IP6_VAL,
 404                              IOADDR(A_IMR_REGISTER(0,
 405                                                    R_IMR_INTERRUPT_MAP_BASE) +
 406                                     (kgdb_irq << 3)));
 407                 sb1250_unmask_irq(0, kgdb_irq);
 408         }
 409 #endif
 410 }
 411
 412 #ifdef CONFIG_KGDB
 413
 414 #include <linux/delay.h>
 415
 416 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 417 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 418
 419 void sb1250_kgdb_interrupt(struct pt_regs *regs)
 420 {
 421         /*
 422          * Clear break-change status (allow some time for the remote
 423          * host to stop the break, since we would see another
 424          * interrupt on the end-of-break too)
 425          */
 426         kstat_this_cpu.irqs[kgdb_irq]++;
 427         mdelay(500);
 428         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 429                                 M_DUART_RX_EN | M_DUART_TX_EN);
 430         set_async_breakpoint(&regs->cp0_epc);
 431 }
 432
 433 #endif  /* CONFIG_KGDB */