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   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8555CDS";
  15         compatible = "MPC8555CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8555@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 08000000>;      // 128M at 0x0
  39         };
  40
  41         soc8555@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 device_type = "soc";
  45                 ranges = <0 e0000000 00100000>;
  46                 reg = <e0000000 00001000>;      // CCSRBAR 1M
  47                 bus-frequency = <0>;
  48
  49                 memory-controller@2000 {
  50                         compatible = "fsl,8555-memory-controller";
  51                         reg = <2000 1000>;
  52                         interrupt-parent = <&mpic>;
  53                         interrupts = <12 2>;
  54                 };
  55
  56                 l2-cache-controller@20000 {
  57                         compatible = "fsl,8555-l2-cache-controller";
  58                         reg = <20000 1000>;
  59                         cache-line-size = <20>; // 32 bytes
  60                         cache-size = <40000>;   // L2, 256K
  61                         interrupt-parent = <&mpic>;
  62                         interrupts = <10 2>;
  63                 };
  64
  65                 i2c@3000 {
  66                         device_type = "i2c";
  67                         compatible = "fsl-i2c";
  68                         reg = <3000 100>;
  69                         interrupts = <2b 2>;
  70                         interrupt-parent = <&mpic>;
  71                         dfsrr;
  72                 };
  73
  74                 mdio@24520 {
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         device_type = "mdio";
  78                         compatible = "gianfar";
  79                         reg = <24520 20>;
  80                         phy0: ethernet-phy@0 {
  81                                 interrupt-parent = <&mpic>;
  82                                 interrupts = <5 1>;
  83                                 reg = <0>;
  84                                 device_type = "ethernet-phy";
  85                         };
  86                         phy1: ethernet-phy@1 {
  87                                 interrupt-parent = <&mpic>;
  88                                 interrupts = <5 1>;
  89                                 reg = <1>;
  90                                 device_type = "ethernet-phy";
  91                         };
  92                 };
  93
  94                 ethernet@24000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         device_type = "network";
  98                         model = "TSEC";
  99                         compatible = "gianfar";
 100                         reg = <24000 1000>;
 101                         local-mac-address = [ 00 00 00 00 00 00 ];
 102                         interrupts = <1d 2 1e 2 22 2>;
 103                         interrupt-parent = <&mpic>;
 104                         phy-handle = <&phy0>;
 105                 };
 106
 107                 ethernet@25000 {
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         device_type = "network";
 111                         model = "TSEC";
 112                         compatible = "gianfar";
 113                         reg = <25000 1000>;
 114                         local-mac-address = [ 00 00 00 00 00 00 ];
 115                         interrupts = <23 2 24 2 28 2>;
 116                         interrupt-parent = <&mpic>;
 117                         phy-handle = <&phy1>;
 118                 };
 119
 120                 serial@4500 {
 121                         device_type = "serial";
 122                         compatible = "ns16550";
 123                         reg = <4500 100>;       // reg base, size
 124                         clock-frequency = <0>;  // should we fill in in uboot?
 125                         interrupts = <2a 2>;
 126                         interrupt-parent = <&mpic>;
 127                 };
 128
 129                 serial@4600 {
 130                         device_type = "serial";
 131                         compatible = "ns16550";
 132                         reg = <4600 100>;       // reg base, size
 133                         clock-frequency = <0>;  // should we fill in in uboot?
 134                         interrupts = <2a 2>;
 135                         interrupt-parent = <&mpic>;
 136                 };
 137
 138                 mpic: pic@40000 {
 139                         clock-frequency = <0>;
 140                         interrupt-controller;
 141                         #address-cells = <0>;
 142                         #interrupt-cells = <2>;
 143                         reg = <40000 40000>;
 144                         compatible = "chrp,open-pic";
 145                         device_type = "open-pic";
 146                         big-endian;
 147                 };
 148         };
 149
 150         pci1: pci@e0008000 {
 151                 interrupt-map-mask = <1f800 0 0 7>;
 152                 interrupt-map = <
 153
 154                         /* IDSEL 0x10 */
 155                         08000 0 0 1 &mpic 0 1
 156                         08000 0 0 2 &mpic 1 1
 157                         08000 0 0 3 &mpic 2 1
 158                         08000 0 0 4 &mpic 3 1
 159
 160                         /* IDSEL 0x11 */
 161                         08800 0 0 1 &mpic 0 1
 162                         08800 0 0 2 &mpic 1 1
 163                         08800 0 0 3 &mpic 2 1
 164                         08800 0 0 4 &mpic 3 1
 165
 166                         /* IDSEL 0x12 (Slot 1) */
 167                         09000 0 0 1 &mpic 0 1
 168                         09000 0 0 2 &mpic 1 1
 169                         09000 0 0 3 &mpic 2 1
 170                         09000 0 0 4 &mpic 3 1
 171
 172                         /* IDSEL 0x13 (Slot 2) */
 173                         09800 0 0 1 &mpic 1 1
 174                         09800 0 0 2 &mpic 2 1
 175                         09800 0 0 3 &mpic 3 1
 176                         09800 0 0 4 &mpic 0 1
 177
 178                         /* IDSEL 0x14 (Slot 3) */
 179                         0a000 0 0 1 &mpic 2 1
 180                         0a000 0 0 2 &mpic 3 1
 181                         0a000 0 0 3 &mpic 0 1
 182                         0a000 0 0 4 &mpic 1 1
 183
 184                         /* IDSEL 0x15 (Slot 4) */
 185                         0a800 0 0 1 &mpic 3 1
 186                         0a800 0 0 2 &mpic 0 1
 187                         0a800 0 0 3 &mpic 1 1
 188                         0a800 0 0 4 &mpic 2 1
 189
 190                         /* Bus 1 (Tundra Bridge) */
 191                         /* IDSEL 0x12 (ISA bridge) */
 192                         19000 0 0 1 &mpic 0 1
 193                         19000 0 0 2 &mpic 1 1
 194                         19000 0 0 3 &mpic 2 1
 195                         19000 0 0 4 &mpic 3 1>;
 196                 interrupt-parent = <&mpic>;
 197                 interrupts = <18 2>;
 198                 bus-range = <0 0>;
 199                 ranges = <02000000 0 80000000 80000000 0 20000000
 200                           01000000 0 00000000 e2000000 0 00100000>;
 201                 clock-frequency = <3f940aa>;
 202                 #interrupt-cells = <1>;
 203                 #size-cells = <2>;
 204                 #address-cells = <3>;
 205                 reg = <e0008000 1000>;
 206                 compatible = "fsl,mpc8540-pci";
 207                 device_type = "pci";
 208
 209                 i8259@19000 {
 210                         interrupt-controller;
 211                         device_type = "interrupt-controller";
 212                         reg = <19000 0 0 0 1>;
 213                         #address-cells = <0>;
 214                         #interrupt-cells = <2>;
 215                         compatible = "chrp,iic";
 216                         interrupts = <1>;
 217                         interrupt-parent = <&pci1>;
 218                 };
 219         };
 220
 221         pci@e0009000 {
 222                 interrupt-map-mask = <f800 0 0 7>;
 223                 interrupt-map = <
 224
 225                         /* IDSEL 0x15 */
 226                         a800 0 0 1 &mpic b 1
 227                         a800 0 0 2 &mpic b 1
 228                         a800 0 0 3 &mpic b 1
 229                         a800 0 0 4 &mpic b 1>;
 230                 interrupt-parent = <&mpic>;
 231                 interrupts = <19 2>;
 232                 bus-range = <0 0>;
 233                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 234                           01000000 0 00000000 e3000000 0 00100000>;
 235                 clock-frequency = <3f940aa>;
 236                 #interrupt-cells = <1>;
 237                 #size-cells = <2>;
 238                 #address-cells = <3>;
 239                 reg = <e0009000 1000>;
 240                 compatible = "fsl,mpc8540-pci";
 241                 device_type = "pci";
 242         };
 243 };