2 * arch/sh/kernel/cpu/sh2a/probe.c
4 * CPU Subtype Probing for SH-2A.
6 * Copyright (C) 2004 - 2007 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
16 int __init detect_cpu_and_cache_system(void)
18 /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
19 boot_cpu_data.flags |= CPU_HAS_OP32;
21 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
22 boot_cpu_data.type = CPU_SH7201;
23 boot_cpu_data.flags |= CPU_HAS_FPU;
24 #elif defined(CONFIG_CPU_SUBTYPE_SH7203)
25 boot_cpu_data.type = CPU_SH7203;
26 boot_cpu_data.flags |= CPU_HAS_FPU;
27 #elif defined(CONFIG_CPU_SUBTYPE_SH7263)
28 boot_cpu_data.type = CPU_SH7263;
29 boot_cpu_data.flags |= CPU_HAS_FPU;
30 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
31 boot_cpu_data.type = CPU_SH7206;
32 boot_cpu_data.flags |= CPU_HAS_DSP;
33 #elif defined(CONFIG_CPU_SUBTYPE_MXG)
34 boot_cpu_data.type = CPU_MXG;
35 boot_cpu_data.flags |= CPU_HAS_DSP;
38 boot_cpu_data.dcache.ways = 4;
39 boot_cpu_data.dcache.way_incr = (1 << 11);
40 boot_cpu_data.dcache.sets = 128;
41 boot_cpu_data.dcache.entry_shift = 4;
42 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
43 boot_cpu_data.dcache.flags = 0;
46 * The icache is the same as the dcache as far as this setup is
47 * concerned. The only real difference in hardware is that the icache
48 * lacks the U bit that the dcache has, none of this has any bearing
51 boot_cpu_data.icache = boot_cpu_data.dcache;