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   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  35
  36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  37  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  38  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  39  */
  40 struct prcm_config {
  41         unsigned long xtal_speed;       /* crystal rate */
  42         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  43         unsigned long mpu_speed;        /* speed of MPU */
  44         unsigned long cm_clksel_mpu;    /* mpu divider */
  45         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  46         unsigned long cm_clksel_gfx;    /* gfx dividers */
  47         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  48         unsigned long cm_clksel1_pll;   /* m,n */
  49         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  50         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  51         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  52         unsigned char flags;
  53 };
  54
  55 /*
  56  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  57  * These configurations are characterized by voltage and speed for clocks.
  58  * The device is only validated for certain combinations. One way to express
  59  * these combinations is via the 'ratio's' which the clocks operate with
  60  * respect to each other. These ratio sets are for a given voltage/DPLL
  61  * setting. All configurations can be described by a DPLL setting and a ratio
  62  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  63  *
  64  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  65  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  66  * 2430 (iva2.1, NOdsp, mdm)
  67  */
  68
  69 /* Core fields for cm_clksel, not ratio governed */
  70 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  71 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  72 #define RX_CLKSEL_SSI                   (0x5 << 20)
  73
  74 /*-------------------------------------------------------------------------
  75  * Voltage/DPLL ratios
  76  *-------------------------------------------------------------------------*/
  77
  78 /* 2430 Ratio's, 2430-Ratio Config 1 */
  79 #define R1_CLKSEL_L3                    (4 << 0)
  80 #define R1_CLKSEL_L4                    (2 << 5)
  81 #define R1_CLKSEL_USB                   (4 << 25)
  82 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  83                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  84                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  85 #define R1_CLKSEL_MPU                   (2 << 0)
  86 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  87 #define R1_CLKSEL_DSP                   (2 << 0)
  88 #define R1_CLKSEL_DSP_IF                (2 << 5)
  89 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  90 #define R1_CLKSEL_GFX                   (2 << 0)
  91 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  92 #define R1_CLKSEL_MDM                   (4 << 0)
  93 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  94
  95 /* 2430-Ratio Config 2 */
  96 #define R2_CLKSEL_L3                    (6 << 0)
  97 #define R2_CLKSEL_L4                    (2 << 5)
  98 #define R2_CLKSEL_USB                   (2 << 25)
  99 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 100                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 101                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 102 #define R2_CLKSEL_MPU                   (2 << 0)
 103 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 104 #define R2_CLKSEL_DSP                   (2 << 0)
 105 #define R2_CLKSEL_DSP_IF                (3 << 5)
 106 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 107 #define R2_CLKSEL_GFX                   (2 << 0)
 108 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 109 #define R2_CLKSEL_MDM                   (6 << 0)
 110 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 111
 112 /* 2430-Ratio Bootm (BYPASS) */
 113 #define RB_CLKSEL_L3                    (1 << 0)
 114 #define RB_CLKSEL_L4                    (1 << 5)
 115 #define RB_CLKSEL_USB                   (1 << 25)
 116 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 117                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 118                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 119 #define RB_CLKSEL_MPU                   (1 << 0)
 120 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 121 #define RB_CLKSEL_DSP                   (1 << 0)
 122 #define RB_CLKSEL_DSP_IF                (1 << 5)
 123 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 124 #define RB_CLKSEL_GFX                   (1 << 0)
 125 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 126 #define RB_CLKSEL_MDM                   (1 << 0)
 127 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 128
 129 /* 2420 Ratio Equivalents */
 130 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 131 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 132
 133 /* 2420-PRCM III 532MHz core */
 134 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 135 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 136 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 137 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 138                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 139                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 140                                         RIII_CLKSEL_L3
 141 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 142 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 143 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 144 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 145 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 146 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 147 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 148 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 149                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 150                                         RIII_CLKSEL_DSP
 151 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 152 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 153
 154 /* 2420-PRCM II 600MHz core */
 155 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 156 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 157 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 158 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 159                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 160                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 161                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 162 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 163 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 164 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 165 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 166 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 167 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 168 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 169 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 170                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 171                                         RII_CLKSEL_DSP
 172 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 173 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 174
 175 /* 2420-PRCM I 660MHz core */
 176 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 177 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 178 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 179 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 180                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 181                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 182                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 183 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 184 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 185 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 186 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 187 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 188 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 189 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 190 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 191                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 192                                         RI_CLKSEL_DSP
 193 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 194 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 195
 196 /* 2420-PRCM VII (boot) */
 197 #define RVII_CLKSEL_L3                  (1 << 0)
 198 #define RVII_CLKSEL_L4                  (1 << 5)
 199 #define RVII_CLKSEL_DSS1                (1 << 8)
 200 #define RVII_CLKSEL_DSS2                (0 << 13)
 201 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 202 #define RVII_CLKSEL_SSI                 (1 << 20)
 203 #define RVII_CLKSEL_USB                 (1 << 25)
 204
 205 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 206                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 207                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 208
 209 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 210 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 211
 212 #define RVII_CLKSEL_DSP                 (1 << 0)
 213 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 214 #define RVII_SYNC_DSP                   (0 << 7)
 215 #define RVII_CLKSEL_IVA                 (1 << 8)
 216 #define RVII_SYNC_IVA                   (0 << 13)
 217 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 218                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 219
 220 #define RVII_CLKSEL_GFX                 (1 << 0)
 221 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 222
 223 /*-------------------------------------------------------------------------
 224  * 2430 Target modes: Along with each configuration the CPU has several
 225  * modes which goes along with them. Modes mainly are the addition of
 226  * describe DPLL combinations to go along with a ratio.
 227  *-------------------------------------------------------------------------*/
 228
 229 /* Hardware governed */
 230 #define MX_48M_SRC                      (0 << 3)
 231 #define MX_54M_SRC                      (0 << 5)
 232 #define MX_APLLS_CLIKIN_12              (3 << 23)
 233 #define MX_APLLS_CLIKIN_13              (2 << 23)
 234 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 235
 236 /*
 237  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 238  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 239  */
 240 #define M5A_DPLL_MULT_12                (133 << 12)
 241 #define M5A_DPLL_DIV_12                 (5 << 8)
 242 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 243                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 244                                         MX_APLLS_CLIKIN_12
 245 #define M5A_DPLL_MULT_13                (61 << 12)
 246 #define M5A_DPLL_DIV_13                 (2 << 8)
 247 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 248                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 249                                         MX_APLLS_CLIKIN_13
 250 #define M5A_DPLL_MULT_19                (55 << 12)
 251 #define M5A_DPLL_DIV_19                 (3 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 254                                         MX_APLLS_CLIKIN_19_2
 255 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 256 #define M5B_DPLL_MULT_12                (50 << 12)
 257 #define M5B_DPLL_DIV_12                 (2 << 8)
 258 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 260                                         MX_APLLS_CLIKIN_12
 261 #define M5B_DPLL_MULT_13                (200 << 12)
 262 #define M5B_DPLL_DIV_13                 (12 << 8)
 263
 264 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 265                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 266                                         MX_APLLS_CLIKIN_13
 267 #define M5B_DPLL_MULT_19                (125 << 12)
 268 #define M5B_DPLL_DIV_19                 (31 << 8)
 269 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 271                                         MX_APLLS_CLIKIN_19_2
 272 /*
 273  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 274  */
 275 #define M4_DPLL_MULT_12                 (133 << 12)
 276 #define M4_DPLL_DIV_12                  (3 << 8)
 277 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 278                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 279                                         MX_APLLS_CLIKIN_12
 280
 281 #define M4_DPLL_MULT_13                 (399 << 12)
 282 #define M4_DPLL_DIV_13                  (12 << 8)
 283 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 284                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 285                                         MX_APLLS_CLIKIN_13
 286
 287 #define M4_DPLL_MULT_19                 (145 << 12)
 288 #define M4_DPLL_DIV_19                  (6 << 8)
 289 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 290                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 291                                         MX_APLLS_CLIKIN_19_2
 292
 293 /*
 294  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 295  */
 296 #define M3_DPLL_MULT_12                 (55 << 12)
 297 #define M3_DPLL_DIV_12                  (1 << 8)
 298 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 300                                         MX_APLLS_CLIKIN_12
 301 #define M3_DPLL_MULT_13                 (76 << 12)
 302 #define M3_DPLL_DIV_13                  (2 << 8)
 303 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 304                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 305                                         MX_APLLS_CLIKIN_13
 306 #define M3_DPLL_MULT_19                 (17 << 12)
 307 #define M3_DPLL_DIV_19                  (0 << 8)
 308 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 309                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 310                                         MX_APLLS_CLIKIN_19_2
 311
 312 /*
 313  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 314  */
 315 #define M2_DPLL_MULT_12                 (55 << 12)
 316 #define M2_DPLL_DIV_12                  (1 << 8)
 317 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 318                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 319                                         MX_APLLS_CLIKIN_12
 320
 321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 322  * relock time issue */
 323 /* Core frequency changed from 330/165 to 329/164 MHz*/
 324 #define M2_DPLL_MULT_13                 (76 << 12)
 325 #define M2_DPLL_DIV_13                  (2 << 8)
 326 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 328                                         MX_APLLS_CLIKIN_13
 329
 330 #define M2_DPLL_MULT_19                 (17 << 12)
 331 #define M2_DPLL_DIV_19                  (0 << 8)
 332 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 333                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 334                                         MX_APLLS_CLIKIN_19_2
 335
 336 /* boot (boot) */
 337 #define MB_DPLL_MULT                    (1 << 12)
 338 #define MB_DPLL_DIV                     (0 << 8)
 339 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 340                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 341
 342 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 343                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 344
 345 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 346                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 347
 348 /*
 349  * 2430 - chassis (sedna)
 350  * 165 (ratio1) same as above #2
 351  * 150 (ratio1)
 352  * 133 (ratio2) same as above #4
 353  * 110 (ratio2) same as above #3
 354  * 104 (ratio2)
 355  * boot (boot)
 356  */
 357
 358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 359 #define MI_DPLL_MULT_12                 (55 << 12)
 360 #define MI_DPLL_DIV_12                  (1 << 8)
 361 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 362                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 363                                         MX_APLLS_CLIKIN_12
 364
 365 /*
 366  * 2420 Equivalent - mode registers
 367  * PRCM II , target DPLL = 2*300MHz = 600MHz
 368  */
 369 #define MII_DPLL_MULT_12                (50 << 12)
 370 #define MII_DPLL_DIV_12                 (1 << 8)
 371 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 372                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 373                                         MX_APLLS_CLIKIN_12
 374 #define MII_DPLL_MULT_13                (300 << 12)
 375 #define MII_DPLL_DIV_13                 (12 << 8)
 376 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 377                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 378                                         MX_APLLS_CLIKIN_13
 379
 380 /* PRCM III target DPLL = 2*266 = 532MHz*/
 381 #define MIII_DPLL_MULT_12               (133 << 12)
 382 #define MIII_DPLL_DIV_12                (5 << 8)
 383 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 384                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 385                                         MX_APLLS_CLIKIN_12
 386 #define MIII_DPLL_MULT_13               (266 << 12)
 387 #define MIII_DPLL_DIV_13                (12 << 8)
 388 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 389                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 390                                         MX_APLLS_CLIKIN_13
 391
 392 /* PRCM VII (boot bypass) */
 393 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 394 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 395
 396 /* High and low operation value */
 397 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 398 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 399
 400 /* MPU speed defines */
 401 #define S12M    12000000
 402 #define S13M    13000000
 403 #define S19M    19200000
 404 #define S26M    26000000
 405 #define S100M   100000000
 406 #define S133M   133000000
 407 #define S150M   150000000
 408 #define S164M   164000000
 409 #define S165M   165000000
 410 #define S199M   199000000
 411 #define S200M   200000000
 412 #define S266M   266000000
 413 #define S300M   300000000
 414 #define S329M   329000000
 415 #define S330M   330000000
 416 #define S399M   399000000
 417 #define S400M   400000000
 418 #define S532M   532000000
 419 #define S600M   600000000
 420 #define S658M   658000000
 421 #define S660M   660000000
 422 #define S798M   798000000
 423
 424 /*-------------------------------------------------------------------------
 425  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 426  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 427  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 428  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 429  *
 430  * Filling in table based on H4 boards and 2430-SDPs variants available.
 431  * There are quite a few more rates combinations which could be defined.
 432  *
 433  * When multiple values are defined the start up will try and choose the
 434  * fastest one. If a 'fast' value is defined, then automatically, the /2
 435  * one should be included as it can be used.    Generally having more that
 436  * one fast set does not make sense, as static timings need to be changed
 437  * to change the set.    The exception is the bypass setting which is
 438  * availble for low power bypass.
 439  *
 440  * Note: This table needs to be sorted, fastest to slowest.
 441  *-------------------------------------------------------------------------*/
 442 static struct prcm_config rate_table[] = {
 443         /* PRCM I - FAST */
 444         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 445                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 446                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 447                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 448                 RATE_IN_242X},
 449
 450         /* PRCM II - FAST */
 451         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 452                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 453                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 454                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 455                 RATE_IN_242X},
 456
 457         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 458                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 459                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 460                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 461                 RATE_IN_242X},
 462
 463         /* PRCM III - FAST */
 464         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 465                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 466                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 467                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 468                 RATE_IN_242X},
 469
 470         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 471                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 472                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 473                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 474                 RATE_IN_242X},
 475
 476         /* PRCM II - SLOW */
 477         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 478                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 479                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 480                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 481                 RATE_IN_242X},
 482
 483         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 484                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 485                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 487                 RATE_IN_242X},
 488
 489         /* PRCM III - SLOW */
 490         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 491                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 492                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 493                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 494                 RATE_IN_242X},
 495
 496         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 497                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 498                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 500                 RATE_IN_242X},
 501
 502         /* PRCM-VII (boot-bypass) */
 503         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 504                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 505                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 507                 RATE_IN_242X},
 508
 509         /* PRCM-VII (boot-bypass) */
 510         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 511                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 512                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 514                 RATE_IN_242X},
 515
 516         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 517         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 518                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 519                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 520                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 521                 SDRC_RFR_CTRL_133MHz,
 522                 RATE_IN_243X},
 523
 524         /* PRCM #2 - ratio1 (ES2) - FAST */
 525         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 526                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 527                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 528                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 529                 SDRC_RFR_CTRL_165MHz,
 530                 RATE_IN_243X},
 531
 532         /* PRCM #5a - ratio1 - FAST */
 533         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 534                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 535                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 536                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 537                 SDRC_RFR_CTRL_133MHz,
 538                 RATE_IN_243X},
 539
 540         /* PRCM #5b - ratio1 - FAST */
 541         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 542                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 543                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 544                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 545                 SDRC_RFR_CTRL_100MHz,
 546                 RATE_IN_243X},
 547
 548         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 549         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 550                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 551                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 552                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 553                 SDRC_RFR_CTRL_133MHz,
 554                 RATE_IN_243X},
 555
 556         /* PRCM #2 - ratio1 (ES2) - SLOW */
 557         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 558                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 559                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 560                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 561                 SDRC_RFR_CTRL_165MHz,
 562                 RATE_IN_243X},
 563
 564         /* PRCM #5a - ratio1 - SLOW */
 565         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 566                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 567                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 568                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 569                 SDRC_RFR_CTRL_133MHz,
 570                 RATE_IN_243X},
 571
 572         /* PRCM #5b - ratio1 - SLOW*/
 573         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 574                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 575                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 576                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 577                 SDRC_RFR_CTRL_100MHz,
 578                 RATE_IN_243X},
 579
 580         /* PRCM-boot/bypass */
 581         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 582                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 583                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 584                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 585                 SDRC_RFR_CTRL_BYPASS,
 586                 RATE_IN_243X},
 587
 588         /* PRCM-boot/bypass */
 589         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 590                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 591                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 592                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 593                 SDRC_RFR_CTRL_BYPASS,
 594                 RATE_IN_243X},
 595
 596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 597 };
 598
 599 /*-------------------------------------------------------------------------
 600  * 24xx clock tree.
 601  *
 602  * NOTE:In many cases here we are assigning a 'default' parent. In many
 603  *      cases the parent is selectable. The get/set parent calls will also
 604  *      switch sources.
 605  *
 606  *      Many some clocks say always_enabled, but they can be auto idled for
 607  *      power savings. They will always be available upon clock request.
 608  *
 609  *      Several sources are given initial rates which may be wrong, this will
 610  *      be fixed up in the init func.
 611  *
 612  *      Things are broadly separated below by clock domains. It is
 613  *      noteworthy that most periferals have dependencies on multiple clock
 614  *      domains. Many get their interface clocks from the L4 domain, but get
 615  *      functional clocks from fixed sources or other core domain derived
 616  *      clocks.
 617  *-------------------------------------------------------------------------*/
 618
 619 /* Base external input clocks */
 620 static struct clk func_32k_ck = {
 621         .name           = "func_32k_ck",
 622         .ops            = &clkops_null,
 623         .rate           = 32000,
 624         .flags          = RATE_FIXED | RATE_PROPAGATES,
 625         .clkdm_name     = "wkup_clkdm",
 626 };
 627
 628 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 629 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 630         .name           = "osc_ck",
 631         .ops            = &clkops_oscck,
 632         .flags          = RATE_PROPAGATES,
 633         .clkdm_name     = "wkup_clkdm",
 634         .recalc         = &omap2_osc_clk_recalc,
 635 };
 636
 637 /* Without modem likely 12MHz, with modem likely 13MHz */
 638 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 639         .name           = "sys_ck",             /* ~ ref_clk also */
 640         .ops            = &clkops_null,
 641         .parent         = &osc_ck,
 642         .flags          = RATE_PROPAGATES,
 643         .clkdm_name     = "wkup_clkdm",
 644         .recalc         = &omap2_sys_clk_recalc,
 645 };
 646
 647 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 648         .name           = "alt_ck",
 649         .ops            = &clkops_null,
 650         .rate           = 54000000,
 651         .flags          = RATE_FIXED | RATE_PROPAGATES,
 652         .clkdm_name     = "wkup_clkdm",
 653 };
 654
 655 /*
 656  * Analog domain root source clocks
 657  */
 658
 659 /* dpll_ck, is broken out in to special cases through clksel */
 660 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 661  * deal with this
 662  */
 663
 664 static struct dpll_data dpll_dd = {
 665         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 666         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 667         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 668         .max_multiplier         = 1024,
 669         .max_divider            = 16,
 670         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 671 };
 672
 673 /*
 674  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 675  * not just a DPLL
 676  */
 677 static struct clk dpll_ck = {
 678         .name           = "dpll_ck",
 679         .ops            = &clkops_null,
 680         .parent         = &sys_ck,              /* Can be func_32k also */
 681         .dpll_data      = &dpll_dd,
 682         .flags          = RATE_PROPAGATES,
 683         .clkdm_name     = "wkup_clkdm",
 684         .recalc         = &omap2_dpllcore_recalc,
 685         .set_rate       = &omap2_reprogram_dpllcore,
 686 };
 687
 688 static struct clk apll96_ck = {
 689         .name           = "apll96_ck",
 690         .ops            = &clkops_fixed,
 691         .parent         = &sys_ck,
 692         .rate           = 96000000,
 693         .flags          = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 694         .clkdm_name     = "wkup_clkdm",
 695         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 696         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 697 };
 698
 699 static struct clk apll54_ck = {
 700         .name           = "apll54_ck",
 701         .ops            = &clkops_fixed,
 702         .parent         = &sys_ck,
 703         .rate           = 54000000,
 704         .flags          = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 705         .clkdm_name     = "wkup_clkdm",
 706         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 707         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 708 };
 709
 710 /*
 711  * PRCM digital base sources
 712  */
 713
 714 /* func_54m_ck */
 715
 716 static const struct clksel_rate func_54m_apll54_rates[] = {
 717         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 718         { .div = 0 },
 719 };
 720
 721 static const struct clksel_rate func_54m_alt_rates[] = {
 722         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 723         { .div = 0 },
 724 };
 725
 726 static const struct clksel func_54m_clksel[] = {
 727         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 728         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 729         { .parent = NULL },
 730 };
 731
 732 static struct clk func_54m_ck = {
 733         .name           = "func_54m_ck",
 734         .ops            = &clkops_null,
 735         .parent         = &apll54_ck,   /* can also be alt_clk */
 736         .flags          = RATE_PROPAGATES,
 737         .clkdm_name     = "wkup_clkdm",
 738         .init           = &omap2_init_clksel_parent,
 739         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 740         .clksel_mask    = OMAP24XX_54M_SOURCE,
 741         .clksel         = func_54m_clksel,
 742         .recalc         = &omap2_clksel_recalc,
 743 };
 744
 745 static struct clk core_ck = {
 746         .name           = "core_ck",
 747         .ops            = &clkops_null,
 748         .parent         = &dpll_ck,             /* can also be 32k */
 749         .flags          = RATE_PROPAGATES,
 750         .clkdm_name     = "wkup_clkdm",
 751         .recalc         = &followparent_recalc,
 752 };
 753
 754 /* func_96m_ck */
 755 static const struct clksel_rate func_96m_apll96_rates[] = {
 756         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 757         { .div = 0 },
 758 };
 759
 760 static const struct clksel_rate func_96m_alt_rates[] = {
 761         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 762         { .div = 0 },
 763 };
 764
 765 static const struct clksel func_96m_clksel[] = {
 766         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 767         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 768         { .parent = NULL }
 769 };
 770
 771 /* The parent of this clock is not selectable on 2420. */
 772 static struct clk func_96m_ck = {
 773         .name           = "func_96m_ck",
 774         .ops            = &clkops_null,
 775         .parent         = &apll96_ck,
 776         .flags          = RATE_PROPAGATES,
 777         .clkdm_name     = "wkup_clkdm",
 778         .init           = &omap2_init_clksel_parent,
 779         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 780         .clksel_mask    = OMAP2430_96M_SOURCE,
 781         .clksel         = func_96m_clksel,
 782         .recalc         = &omap2_clksel_recalc,
 783         .round_rate     = &omap2_clksel_round_rate,
 784         .set_rate       = &omap2_clksel_set_rate
 785 };
 786
 787 /* func_48m_ck */
 788
 789 static const struct clksel_rate func_48m_apll96_rates[] = {
 790         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 791         { .div = 0 },
 792 };
 793
 794 static const struct clksel_rate func_48m_alt_rates[] = {
 795         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 796         { .div = 0 },
 797 };
 798
 799 static const struct clksel func_48m_clksel[] = {
 800         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 801         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 802         { .parent = NULL }
 803 };
 804
 805 static struct clk func_48m_ck = {
 806         .name           = "func_48m_ck",
 807         .ops            = &clkops_null,
 808         .parent         = &apll96_ck,    /* 96M or Alt */
 809         .flags          = RATE_PROPAGATES,
 810         .clkdm_name     = "wkup_clkdm",
 811         .init           = &omap2_init_clksel_parent,
 812         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 813         .clksel_mask    = OMAP24XX_48M_SOURCE,
 814         .clksel         = func_48m_clksel,
 815         .recalc         = &omap2_clksel_recalc,
 816         .round_rate     = &omap2_clksel_round_rate,
 817         .set_rate       = &omap2_clksel_set_rate
 818 };
 819
 820 static struct clk func_12m_ck = {
 821         .name           = "func_12m_ck",
 822         .ops            = &clkops_null,
 823         .parent         = &func_48m_ck,
 824         .fixed_div      = 4,
 825         .flags          = RATE_PROPAGATES,
 826         .clkdm_name     = "wkup_clkdm",
 827         .recalc         = &omap2_fixed_divisor_recalc,
 828 };
 829
 830 /* Secure timer, only available in secure mode */
 831 static struct clk wdt1_osc_ck = {
 832         .name           = "ck_wdt1_osc",
 833         .ops            = &clkops_null, /* RMK: missing? */
 834         .parent         = &osc_ck,
 835         .recalc         = &followparent_recalc,
 836 };
 837
 838 /*
 839  * The common_clkout* clksel_rate structs are common to
 840  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 841  * sys_clkout2_* are 2420-only, so the
 842  * clksel_rate flags fields are inaccurate for those clocks. This is
 843  * harmless since access to those clocks are gated by the struct clk
 844  * flags fields, which mark them as 2420-only.
 845  */
 846 static const struct clksel_rate common_clkout_src_core_rates[] = {
 847         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 848         { .div = 0 }
 849 };
 850
 851 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 852         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 853         { .div = 0 }
 854 };
 855
 856 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 857         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 858         { .div = 0 }
 859 };
 860
 861 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 862         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 863         { .div = 0 }
 864 };
 865
 866 static const struct clksel common_clkout_src_clksel[] = {
 867         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 868         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 869         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 870         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 871         { .parent = NULL }
 872 };
 873
 874 static struct clk sys_clkout_src = {
 875         .name           = "sys_clkout_src",
 876         .ops            = &clkops_omap2_dflt,
 877         .parent         = &func_54m_ck,
 878         .flags          = RATE_PROPAGATES,
 879         .clkdm_name     = "wkup_clkdm",
 880         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 881         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 882         .init           = &omap2_init_clksel_parent,
 883         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 884         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 885         .clksel         = common_clkout_src_clksel,
 886         .recalc         = &omap2_clksel_recalc,
 887         .round_rate     = &omap2_clksel_round_rate,
 888         .set_rate       = &omap2_clksel_set_rate
 889 };
 890
 891 static const struct clksel_rate common_clkout_rates[] = {
 892         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 893         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 894         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 895         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 896         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 897         { .div = 0 },
 898 };
 899
 900 static const struct clksel sys_clkout_clksel[] = {
 901         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 902         { .parent = NULL }
 903 };
 904
 905 static struct clk sys_clkout = {
 906         .name           = "sys_clkout",
 907         .ops            = &clkops_null,
 908         .parent         = &sys_clkout_src,
 909         .clkdm_name     = "wkup_clkdm",
 910         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 911         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 912         .clksel         = sys_clkout_clksel,
 913         .recalc         = &omap2_clksel_recalc,
 914         .round_rate     = &omap2_clksel_round_rate,
 915         .set_rate       = &omap2_clksel_set_rate
 916 };
 917
 918 /* In 2430, new in 2420 ES2 */
 919 static struct clk sys_clkout2_src = {
 920         .name           = "sys_clkout2_src",
 921         .ops            = &clkops_omap2_dflt,
 922         .parent         = &func_54m_ck,
 923         .flags          = RATE_PROPAGATES,
 924         .clkdm_name     = "wkup_clkdm",
 925         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 926         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 927         .init           = &omap2_init_clksel_parent,
 928         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 929         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 930         .clksel         = common_clkout_src_clksel,
 931         .recalc         = &omap2_clksel_recalc,
 932         .round_rate     = &omap2_clksel_round_rate,
 933         .set_rate       = &omap2_clksel_set_rate
 934 };
 935
 936 static const struct clksel sys_clkout2_clksel[] = {
 937         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 938         { .parent = NULL }
 939 };
 940
 941 /* In 2430, new in 2420 ES2 */
 942 static struct clk sys_clkout2 = {
 943         .name           = "sys_clkout2",
 944         .ops            = &clkops_null,
 945         .parent         = &sys_clkout2_src,
 946         .clkdm_name     = "wkup_clkdm",
 947         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 948         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 949         .clksel         = sys_clkout2_clksel,
 950         .recalc         = &omap2_clksel_recalc,
 951         .round_rate     = &omap2_clksel_round_rate,
 952         .set_rate       = &omap2_clksel_set_rate
 953 };
 954
 955 static struct clk emul_ck = {
 956         .name           = "emul_ck",
 957         .ops            = &clkops_omap2_dflt,
 958         .parent         = &func_54m_ck,
 959         .clkdm_name     = "wkup_clkdm",
 960         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 961         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 962         .recalc         = &followparent_recalc,
 963
 964 };
 965
 966 /*
 967  * MPU clock domain
 968  *      Clocks:
 969  *              MPU_FCLK, MPU_ICLK
 970  *              INT_M_FCLK, INT_M_I_CLK
 971  *
 972  * - Individual clocks are hardware managed.
 973  * - Base divider comes from: CM_CLKSEL_MPU
 974  *
 975  */
 976 static const struct clksel_rate mpu_core_rates[] = {
 977         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 978         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 979         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 980         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 981         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 982         { .div = 0 },
 983 };
 984
 985 static const struct clksel mpu_clksel[] = {
 986         { .parent = &core_ck, .rates = mpu_core_rates },
 987         { .parent = NULL }
 988 };
 989
 990 static struct clk mpu_ck = {    /* Control cpu */
 991         .name           = "mpu_ck",
 992         .ops            = &clkops_null,
 993         .parent         = &core_ck,
 994         .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 995         .clkdm_name     = "mpu_clkdm",
 996         .init           = &omap2_init_clksel_parent,
 997         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 998         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 999         .clksel         = mpu_clksel,
1000         .recalc         = &omap2_clksel_recalc,
1001         .round_rate     = &omap2_clksel_round_rate,
1002         .set_rate       = &omap2_clksel_set_rate
1003 };
1004
1005 /*
1006  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1007  * Clocks:
1008  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1009  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1010  *
1011  * Won't be too specific here. The core clock comes into this block
1012  * it is divided then tee'ed. One branch goes directly to xyz enable
1013  * controls. The other branch gets further divided by 2 then possibly
1014  * routed into a synchronizer and out of clocks abc.
1015  */
1016 static const struct clksel_rate dsp_fck_core_rates[] = {
1017         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1018         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1019         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1020         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1021         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1022         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1023         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1024         { .div = 0 },
1025 };
1026
1027 static const struct clksel dsp_fck_clksel[] = {
1028         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1029         { .parent = NULL }
1030 };
1031
1032 static struct clk dsp_fck = {
1033         .name           = "dsp_fck",
1034         .ops            = &clkops_omap2_dflt_wait,
1035         .parent         = &core_ck,
1036         .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1037         .clkdm_name     = "dsp_clkdm",
1038         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1039         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1040         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1041         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1042         .clksel         = dsp_fck_clksel,
1043         .recalc         = &omap2_clksel_recalc,
1044         .round_rate     = &omap2_clksel_round_rate,
1045         .set_rate       = &omap2_clksel_set_rate
1046 };
1047
1048 /* DSP interface clock */
1049 static const struct clksel_rate dsp_irate_ick_rates[] = {
1050         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1051         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1052         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1053         { .div = 0 },
1054 };
1055
1056 static const struct clksel dsp_irate_ick_clksel[] = {
1057         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1058         { .parent = NULL }
1059 };
1060
1061 /* This clock does not exist as such in the TRM. */
1062 static struct clk dsp_irate_ick = {
1063         .name           = "dsp_irate_ick",
1064         .ops            = &clkops_null,
1065         .parent         = &dsp_fck,
1066         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1067         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1068         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1069         .clksel         = dsp_irate_ick_clksel,
1070         .recalc         = &omap2_clksel_recalc,
1071         .round_rate     = &omap2_clksel_round_rate,
1072         .set_rate             = &omap2_clksel_set_rate
1073 };
1074
1075 /* 2420 only */
1076 static struct clk dsp_ick = {
1077         .name           = "dsp_ick",     /* apparently ipi and isp */
1078         .ops            = &clkops_omap2_dflt_wait,
1079         .parent         = &dsp_irate_ick,
1080         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1081         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1082         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1083 };
1084
1085 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1086 static struct clk iva2_1_ick = {
1087         .name           = "iva2_1_ick",
1088         .ops            = &clkops_omap2_dflt_wait,
1089         .parent         = &dsp_irate_ick,
1090         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1091         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1092         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1093 };
1094
1095 /*
1096  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1097  * the C54x, but which is contained in the DSP powerdomain.  Does not
1098  * exist on later OMAPs.
1099  */
1100 static struct clk iva1_ifck = {
1101         .name           = "iva1_ifck",
1102         .ops            = &clkops_omap2_dflt_wait,
1103         .parent         = &core_ck,
1104         .flags          = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
1105         .clkdm_name     = "iva1_clkdm",
1106         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1107         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1108         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1109         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1110         .clksel         = dsp_fck_clksel,
1111         .recalc         = &omap2_clksel_recalc,
1112         .round_rate     = &omap2_clksel_round_rate,
1113         .set_rate       = &omap2_clksel_set_rate
1114 };
1115
1116 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1117 static struct clk iva1_mpu_int_ifck = {
1118         .name           = "iva1_mpu_int_ifck",
1119         .ops            = &clkops_omap2_dflt_wait,
1120         .parent         = &iva1_ifck,
1121         .clkdm_name     = "iva1_clkdm",
1122         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1123         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1124         .fixed_div      = 2,
1125         .recalc         = &omap2_fixed_divisor_recalc,
1126 };
1127
1128 /*
1129  * L3 clock domain
1130  * L3 clocks are used for both interface and functional clocks to
1131  * multiple entities. Some of these clocks are completely managed
1132  * by hardware, and some others allow software control. Hardware
1133  * managed ones general are based on directly CLK_REQ signals and
1134  * various auto idle settings. The functional spec sets many of these
1135  * as 'tie-high' for their enables.
1136  *
1137  * I-CLOCKS:
1138  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1139  *      CAM, HS-USB.
1140  * F-CLOCK
1141  *      SSI.
1142  *
1143  * GPMC memories and SDRC have timing and clock sensitive registers which
1144  * may very well need notification when the clock changes. Currently for low
1145  * operating points, these are taken care of in sleep.S.
1146  */
1147 static const struct clksel_rate core_l3_core_rates[] = {
1148         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1149         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1150         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1151         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1152         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1153         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1154         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1155         { .div = 0 }
1156 };
1157
1158 static const struct clksel core_l3_clksel[] = {
1159         { .parent = &core_ck, .rates = core_l3_core_rates },
1160         { .parent = NULL }
1161 };
1162
1163 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1164         .name           = "core_l3_ck",
1165         .ops            = &clkops_null,
1166         .parent         = &core_ck,
1167         .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
1168         .clkdm_name     = "core_l3_clkdm",
1169         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1170         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1171         .clksel         = core_l3_clksel,
1172         .recalc         = &omap2_clksel_recalc,
1173         .round_rate     = &omap2_clksel_round_rate,
1174         .set_rate       = &omap2_clksel_set_rate
1175 };
1176
1177 /* usb_l4_ick */
1178 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1179         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1180         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1181         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1182         { .div = 0 }
1183 };
1184
1185 static const struct clksel usb_l4_ick_clksel[] = {
1186         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1187         { .parent = NULL },
1188 };
1189
1190 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1191 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1192         .name           = "usb_l4_ick",
1193         .ops            = &clkops_omap2_dflt_wait,
1194         .parent         = &core_l3_ck,
1195         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1196         .clkdm_name     = "core_l4_clkdm",
1197         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1198         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1199         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1200         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1201         .clksel         = usb_l4_ick_clksel,
1202         .recalc         = &omap2_clksel_recalc,
1203         .round_rate     = &omap2_clksel_round_rate,
1204         .set_rate       = &omap2_clksel_set_rate
1205 };
1206
1207 /*
1208  * L4 clock management domain
1209  *
1210  * This domain contains lots of interface clocks from the L4 interface, some
1211  * functional clocks.   Fixed APLL functional source clocks are managed in
1212  * this domain.
1213  */
1214 static const struct clksel_rate l4_core_l3_rates[] = {
1215         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1216         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1217         { .div = 0 }
1218 };
1219
1220 static const struct clksel l4_clksel[] = {
1221         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1222         { .parent = NULL }
1223 };
1224
1225 static struct clk l4_ck = {             /* used both as an ick and fck */
1226         .name           = "l4_ck",
1227         .ops            = &clkops_null,
1228         .parent         = &core_l3_ck,
1229         .flags          = DELAYED_APP | RATE_PROPAGATES,
1230         .clkdm_name     = "core_l4_clkdm",
1231         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1232         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1233         .clksel         = l4_clksel,
1234         .recalc         = &omap2_clksel_recalc,
1235         .round_rate     = &omap2_clksel_round_rate,
1236         .set_rate       = &omap2_clksel_set_rate
1237 };
1238
1239 /*
1240  * SSI is in L3 management domain, its direct parent is core not l3,
1241  * many core power domain entities are grouped into the L3 clock
1242  * domain.
1243  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1244  *
1245  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1246  */
1247 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1248         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1249         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1250         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1251         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1252         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1253         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1254         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1255         { .div = 0 }
1256 };
1257
1258 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1259         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1260         { .parent = NULL }
1261 };
1262
1263 static struct clk ssi_ssr_sst_fck = {
1264         .name           = "ssi_fck",
1265         .ops            = &clkops_omap2_dflt_wait,
1266         .parent         = &core_ck,
1267         .flags          = DELAYED_APP,
1268         .clkdm_name     = "core_l3_clkdm",
1269         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1270         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1271         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1272         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1273         .clksel         = ssi_ssr_sst_fck_clksel,
1274         .recalc         = &omap2_clksel_recalc,
1275         .round_rate     = &omap2_clksel_round_rate,
1276         .set_rate       = &omap2_clksel_set_rate
1277 };
1278
1279
1280 /*
1281  * GFX clock domain
1282  *      Clocks:
1283  * GFX_FCLK, GFX_ICLK
1284  * GFX_CG1(2d), GFX_CG2(3d)
1285  *
1286  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1287  * The 2d and 3d clocks run at a hardware determined
1288  * divided value of fclk.
1289  *
1290  */
1291 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1292
1293 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1294 static const struct clksel gfx_fck_clksel[] = {
1295         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1296         { .parent = NULL },
1297 };
1298
1299 static struct clk gfx_3d_fck = {
1300         .name           = "gfx_3d_fck",
1301         .ops            = &clkops_omap2_dflt_wait,
1302         .parent         = &core_l3_ck,
1303         .clkdm_name     = "gfx_clkdm",
1304         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1305         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1306         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1307         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1308         .clksel         = gfx_fck_clksel,
1309         .recalc         = &omap2_clksel_recalc,
1310         .round_rate     = &omap2_clksel_round_rate,
1311         .set_rate       = &omap2_clksel_set_rate
1312 };
1313
1314 static struct clk gfx_2d_fck = {
1315         .name           = "gfx_2d_fck",
1316         .ops            = &clkops_omap2_dflt_wait,
1317         .parent         = &core_l3_ck,
1318         .clkdm_name     = "gfx_clkdm",
1319         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1320         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1321         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1322         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1323         .clksel         = gfx_fck_clksel,
1324         .recalc         = &omap2_clksel_recalc,
1325         .round_rate     = &omap2_clksel_round_rate,
1326         .set_rate       = &omap2_clksel_set_rate
1327 };
1328
1329 static struct clk gfx_ick = {
1330         .name           = "gfx_ick",            /* From l3 */
1331         .ops            = &clkops_omap2_dflt_wait,
1332         .parent         = &core_l3_ck,
1333         .clkdm_name     = "gfx_clkdm",
1334         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1335         .enable_bit     = OMAP_EN_GFX_SHIFT,
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 /*
1340  * Modem clock domain (2430)
1341  *      CLOCKS:
1342  *              MDM_OSC_CLK
1343  *              MDM_ICLK
1344  * These clocks are usable in chassis mode only.
1345  */
1346 static const struct clksel_rate mdm_ick_core_rates[] = {
1347         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1348         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1349         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1350         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1351         { .div = 0 }
1352 };
1353
1354 static const struct clksel mdm_ick_clksel[] = {
1355         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1356         { .parent = NULL }
1357 };
1358
1359 static struct clk mdm_ick = {           /* used both as a ick and fck */
1360         .name           = "mdm_ick",
1361         .ops            = &clkops_omap2_dflt_wait,
1362         .parent         = &core_ck,
1363         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1364         .clkdm_name     = "mdm_clkdm",
1365         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1366         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1367         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1368         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1369         .clksel         = mdm_ick_clksel,
1370         .recalc         = &omap2_clksel_recalc,
1371         .round_rate     = &omap2_clksel_round_rate,
1372         .set_rate       = &omap2_clksel_set_rate
1373 };
1374
1375 static struct clk mdm_osc_ck = {
1376         .name           = "mdm_osc_ck",
1377         .ops            = &clkops_omap2_dflt_wait,
1378         .parent         = &osc_ck,
1379         .clkdm_name     = "mdm_clkdm",
1380         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1381         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1382         .recalc         = &followparent_recalc,
1383 };
1384
1385 /*
1386  * DSS clock domain
1387  * CLOCKs:
1388  * DSS_L4_ICLK, DSS_L3_ICLK,
1389  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1390  *
1391  * DSS is both initiator and target.
1392  */
1393 /* XXX Add RATE_NOT_VALIDATED */
1394
1395 static const struct clksel_rate dss1_fck_sys_rates[] = {
1396         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1397         { .div = 0 }
1398 };
1399
1400 static const struct clksel_rate dss1_fck_core_rates[] = {
1401         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1402         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1403         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1404         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1405         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1406         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1407         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1408         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1409         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1410         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1411         { .div = 0 }
1412 };
1413
1414 static const struct clksel dss1_fck_clksel[] = {
1415         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1416         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1417         { .parent = NULL },
1418 };
1419
1420 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1421         .name           = "dss_ick",
1422         .ops            = &clkops_omap2_dflt,
1423         .parent         = &l4_ck,       /* really both l3 and l4 */
1424         .clkdm_name     = "dss_clkdm",
1425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1426         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk dss1_fck = {
1431         .name           = "dss1_fck",
1432         .ops            = &clkops_omap2_dflt,
1433         .parent         = &core_ck,             /* Core or sys */
1434         .flags          = DELAYED_APP,
1435         .clkdm_name     = "dss_clkdm",
1436         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1438         .init           = &omap2_init_clksel_parent,
1439         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1440         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1441         .clksel         = dss1_fck_clksel,
1442         .recalc         = &omap2_clksel_recalc,
1443         .round_rate     = &omap2_clksel_round_rate,
1444         .set_rate       = &omap2_clksel_set_rate
1445 };
1446
1447 static const struct clksel_rate dss2_fck_sys_rates[] = {
1448         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1449         { .div = 0 }
1450 };
1451
1452 static const struct clksel_rate dss2_fck_48m_rates[] = {
1453         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1454         { .div = 0 }
1455 };
1456
1457 static const struct clksel dss2_fck_clksel[] = {
1458         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1459         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1460         { .parent = NULL }
1461 };
1462
1463 static struct clk dss2_fck = {          /* Alt clk used in power management */
1464         .name           = "dss2_fck",
1465         .ops            = &clkops_omap2_dflt,
1466         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1467         .flags          = DELAYED_APP,
1468         .clkdm_name     = "dss_clkdm",
1469         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1470         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1471         .init           = &omap2_init_clksel_parent,
1472         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1473         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1474         .clksel         = dss2_fck_clksel,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1479         .name           = "dss_54m_fck",        /* 54m tv clk */
1480         .ops            = &clkops_omap2_dflt_wait,
1481         .parent         = &func_54m_ck,
1482         .clkdm_name     = "dss_clkdm",
1483         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1485         .recalc         = &followparent_recalc,
1486 };
1487
1488 /*
1489  * CORE power domain ICLK & FCLK defines.
1490  * Many of the these can have more than one possible parent. Entries
1491  * here will likely have an L4 interface parent, and may have multiple
1492  * functional clock parents.
1493  */
1494 static const struct clksel_rate gpt_alt_rates[] = {
1495         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1496         { .div = 0 }
1497 };
1498
1499 static const struct clksel omap24xx_gpt_clksel[] = {
1500         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1501         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1502         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1503         { .parent = NULL },
1504 };
1505
1506 static struct clk gpt1_ick = {
1507         .name           = "gpt1_ick",
1508         .ops            = &clkops_omap2_dflt_wait,
1509         .parent         = &l4_ck,
1510         .clkdm_name     = "core_l4_clkdm",
1511         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1512         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1513         .recalc         = &followparent_recalc,
1514 };
1515
1516 static struct clk gpt1_fck = {
1517         .name           = "gpt1_fck",
1518         .ops            = &clkops_omap2_dflt_wait,
1519         .parent         = &func_32k_ck,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1522         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1523         .init           = &omap2_init_clksel_parent,
1524         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1525         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1526         .clksel         = omap24xx_gpt_clksel,
1527         .recalc         = &omap2_clksel_recalc,
1528         .round_rate     = &omap2_clksel_round_rate,
1529         .set_rate       = &omap2_clksel_set_rate
1530 };
1531
1532 static struct clk gpt2_ick = {
1533         .name           = "gpt2_ick",
1534         .ops            = &clkops_omap2_dflt_wait,
1535         .parent         = &l4_ck,
1536         .clkdm_name     = "core_l4_clkdm",
1537         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1538         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk gpt2_fck = {
1543         .name           = "gpt2_fck",
1544         .ops            = &clkops_omap2_dflt_wait,
1545         .parent         = &func_32k_ck,
1546         .clkdm_name     = "core_l4_clkdm",
1547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1549         .init           = &omap2_init_clksel_parent,
1550         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1551         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1552         .clksel         = omap24xx_gpt_clksel,
1553         .recalc         = &omap2_clksel_recalc,
1554 };
1555
1556 static struct clk gpt3_ick = {
1557         .name           = "gpt3_ick",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .parent         = &l4_ck,
1560         .clkdm_name     = "core_l4_clkdm",
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1562         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk gpt3_fck = {
1567         .name           = "gpt3_fck",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .parent         = &func_32k_ck,
1570         .clkdm_name     = "core_l4_clkdm",
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1573         .init           = &omap2_init_clksel_parent,
1574         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1575         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1576         .clksel         = omap24xx_gpt_clksel,
1577         .recalc         = &omap2_clksel_recalc,
1578 };
1579
1580 static struct clk gpt4_ick = {
1581         .name           = "gpt4_ick",
1582         .ops            = &clkops_omap2_dflt_wait,
1583         .parent         = &l4_ck,
1584         .clkdm_name     = "core_l4_clkdm",
1585         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1586         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1587         .recalc         = &followparent_recalc,
1588 };
1589
1590 static struct clk gpt4_fck = {
1591         .name           = "gpt4_fck",
1592         .ops            = &clkops_omap2_dflt_wait,
1593         .parent         = &func_32k_ck,
1594         .clkdm_name     = "core_l4_clkdm",
1595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1596         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1597         .init           = &omap2_init_clksel_parent,
1598         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1599         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1600         .clksel         = omap24xx_gpt_clksel,
1601         .recalc         = &omap2_clksel_recalc,
1602 };
1603
1604 static struct clk gpt5_ick = {
1605         .name           = "gpt5_ick",
1606         .ops            = &clkops_omap2_dflt_wait,
1607         .parent         = &l4_ck,
1608         .clkdm_name     = "core_l4_clkdm",
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1610         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk gpt5_fck = {
1615         .name           = "gpt5_fck",
1616         .ops            = &clkops_omap2_dflt_wait,
1617         .parent         = &func_32k_ck,
1618         .clkdm_name     = "core_l4_clkdm",
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1621         .init           = &omap2_init_clksel_parent,
1622         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1623         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1624         .clksel         = omap24xx_gpt_clksel,
1625         .recalc         = &omap2_clksel_recalc,
1626 };
1627
1628 static struct clk gpt6_ick = {
1629         .name           = "gpt6_ick",
1630         .ops            = &clkops_omap2_dflt_wait,
1631         .parent         = &l4_ck,
1632         .clkdm_name     = "core_l4_clkdm",
1633         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1634         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1635         .recalc         = &followparent_recalc,
1636 };
1637
1638 static struct clk gpt6_fck = {
1639         .name           = "gpt6_fck",
1640         .ops            = &clkops_omap2_dflt_wait,
1641         .parent         = &func_32k_ck,
1642         .clkdm_name     = "core_l4_clkdm",
1643         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1645         .init           = &omap2_init_clksel_parent,
1646         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1647         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1648         .clksel         = omap24xx_gpt_clksel,
1649         .recalc         = &omap2_clksel_recalc,
1650 };
1651
1652 static struct clk gpt7_ick = {
1653         .name           = "gpt7_ick",
1654         .ops            = &clkops_omap2_dflt_wait,
1655         .parent         = &l4_ck,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1657         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1658         .recalc         = &followparent_recalc,
1659 };
1660
1661 static struct clk gpt7_fck = {
1662         .name           = "gpt7_fck",
1663         .ops            = &clkops_omap2_dflt_wait,
1664         .parent         = &func_32k_ck,
1665         .clkdm_name     = "core_l4_clkdm",
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1667         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1668         .init           = &omap2_init_clksel_parent,
1669         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1670         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1671         .clksel         = omap24xx_gpt_clksel,
1672         .recalc         = &omap2_clksel_recalc,
1673 };
1674
1675 static struct clk gpt8_ick = {
1676         .name           = "gpt8_ick",
1677         .ops            = &clkops_omap2_dflt_wait,
1678         .parent         = &l4_ck,
1679         .clkdm_name     = "core_l4_clkdm",
1680         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1682         .recalc         = &followparent_recalc,
1683 };
1684
1685 static struct clk gpt8_fck = {
1686         .name           = "gpt8_fck",
1687         .ops            = &clkops_omap2_dflt_wait,
1688         .parent         = &func_32k_ck,
1689         .clkdm_name     = "core_l4_clkdm",
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1692         .init           = &omap2_init_clksel_parent,
1693         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1694         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1695         .clksel         = omap24xx_gpt_clksel,
1696         .recalc         = &omap2_clksel_recalc,
1697 };
1698
1699 static struct clk gpt9_ick = {
1700         .name           = "gpt9_ick",
1701         .ops            = &clkops_omap2_dflt_wait,
1702         .parent         = &l4_ck,
1703         .clkdm_name     = "core_l4_clkdm",
1704         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1705         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk gpt9_fck = {
1710         .name           = "gpt9_fck",
1711         .ops            = &clkops_omap2_dflt_wait,
1712         .parent         = &func_32k_ck,
1713         .clkdm_name     = "core_l4_clkdm",
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1715         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1716         .init           = &omap2_init_clksel_parent,
1717         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1718         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1719         .clksel         = omap24xx_gpt_clksel,
1720         .recalc         = &omap2_clksel_recalc,
1721 };
1722
1723 static struct clk gpt10_ick = {
1724         .name           = "gpt10_ick",
1725         .ops            = &clkops_omap2_dflt_wait,
1726         .parent         = &l4_ck,
1727         .clkdm_name     = "core_l4_clkdm",
1728         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1729         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 static struct clk gpt10_fck = {
1734         .name           = "gpt10_fck",
1735         .ops            = &clkops_omap2_dflt_wait,
1736         .parent         = &func_32k_ck,
1737         .clkdm_name     = "core_l4_clkdm",
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1739         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1740         .init           = &omap2_init_clksel_parent,
1741         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1742         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1743         .clksel         = omap24xx_gpt_clksel,
1744         .recalc         = &omap2_clksel_recalc,
1745 };
1746
1747 static struct clk gpt11_ick = {
1748         .name           = "gpt11_ick",
1749         .ops            = &clkops_omap2_dflt_wait,
1750         .parent         = &l4_ck,
1751         .clkdm_name     = "core_l4_clkdm",
1752         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1753         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 static struct clk gpt11_fck = {
1758         .name           = "gpt11_fck",
1759         .ops            = &clkops_omap2_dflt_wait,
1760         .parent         = &func_32k_ck,
1761         .clkdm_name     = "core_l4_clkdm",
1762         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1763         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1764         .init           = &omap2_init_clksel_parent,
1765         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1766         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1767         .clksel         = omap24xx_gpt_clksel,
1768         .recalc         = &omap2_clksel_recalc,
1769 };
1770
1771 static struct clk gpt12_ick = {
1772         .name           = "gpt12_ick",
1773         .ops            = &clkops_omap2_dflt_wait,
1774         .parent         = &l4_ck,
1775         .clkdm_name     = "core_l4_clkdm",
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk gpt12_fck = {
1782         .name           = "gpt12_fck",
1783         .ops            = &clkops_omap2_dflt_wait,
1784         .parent         = &func_32k_ck,
1785         .clkdm_name     = "core_l4_clkdm",
1786         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1787         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1788         .init           = &omap2_init_clksel_parent,
1789         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1790         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1791         .clksel         = omap24xx_gpt_clksel,
1792         .recalc         = &omap2_clksel_recalc,
1793 };
1794
1795 static struct clk mcbsp1_ick = {
1796         .name           = "mcbsp_ick",
1797         .ops            = &clkops_omap2_dflt_wait,
1798         .id             = 1,
1799         .parent         = &l4_ck,
1800         .clkdm_name     = "core_l4_clkdm",
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mcbsp1_fck = {
1807         .name           = "mcbsp_fck",
1808         .ops            = &clkops_omap2_dflt_wait,
1809         .id             = 1,
1810         .parent         = &func_96m_ck,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1813         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mcbsp2_ick = {
1818         .name           = "mcbsp_ick",
1819         .ops            = &clkops_omap2_dflt_wait,
1820         .id             = 2,
1821         .parent         = &l4_ck,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk mcbsp2_fck = {
1829         .name           = "mcbsp_fck",
1830         .ops            = &clkops_omap2_dflt_wait,
1831         .id             = 2,
1832         .parent         = &func_96m_ck,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1835         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk mcbsp3_ick = {
1840         .name           = "mcbsp_ick",
1841         .ops            = &clkops_omap2_dflt_wait,
1842         .id             = 3,
1843         .parent         = &l4_ck,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1846         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mcbsp3_fck = {
1851         .name           = "mcbsp_fck",
1852         .ops            = &clkops_omap2_dflt_wait,
1853         .id             = 3,
1854         .parent         = &func_96m_ck,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1857         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk mcbsp4_ick = {
1862         .name           = "mcbsp_ick",
1863         .ops            = &clkops_omap2_dflt_wait,
1864         .id             = 4,
1865         .parent         = &l4_ck,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1868         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcbsp4_fck = {
1873         .name           = "mcbsp_fck",
1874         .ops            = &clkops_omap2_dflt_wait,
1875         .id             = 4,
1876         .parent         = &func_96m_ck,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1879         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk mcbsp5_ick = {
1884         .name           = "mcbsp_ick",
1885         .ops            = &clkops_omap2_dflt_wait,
1886         .id             = 5,
1887         .parent         = &l4_ck,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1890         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk mcbsp5_fck = {
1895         .name           = "mcbsp_fck",
1896         .ops            = &clkops_omap2_dflt_wait,
1897         .id             = 5,
1898         .parent         = &func_96m_ck,
1899         .clkdm_name     = "core_l4_clkdm",
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1901         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1902         .recalc         = &followparent_recalc,
1903 };
1904
1905 static struct clk mcspi1_ick = {
1906         .name           = "mcspi_ick",
1907         .ops            = &clkops_omap2_dflt_wait,
1908         .id             = 1,
1909         .parent         = &l4_ck,
1910         .clkdm_name     = "core_l4_clkdm",
1911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk mcspi1_fck = {
1917         .name           = "mcspi_fck",
1918         .ops            = &clkops_omap2_dflt_wait,
1919         .id             = 1,
1920         .parent         = &func_48m_ck,
1921         .clkdm_name     = "core_l4_clkdm",
1922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1923         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1924         .recalc         = &followparent_recalc,
1925 };
1926
1927 static struct clk mcspi2_ick = {
1928         .name           = "mcspi_ick",
1929         .ops            = &clkops_omap2_dflt_wait,
1930         .id             = 2,
1931         .parent         = &l4_ck,
1932         .clkdm_name     = "core_l4_clkdm",
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk mcspi2_fck = {
1939         .name           = "mcspi_fck",
1940         .ops            = &clkops_omap2_dflt_wait,
1941         .id             = 2,
1942         .parent         = &func_48m_ck,
1943         .clkdm_name     = "core_l4_clkdm",
1944         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1945         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk mcspi3_ick = {
1950         .name           = "mcspi_ick",
1951         .ops            = &clkops_omap2_dflt_wait,
1952         .id             = 3,
1953         .parent         = &l4_ck,
1954         .clkdm_name     = "core_l4_clkdm",
1955         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1956         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mcspi3_fck = {
1961         .name           = "mcspi_fck",
1962         .ops            = &clkops_omap2_dflt_wait,
1963         .id             = 3,
1964         .parent         = &func_48m_ck,
1965         .clkdm_name     = "core_l4_clkdm",
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1967         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk uart1_ick = {
1972         .name           = "uart1_ick",
1973         .ops            = &clkops_omap2_dflt_wait,
1974         .parent         = &l4_ck,
1975         .clkdm_name     = "core_l4_clkdm",
1976         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 static struct clk uart1_fck = {
1982         .name           = "uart1_fck",
1983         .ops            = &clkops_omap2_dflt_wait,
1984         .parent         = &func_48m_ck,
1985         .clkdm_name     = "core_l4_clkdm",
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1987         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk uart2_ick = {
1992         .name           = "uart2_ick",
1993         .ops            = &clkops_omap2_dflt_wait,
1994         .parent         = &l4_ck,
1995         .clkdm_name     = "core_l4_clkdm",
1996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1997         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk uart2_fck = {
2002         .name           = "uart2_fck",
2003         .ops            = &clkops_omap2_dflt_wait,
2004         .parent         = &func_48m_ck,
2005         .clkdm_name     = "core_l4_clkdm",
2006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2007         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2008         .recalc         = &followparent_recalc,
2009 };
2010
2011 static struct clk uart3_ick = {
2012         .name           = "uart3_ick",
2013         .ops            = &clkops_omap2_dflt_wait,
2014         .parent         = &l4_ck,
2015         .clkdm_name     = "core_l4_clkdm",
2016         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2017         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2018         .recalc         = &followparent_recalc,
2019 };
2020
2021 static struct clk uart3_fck = {
2022         .name           = "uart3_fck",
2023         .ops            = &clkops_omap2_dflt_wait,
2024         .parent         = &func_48m_ck,
2025         .clkdm_name     = "core_l4_clkdm",
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2027         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk gpios_ick = {
2032         .name           = "gpios_ick",
2033         .ops            = &clkops_omap2_dflt_wait,
2034         .parent         = &l4_ck,
2035         .clkdm_name     = "core_l4_clkdm",
2036         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2037         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk gpios_fck = {
2042         .name           = "gpios_fck",
2043         .ops            = &clkops_omap2_dflt_wait,
2044         .parent         = &func_32k_ck,
2045         .clkdm_name     = "wkup_clkdm",
2046         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2047         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk mpu_wdt_ick = {
2052         .name           = "mpu_wdt_ick",
2053         .ops            = &clkops_omap2_dflt_wait,
2054         .parent         = &l4_ck,
2055         .clkdm_name     = "core_l4_clkdm",
2056         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2057         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk mpu_wdt_fck = {
2062         .name           = "mpu_wdt_fck",
2063         .ops            = &clkops_omap2_dflt_wait,
2064         .parent         = &func_32k_ck,
2065         .clkdm_name     = "wkup_clkdm",
2066         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2067         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk sync_32k_ick = {
2072         .name           = "sync_32k_ick",
2073         .ops            = &clkops_omap2_dflt_wait,
2074         .parent         = &l4_ck,
2075         .flags          = ENABLE_ON_INIT,
2076         .clkdm_name     = "core_l4_clkdm",
2077         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2078         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 static struct clk wdt1_ick = {
2083         .name           = "wdt1_ick",
2084         .ops            = &clkops_omap2_dflt_wait,
2085         .parent         = &l4_ck,
2086         .clkdm_name     = "core_l4_clkdm",
2087         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2088         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk omapctrl_ick = {
2093         .name           = "omapctrl_ick",
2094         .ops            = &clkops_omap2_dflt_wait,
2095         .parent         = &l4_ck,
2096         .flags          = ENABLE_ON_INIT,
2097         .clkdm_name     = "core_l4_clkdm",
2098         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2099         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 static struct clk icr_ick = {
2104         .name           = "icr_ick",
2105         .ops            = &clkops_omap2_dflt_wait,
2106         .parent         = &l4_ck,
2107         .clkdm_name     = "core_l4_clkdm",
2108         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2109         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk cam_ick = {
2114         .name           = "cam_ick",
2115         .ops            = &clkops_omap2_dflt,
2116         .parent         = &l4_ck,
2117         .clkdm_name     = "core_l4_clkdm",
2118         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2119         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 /*
2124  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2125  * split into two separate clocks, since the parent clocks are different
2126  * and the clockdomains are also different.
2127  */
2128 static struct clk cam_fck = {
2129         .name           = "cam_fck",
2130         .ops            = &clkops_omap2_dflt,
2131         .parent         = &func_96m_ck,
2132         .clkdm_name     = "core_l3_clkdm",
2133         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2134         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk mailboxes_ick = {
2139         .name           = "mailboxes_ick",
2140         .ops            = &clkops_omap2_dflt_wait,
2141         .parent         = &l4_ck,
2142         .clkdm_name     = "core_l4_clkdm",
2143         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2144         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk wdt4_ick = {
2149         .name           = "wdt4_ick",
2150         .ops            = &clkops_omap2_dflt_wait,
2151         .parent         = &l4_ck,
2152         .clkdm_name     = "core_l4_clkdm",
2153         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2154         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk wdt4_fck = {
2159         .name           = "wdt4_fck",
2160         .ops            = &clkops_omap2_dflt_wait,
2161         .parent         = &func_32k_ck,
2162         .clkdm_name     = "core_l4_clkdm",
2163         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2164         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2165         .recalc         = &followparent_recalc,
2166 };
2167
2168 static struct clk wdt3_ick = {
2169         .name           = "wdt3_ick",
2170         .ops            = &clkops_omap2_dflt_wait,
2171         .parent         = &l4_ck,
2172         .clkdm_name     = "core_l4_clkdm",
2173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2174         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk wdt3_fck = {
2179         .name           = "wdt3_fck",
2180         .ops            = &clkops_omap2_dflt_wait,
2181         .parent         = &func_32k_ck,
2182         .clkdm_name     = "core_l4_clkdm",
2183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2184         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 static struct clk mspro_ick = {
2189         .name           = "mspro_ick",
2190         .ops            = &clkops_omap2_dflt_wait,
2191         .parent         = &l4_ck,
2192         .clkdm_name     = "core_l4_clkdm",
2193         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2194         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk mspro_fck = {
2199         .name           = "mspro_fck",
2200         .ops            = &clkops_omap2_dflt_wait,
2201         .parent         = &func_96m_ck,
2202         .clkdm_name     = "core_l4_clkdm",
2203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2204         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk mmc_ick = {
2209         .name           = "mmc_ick",
2210         .ops            = &clkops_omap2_dflt_wait,
2211         .parent         = &l4_ck,
2212         .clkdm_name     = "core_l4_clkdm",
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2214         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk mmc_fck = {
2219         .name           = "mmc_fck",
2220         .ops            = &clkops_omap2_dflt_wait,
2221         .parent         = &func_96m_ck,
2222         .clkdm_name     = "core_l4_clkdm",
2223         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2224         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk fac_ick = {
2229         .name           = "fac_ick",
2230         .ops            = &clkops_omap2_dflt_wait,
2231         .parent         = &l4_ck,
2232         .clkdm_name     = "core_l4_clkdm",
2233         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2234         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk fac_fck = {
2239         .name           = "fac_fck",
2240         .ops            = &clkops_omap2_dflt_wait,
2241         .parent         = &func_12m_ck,
2242         .clkdm_name     = "core_l4_clkdm",
2243         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2244         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2245         .recalc         = &followparent_recalc,
2246 };
2247
2248 static struct clk eac_ick = {
2249         .name           = "eac_ick",
2250         .ops            = &clkops_omap2_dflt_wait,
2251         .parent         = &l4_ck,
2252         .clkdm_name     = "core_l4_clkdm",
2253         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2254         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk eac_fck = {
2259         .name           = "eac_fck",
2260         .ops            = &clkops_omap2_dflt_wait,
2261         .parent         = &func_96m_ck,
2262         .clkdm_name     = "core_l4_clkdm",
2263         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2264         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 static struct clk hdq_ick = {
2269         .name           = "hdq_ick",
2270         .ops            = &clkops_omap2_dflt_wait,
2271         .parent         = &l4_ck,
2272         .clkdm_name     = "core_l4_clkdm",
2273         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2274         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 static struct clk hdq_fck = {
2279         .name           = "hdq_fck",
2280         .ops            = &clkops_omap2_dflt_wait,
2281         .parent         = &func_12m_ck,
2282         .clkdm_name     = "core_l4_clkdm",
2283         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2284         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2285         .recalc         = &followparent_recalc,
2286 };
2287
2288 static struct clk i2c2_ick = {
2289         .name           = "i2c_ick",
2290         .ops            = &clkops_omap2_dflt_wait,
2291         .id             = 2,
2292         .parent         = &l4_ck,
2293         .clkdm_name     = "core_l4_clkdm",
2294         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2295         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2296         .recalc         = &followparent_recalc,
2297 };
2298
2299 static struct clk i2c2_fck = {
2300         .name           = "i2c_fck",
2301         .ops            = &clkops_omap2_dflt_wait,
2302         .id             = 2,
2303         .parent         = &func_12m_ck,
2304         .clkdm_name     = "core_l4_clkdm",
2305         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2306         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2307         .recalc         = &followparent_recalc,
2308 };
2309
2310 static struct clk i2chs2_fck = {
2311         .name           = "i2c_fck",
2312         .ops            = &clkops_omap2_dflt_wait,
2313         .id             = 2,
2314         .parent         = &func_96m_ck,
2315         .clkdm_name     = "core_l4_clkdm",
2316         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2317         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2318         .recalc         = &followparent_recalc,
2319 };
2320
2321 static struct clk i2c1_ick = {
2322         .name           = "i2c_ick",
2323         .ops            = &clkops_omap2_dflt_wait,
2324         .id             = 1,
2325         .parent         = &l4_ck,
2326         .clkdm_name     = "core_l4_clkdm",
2327         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2328         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk i2c1_fck = {
2333         .name           = "i2c_fck",
2334         .ops            = &clkops_omap2_dflt_wait,
2335         .id             = 1,
2336         .parent         = &func_12m_ck,
2337         .clkdm_name     = "core_l4_clkdm",
2338         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2339         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk i2chs1_fck = {
2344         .name           = "i2c_fck",
2345         .ops            = &clkops_omap2_dflt_wait,
2346         .id             = 1,
2347         .parent         = &func_96m_ck,
2348         .clkdm_name     = "core_l4_clkdm",
2349         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2350         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk gpmc_fck = {
2355         .name           = "gpmc_fck",
2356         .ops            = &clkops_null, /* RMK: missing? */
2357         .parent         = &core_l3_ck,
2358         .flags          = ENABLE_ON_INIT,
2359         .clkdm_name     = "core_l3_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk sdma_fck = {
2364         .name           = "sdma_fck",
2365         .ops            = &clkops_null, /* RMK: missing? */
2366         .parent         = &core_l3_ck,
2367         .clkdm_name     = "core_l3_clkdm",
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 static struct clk sdma_ick = {
2372         .name           = "sdma_ick",
2373         .ops            = &clkops_null, /* RMK: missing? */
2374         .parent         = &l4_ck,
2375         .clkdm_name     = "core_l3_clkdm",
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk vlynq_ick = {
2380         .name           = "vlynq_ick",
2381         .ops            = &clkops_omap2_dflt_wait,
2382         .parent         = &core_l3_ck,
2383         .clkdm_name     = "core_l3_clkdm",
2384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2385         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2390         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2391         { .div = 0 }
2392 };
2393
2394 static const struct clksel_rate vlynq_fck_core_rates[] = {
2395         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2396         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2397         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2398         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2399         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2400         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2401         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2402         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2403         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2404         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2405         { .div = 0 }
2406 };
2407
2408 static const struct clksel vlynq_fck_clksel[] = {
2409         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2410         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2411         { .parent = NULL }
2412 };
2413
2414 static struct clk vlynq_fck = {
2415         .name           = "vlynq_fck",
2416         .ops            = &clkops_omap2_dflt_wait,
2417         .parent         = &func_96m_ck,
2418         .flags          = DELAYED_APP,
2419         .clkdm_name     = "core_l3_clkdm",
2420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2421         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2422         .init           = &omap2_init_clksel_parent,
2423         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2424         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2425         .clksel         = vlynq_fck_clksel,
2426         .recalc         = &omap2_clksel_recalc,
2427         .round_rate     = &omap2_clksel_round_rate,
2428         .set_rate       = &omap2_clksel_set_rate
2429 };
2430
2431 static struct clk sdrc_ick = {
2432         .name           = "sdrc_ick",
2433         .ops            = &clkops_omap2_dflt_wait,
2434         .parent         = &l4_ck,
2435         .flags          = ENABLE_ON_INIT,
2436         .clkdm_name     = "core_l4_clkdm",
2437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2438         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2439         .recalc         = &followparent_recalc,
2440 };
2441
2442 static struct clk des_ick = {
2443         .name           = "des_ick",
2444         .ops            = &clkops_omap2_dflt_wait,
2445         .parent         = &l4_ck,
2446         .clkdm_name     = "core_l4_clkdm",
2447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2448         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk sha_ick = {
2453         .name           = "sha_ick",
2454         .ops            = &clkops_omap2_dflt_wait,
2455         .parent         = &l4_ck,
2456         .clkdm_name     = "core_l4_clkdm",
2457         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2458         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk rng_ick = {
2463         .name           = "rng_ick",
2464         .ops            = &clkops_omap2_dflt_wait,
2465         .parent         = &l4_ck,
2466         .clkdm_name     = "core_l4_clkdm",
2467         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2468         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2469         .recalc         = &followparent_recalc,
2470 };
2471
2472 static struct clk aes_ick = {
2473         .name           = "aes_ick",
2474         .ops            = &clkops_omap2_dflt_wait,
2475         .parent         = &l4_ck,
2476         .clkdm_name     = "core_l4_clkdm",
2477         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2478         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2479         .recalc         = &followparent_recalc,
2480 };
2481
2482 static struct clk pka_ick = {
2483         .name           = "pka_ick",
2484         .ops            = &clkops_omap2_dflt_wait,
2485         .parent         = &l4_ck,
2486         .clkdm_name     = "core_l4_clkdm",
2487         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2488         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2489         .recalc         = &followparent_recalc,
2490 };
2491
2492 static struct clk usb_fck = {
2493         .name           = "usb_fck",
2494         .ops            = &clkops_omap2_dflt_wait,
2495         .parent         = &func_48m_ck,
2496         .clkdm_name     = "core_l3_clkdm",
2497         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2498         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2499         .recalc         = &followparent_recalc,
2500 };
2501
2502 static struct clk usbhs_ick = {
2503         .name           = "usbhs_ick",
2504         .ops            = &clkops_omap2_dflt_wait,
2505         .parent         = &core_l3_ck,
2506         .clkdm_name     = "core_l3_clkdm",
2507         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2508         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2509         .recalc         = &followparent_recalc,
2510 };
2511
2512 static struct clk mmchs1_ick = {
2513         .name           = "mmchs_ick",
2514         .ops            = &clkops_omap2_dflt_wait,
2515         .parent         = &l4_ck,
2516         .clkdm_name     = "core_l4_clkdm",
2517         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2518         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static struct clk mmchs1_fck = {
2523         .name           = "mmchs_fck",
2524         .ops            = &clkops_omap2_dflt_wait,
2525         .parent         = &func_96m_ck,
2526         .clkdm_name     = "core_l3_clkdm",
2527         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2528         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2529         .recalc         = &followparent_recalc,
2530 };
2531
2532 static struct clk mmchs2_ick = {
2533         .name           = "mmchs_ick",
2534         .ops            = &clkops_omap2_dflt_wait,
2535         .id             = 1,
2536         .parent         = &l4_ck,
2537         .clkdm_name     = "core_l4_clkdm",
2538         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2539         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2540         .recalc         = &followparent_recalc,
2541 };
2542
2543 static struct clk mmchs2_fck = {
2544         .name           = "mmchs_fck",
2545         .ops            = &clkops_omap2_dflt_wait,
2546         .id             = 1,
2547         .parent         = &func_96m_ck,
2548         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2549         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk gpio5_ick = {
2554         .name           = "gpio5_ick",
2555         .ops            = &clkops_omap2_dflt_wait,
2556         .parent         = &l4_ck,
2557         .clkdm_name     = "core_l4_clkdm",
2558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2559         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2560         .recalc         = &followparent_recalc,
2561 };
2562
2563 static struct clk gpio5_fck = {
2564         .name           = "gpio5_fck",
2565         .ops            = &clkops_omap2_dflt_wait,
2566         .parent         = &func_32k_ck,
2567         .clkdm_name     = "core_l4_clkdm",
2568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2569         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2570         .recalc         = &followparent_recalc,
2571 };
2572
2573 static struct clk mdm_intc_ick = {
2574         .name           = "mdm_intc_ick",
2575         .ops            = &clkops_omap2_dflt_wait,
2576         .parent         = &l4_ck,
2577         .clkdm_name     = "core_l4_clkdm",
2578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2579         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2580         .recalc         = &followparent_recalc,
2581 };
2582
2583 static struct clk mmchsdb1_fck = {
2584         .name           = "mmchsdb_fck",
2585         .ops            = &clkops_omap2_dflt_wait,
2586         .parent         = &func_32k_ck,
2587         .clkdm_name     = "core_l4_clkdm",
2588         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2589         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2590         .recalc         = &followparent_recalc,
2591 };
2592
2593 static struct clk mmchsdb2_fck = {
2594         .name           = "mmchsdb_fck",
2595         .ops            = &clkops_omap2_dflt_wait,
2596         .id             = 1,
2597         .parent         = &func_32k_ck,
2598         .clkdm_name     = "core_l4_clkdm",
2599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2600         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2601         .recalc         = &followparent_recalc,
2602 };
2603
2604 /*
2605  * This clock is a composite clock which does entire set changes then
2606  * forces a rebalance. It keys on the MPU speed, but it really could
2607  * be any key speed part of a set in the rate table.
2608  *
2609  * to really change a set, you need memory table sets which get changed
2610  * in sram, pre-notifiers & post notifiers, changing the top set, without
2611  * having low level display recalc's won't work... this is why dpm notifiers
2612  * work, isr's off, walk a list of clocks already _off_ and not messing with
2613  * the bus.
2614  *
2615  * This clock should have no parent. It embodies the entire upper level
2616  * active set. A parent will mess up some of the init also.
2617  */
2618 static struct clk virt_prcm_set = {
2619         .name           = "virt_prcm_set",
2620         .ops            = &clkops_null,
2621         .flags          = DELAYED_APP,
2622         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2623         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2624         .set_rate       = &omap2_select_table_rate,
2625         .round_rate     = &omap2_round_to_table_rate,
2626 };
2627
2628 #endif
2629