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   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/i2c-id.h>
  28 #include <linux/init.h>
  29 #include <linux/time.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/delay.h>
  32 #include <linux/errno.h>
  33 #include <linux/err.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40
  41 #include <asm/plat-s3c/regs-iic.h>
  42 #include <asm/plat-s3c/iic.h>
  43
  44 /* i2c controller state */
  45
  46 enum s3c24xx_i2c_state {
  47         STATE_IDLE,
  48         STATE_START,
  49         STATE_READ,
  50         STATE_WRITE,
  51         STATE_STOP
  52 };
  53
  54 struct s3c24xx_i2c {
  55         spinlock_t              lock;
  56         wait_queue_head_t       wait;
  57
  58         struct i2c_msg          *msg;
  59         unsigned int            msg_num;
  60         unsigned int            msg_idx;
  61         unsigned int            msg_ptr;
  62
  63         unsigned int            tx_setup;
  64
  65         enum s3c24xx_i2c_state  state;
  66         unsigned long           clkrate;
  67
  68         void __iomem            *regs;
  69         struct clk              *clk;
  70         struct device           *dev;
  71         struct resource         *irq;
  72         struct resource         *ioarea;
  73         struct i2c_adapter      adap;
  74
  75 #ifdef CONFIG_CPU_FREQ
  76         struct notifier_block   freq_transition;
  77 #endif
  78 };
  79
  80 /* default platform data to use if not supplied in the platform_device
  81 */
  82
  83 static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
  84         .flags          = 0,
  85         .slave_addr     = 0x10,
  86         .bus_freq       = 100*1000,
  87         .max_freq       = 400*1000,
  88         .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
  89 };
  90
  91 /* s3c24xx_i2c_is2440()
  92  *
  93  * return true is this is an s3c2440
  94 */
  95
  96 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  97 {
  98         struct platform_device *pdev = to_platform_device(i2c->dev);
  99
 100         return !strcmp(pdev->name, "s3c2440-i2c");
 101 }
 102
 103
 104 /* s3c24xx_i2c_get_platformdata
 105  *
 106  * get the platform data associated with the given device, or return
 107  * the default if there is none
 108 */
 109
 110 static inline struct s3c2410_platform_i2c *
 111 s3c24xx_i2c_get_platformdata(struct device *dev)
 112 {
 113         if (dev->platform_data != NULL)
 114                 return (struct s3c2410_platform_i2c *)dev->platform_data;
 115
 116         return &s3c24xx_i2c_default_platform;
 117 }
 118
 119 /* s3c24xx_i2c_master_complete
 120  *
 121  * complete the message and wake up the caller, using the given return code,
 122  * or zero to mean ok.
 123 */
 124
 125 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 126 {
 127         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 128
 129         i2c->msg_ptr = 0;
 130         i2c->msg = NULL;
 131         i2c->msg_idx++;
 132         i2c->msg_num = 0;
 133         if (ret)
 134                 i2c->msg_idx = ret;
 135
 136         wake_up(&i2c->wait);
 137 }
 138
 139 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 140 {
 141         unsigned long tmp;
 142
 143         tmp = readl(i2c->regs + S3C2410_IICCON);
 144         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 145 }
 146
 147 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 148 {
 149         unsigned long tmp;
 150
 151         tmp = readl(i2c->regs + S3C2410_IICCON);
 152         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 153 }
 154
 155 /* irq enable/disable functions */
 156
 157 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 158 {
 159         unsigned long tmp;
 160
 161         tmp = readl(i2c->regs + S3C2410_IICCON);
 162         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 163 }
 164
 165 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 166 {
 167         unsigned long tmp;
 168
 169         tmp = readl(i2c->regs + S3C2410_IICCON);
 170         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 171 }
 172
 173
 174 /* s3c24xx_i2c_message_start
 175  *
 176  * put the start of a message onto the bus
 177 */
 178
 179 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 180                                       struct i2c_msg *msg)
 181 {
 182         unsigned int addr = (msg->addr & 0x7f) << 1;
 183         unsigned long stat;
 184         unsigned long iiccon;
 185
 186         stat = 0;
 187         stat |=  S3C2410_IICSTAT_TXRXEN;
 188
 189         if (msg->flags & I2C_M_RD) {
 190                 stat |= S3C2410_IICSTAT_MASTER_RX;
 191                 addr |= 1;
 192         } else
 193                 stat |= S3C2410_IICSTAT_MASTER_TX;
 194
 195         if (msg->flags & I2C_M_REV_DIR_ADDR)
 196                 addr ^= 1;
 197
 198         /* todo - check for wether ack wanted or not */
 199         s3c24xx_i2c_enable_ack(i2c);
 200
 201         iiccon = readl(i2c->regs + S3C2410_IICCON);
 202         writel(stat, i2c->regs + S3C2410_IICSTAT);
 203
 204         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 205         writeb(addr, i2c->regs + S3C2410_IICDS);
 206
 207         /* delay here to ensure the data byte has gotten onto the bus
 208          * before the transaction is started */
 209
 210         ndelay(i2c->tx_setup);
 211
 212         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 213         writel(iiccon, i2c->regs + S3C2410_IICCON);
 214
 215         stat |= S3C2410_IICSTAT_START;
 216         writel(stat, i2c->regs + S3C2410_IICSTAT);
 217 }
 218
 219 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 220 {
 221         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 222
 223         dev_dbg(i2c->dev, "STOP\n");
 224
 225         /* stop the transfer */
 226         iicstat &= ~S3C2410_IICSTAT_START;
 227         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 228
 229         i2c->state = STATE_STOP;
 230
 231         s3c24xx_i2c_master_complete(i2c, ret);
 232         s3c24xx_i2c_disable_irq(i2c);
 233 }
 234
 235 /* helper functions to determine the current state in the set of
 236  * messages we are sending */
 237
 238 /* is_lastmsg()
 239  *
 240  * returns TRUE if the current message is the last in the set
 241 */
 242
 243 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 244 {
 245         return i2c->msg_idx >= (i2c->msg_num - 1);
 246 }
 247
 248 /* is_msglast
 249  *
 250  * returns TRUE if we this is the last byte in the current message
 251 */
 252
 253 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 254 {
 255         return i2c->msg_ptr == i2c->msg->len-1;
 256 }
 257
 258 /* is_msgend
 259  *
 260  * returns TRUE if we reached the end of the current message
 261 */
 262
 263 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 264 {
 265         return i2c->msg_ptr >= i2c->msg->len;
 266 }
 267
 268 /* i2s_s3c_irq_nextbyte
 269  *
 270  * process an interrupt and work out what to do
 271  */
 272
 273 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 274 {
 275         unsigned long tmp;
 276         unsigned char byte;
 277         int ret = 0;
 278
 279         switch (i2c->state) {
 280
 281         case STATE_IDLE:
 282                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 283                 goto out;
 284                 break;
 285
 286         case STATE_STOP:
 287                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 288                 s3c24xx_i2c_disable_irq(i2c);
 289                 goto out_ack;
 290
 291         case STATE_START:
 292                 /* last thing we did was send a start condition on the
 293                  * bus, or started a new i2c message
 294                  */
 295
 296                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 297                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 298                         /* ack was not received... */
 299
 300                         dev_dbg(i2c->dev, "ack was not received\n");
 301                         s3c24xx_i2c_stop(i2c, -ENXIO);
 302                         goto out_ack;
 303                 }
 304
 305                 if (i2c->msg->flags & I2C_M_RD)
 306                         i2c->state = STATE_READ;
 307                 else
 308                         i2c->state = STATE_WRITE;
 309
 310                 /* terminate the transfer if there is nothing to do
 311                  * as this is used by the i2c probe to find devices. */
 312
 313                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 314                         s3c24xx_i2c_stop(i2c, 0);
 315                         goto out_ack;
 316                 }
 317
 318                 if (i2c->state == STATE_READ)
 319                         goto prepare_read;
 320
 321                 /* fall through to the write state, as we will need to
 322                  * send a byte as well */
 323
 324         case STATE_WRITE:
 325                 /* we are writing data to the device... check for the
 326                  * end of the message, and if so, work out what to do
 327                  */
 328
 329                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 330                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 331                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 332
 333                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 334                                 goto out_ack;
 335                         }
 336                 }
 337
 338  retry_write:
 339
 340                 if (!is_msgend(i2c)) {
 341                         byte = i2c->msg->buf[i2c->msg_ptr++];
 342                         writeb(byte, i2c->regs + S3C2410_IICDS);
 343
 344                         /* delay after writing the byte to allow the
 345                          * data setup time on the bus, as writing the
 346                          * data to the register causes the first bit
 347                          * to appear on SDA, and SCL will change as
 348                          * soon as the interrupt is acknowledged */
 349
 350                         ndelay(i2c->tx_setup);
 351
 352                 } else if (!is_lastmsg(i2c)) {
 353                         /* we need to go to the next i2c message */
 354
 355                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 356
 357                         i2c->msg_ptr = 0;
 358                         i2c->msg_idx++;
 359                         i2c->msg++;
 360
 361                         /* check to see if we need to do another message */
 362                         if (i2c->msg->flags & I2C_M_NOSTART) {
 363
 364                                 if (i2c->msg->flags & I2C_M_RD) {
 365                                         /* cannot do this, the controller
 366                                          * forces us to send a new START
 367                                          * when we change direction */
 368
 369                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 370                                 }
 371
 372                                 goto retry_write;
 373                         } else {
 374                                 /* send the new start */
 375                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 376                                 i2c->state = STATE_START;
 377                         }
 378
 379                 } else {
 380                         /* send stop */
 381
 382                         s3c24xx_i2c_stop(i2c, 0);
 383                 }
 384                 break;
 385
 386         case STATE_READ:
 387                 /* we have a byte of data in the data register, do
 388                  * something with it, and then work out wether we are
 389                  * going to do any more read/write
 390                  */
 391
 392                 byte = readb(i2c->regs + S3C2410_IICDS);
 393                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 394
 395  prepare_read:
 396                 if (is_msglast(i2c)) {
 397                         /* last byte of buffer */
 398
 399                         if (is_lastmsg(i2c))
 400                                 s3c24xx_i2c_disable_ack(i2c);
 401
 402                 } else if (is_msgend(i2c)) {
 403                         /* ok, we've read the entire buffer, see if there
 404                          * is anything else we need to do */
 405
 406                         if (is_lastmsg(i2c)) {
 407                                 /* last message, send stop and complete */
 408                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 409
 410                                 s3c24xx_i2c_stop(i2c, 0);
 411                         } else {
 412                                 /* go to the next transfer */
 413                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 414
 415                                 i2c->msg_ptr = 0;
 416                                 i2c->msg_idx++;
 417                                 i2c->msg++;
 418                         }
 419                 }
 420
 421                 break;
 422         }
 423
 424         /* acknowlegde the IRQ and get back on with the work */
 425
 426  out_ack:
 427         tmp = readl(i2c->regs + S3C2410_IICCON);
 428         tmp &= ~S3C2410_IICCON_IRQPEND;
 429         writel(tmp, i2c->regs + S3C2410_IICCON);
 430  out:
 431         return ret;
 432 }
 433
 434 /* s3c24xx_i2c_irq
 435  *
 436  * top level IRQ servicing routine
 437 */
 438
 439 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 440 {
 441         struct s3c24xx_i2c *i2c = dev_id;
 442         unsigned long status;
 443         unsigned long tmp;
 444
 445         status = readl(i2c->regs + S3C2410_IICSTAT);
 446
 447         if (status & S3C2410_IICSTAT_ARBITR) {
 448                 /* deal with arbitration loss */
 449                 dev_err(i2c->dev, "deal with arbitration loss\n");
 450         }
 451
 452         if (i2c->state == STATE_IDLE) {
 453                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 454
 455                 tmp = readl(i2c->regs + S3C2410_IICCON);
 456                 tmp &= ~S3C2410_IICCON_IRQPEND;
 457                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 458                 goto out;
 459         }
 460
 461         /* pretty much this leaves us with the fact that we've
 462          * transmitted or received whatever byte we last sent */
 463
 464         i2s_s3c_irq_nextbyte(i2c, status);
 465
 466  out:
 467         return IRQ_HANDLED;
 468 }
 469
 470
 471 /* s3c24xx_i2c_set_master
 472  *
 473  * get the i2c bus for a master transaction
 474 */
 475
 476 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 477 {
 478         unsigned long iicstat;
 479         int timeout = 400;
 480
 481         while (timeout-- > 0) {
 482                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 483
 484                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 485                         return 0;
 486
 487                 msleep(1);
 488         }
 489
 490         return -ETIMEDOUT;
 491 }
 492
 493 /* s3c24xx_i2c_doxfer
 494  *
 495  * this starts an i2c transfer
 496 */
 497
 498 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 499                               struct i2c_msg *msgs, int num)
 500 {
 501         unsigned long timeout;
 502         int ret;
 503
 504         if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN))
 505                 return -EIO;
 506
 507         ret = s3c24xx_i2c_set_master(i2c);
 508         if (ret != 0) {
 509                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 510                 ret = -EAGAIN;
 511                 goto out;
 512         }
 513
 514         spin_lock_irq(&i2c->lock);
 515
 516         i2c->msg     = msgs;
 517         i2c->msg_num = num;
 518         i2c->msg_ptr = 0;
 519         i2c->msg_idx = 0;
 520         i2c->state   = STATE_START;
 521
 522         s3c24xx_i2c_enable_irq(i2c);
 523         s3c24xx_i2c_message_start(i2c, msgs);
 524         spin_unlock_irq(&i2c->lock);
 525
 526         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 527
 528         ret = i2c->msg_idx;
 529
 530         /* having these next two as dev_err() makes life very
 531          * noisy when doing an i2cdetect */
 532
 533         if (timeout == 0)
 534                 dev_dbg(i2c->dev, "timeout\n");
 535         else if (ret != num)
 536                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 537
 538         /* ensure the stop has been through the bus */
 539
 540         msleep(1);
 541
 542  out:
 543         return ret;
 544 }
 545
 546 /* s3c24xx_i2c_xfer
 547  *
 548  * first port of call from the i2c bus code when an message needs
 549  * transferring across the i2c bus.
 550 */
 551
 552 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 553                         struct i2c_msg *msgs, int num)
 554 {
 555         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 556         int retry;
 557         int ret;
 558
 559         for (retry = 0; retry < adap->retries; retry++) {
 560
 561                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 562
 563                 if (ret != -EAGAIN)
 564                         return ret;
 565
 566                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 567
 568                 udelay(100);
 569         }
 570
 571         return -EREMOTEIO;
 572 }
 573
 574 /* declare our i2c functionality */
 575 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 576 {
 577         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 578 }
 579
 580 /* i2c bus registration info */
 581
 582 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 583         .master_xfer            = s3c24xx_i2c_xfer,
 584         .functionality          = s3c24xx_i2c_func,
 585 };
 586
 587 static struct s3c24xx_i2c s3c24xx_i2c = {
 588         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
 589         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
 590         .tx_setup       = 50,
 591         .adap           = {
 592                 .name                   = "s3c2410-i2c",
 593                 .owner                  = THIS_MODULE,
 594                 .algo                   = &s3c24xx_i2c_algorithm,
 595                 .retries                = 2,
 596                 .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 597         },
 598 };
 599
 600 /* s3c24xx_i2c_calcdivisor
 601  *
 602  * return the divisor settings for a given frequency
 603 */
 604
 605 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 606                                    unsigned int *div1, unsigned int *divs)
 607 {
 608         unsigned int calc_divs = clkin / wanted;
 609         unsigned int calc_div1;
 610
 611         if (calc_divs > (16*16))
 612                 calc_div1 = 512;
 613         else
 614                 calc_div1 = 16;
 615
 616         calc_divs += calc_div1-1;
 617         calc_divs /= calc_div1;
 618
 619         if (calc_divs == 0)
 620                 calc_divs = 1;
 621         if (calc_divs > 17)
 622                 calc_divs = 17;
 623
 624         *divs = calc_divs;
 625         *div1 = calc_div1;
 626
 627         return clkin / (calc_divs * calc_div1);
 628 }
 629
 630 /* freq_acceptable
 631  *
 632  * test wether a frequency is within the acceptable range of error
 633 */
 634
 635 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 636 {
 637         int diff = freq - wanted;
 638
 639         return diff >= -2 && diff <= 2;
 640 }
 641
 642 /* s3c24xx_i2c_clockrate
 643  *
 644  * work out a divisor for the user requested frequency setting,
 645  * either by the requested frequency, or scanning the acceptable
 646  * range of frequencies until something is found
 647 */
 648
 649 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 650 {
 651         struct s3c2410_platform_i2c *pdata;
 652         unsigned long clkin = clk_get_rate(i2c->clk);
 653         unsigned int divs, div1;
 654         u32 iiccon;
 655         int freq;
 656         int start, end;
 657
 658         i2c->clkrate = clkin;
 659
 660         pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
 661         clkin /= 1000;          /* clkin now in KHz */
 662
 663         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
 664                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
 665
 666         if (pdata->bus_freq != 0) {
 667                 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
 668                                                &div1, &divs);
 669                 if (freq_acceptable(freq, pdata->bus_freq/1000))
 670                         goto found;
 671         }
 672
 673         /* ok, we may have to search for something suitable... */
 674
 675         start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
 676         end = pdata->min_freq;
 677
 678         start /= 1000;
 679         end /= 1000;
 680
 681         /* search loop... */
 682
 683         for (; start > end; start--) {
 684                 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
 685                 if (freq_acceptable(freq, start))
 686                         goto found;
 687         }
 688
 689         /* cannot find frequency spec */
 690
 691         return -EINVAL;
 692
 693  found:
 694         *got = freq;
 695
 696         iiccon = readl(i2c->regs + S3C2410_IICCON);
 697         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 698         iiccon |= (divs-1);
 699
 700         if (div1 == 512)
 701                 iiccon |= S3C2410_IICCON_TXDIV_512;
 702
 703         writel(iiccon, i2c->regs + S3C2410_IICCON);
 704
 705         return 0;
 706 }
 707
 708 #ifdef CONFIG_CPU_FREQ
 709
 710 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 711
 712 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 713                                           unsigned long val, void *data)
 714 {
 715         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 716         unsigned long flags;
 717         unsigned int got;
 718         int delta_f;
 719         int ret;
 720
 721         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 722
 723         /* if we're post-change and the input clock has slowed down
 724          * or at pre-change and the clock is about to speed up, then
 725          * adjust our clock rate. <0 is slow, >0 speedup.
 726          */
 727
 728         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 729             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 730                 spin_lock_irqsave(&i2c->lock, flags);
 731                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 732                 spin_unlock_irqrestore(&i2c->lock, flags);
 733
 734                 if (ret < 0)
 735                         dev_err(i2c->dev, "cannot find frequency\n");
 736                 else
 737                         dev_info(i2c->dev, "setting freq %d\n", got);
 738         }
 739
 740         return 0;
 741 }
 742
 743 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 744 {
 745         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 746
 747         return cpufreq_register_notifier(&i2c->freq_transition,
 748                                          CPUFREQ_TRANSITION_NOTIFIER);
 749 }
 750
 751 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 752 {
 753         cpufreq_unregister_notifier(&i2c->freq_transition,
 754                                     CPUFREQ_TRANSITION_NOTIFIER);
 755 }
 756
 757 #else
 758 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 759 {
 760         return 0;
 761 }
 762
 763 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 764 {
 765 }
 766 #endif
 767
 768 /* s3c24xx_i2c_init
 769  *
 770  * initialise the controller, set the IO lines and frequency
 771 */
 772
 773 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 774 {
 775         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 776         struct s3c2410_platform_i2c *pdata;
 777         unsigned int freq;
 778
 779         /* get the plafrom data */
 780
 781         pdata = s3c24xx_i2c_get_platformdata(i2c->dev);
 782
 783         /* inititalise the gpio */
 784
 785         if (pdata->cfg_gpio)
 786                 pdata->cfg_gpio(to_platform_device(i2c->dev));
 787
 788         /* write slave address */
 789
 790         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 791
 792         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 793
 794         writel(iicon, i2c->regs + S3C2410_IICCON);
 795
 796         /* we need to work out the divisors for the clock... */
 797
 798         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 799                 writel(0, i2c->regs + S3C2410_IICCON);
 800                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 801                 return -EINVAL;
 802         }
 803
 804         /* todo - check that the i2c lines aren't being dragged anywhere */
 805
 806         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 807         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 808
 809         /* check for s3c2440 i2c controller  */
 810
 811         if (s3c24xx_i2c_is2440(i2c)) {
 812                 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
 813
 814                 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
 815         }
 816
 817         return 0;
 818 }
 819
 820 /* s3c24xx_i2c_probe
 821  *
 822  * called by the bus driver when a suitable device is found
 823 */
 824
 825 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 826 {
 827         struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
 828         struct s3c2410_platform_i2c *pdata;
 829         struct resource *res;
 830         int ret;
 831
 832         pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
 833
 834         /* find the clock and enable it */
 835
 836         i2c->dev = &pdev->dev;
 837         i2c->clk = clk_get(&pdev->dev, "i2c");
 838         if (IS_ERR(i2c->clk)) {
 839                 dev_err(&pdev->dev, "cannot get clock\n");
 840                 ret = -ENOENT;
 841                 goto err_noclk;
 842         }
 843
 844         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 845
 846         clk_enable(i2c->clk);
 847
 848         /* map the registers */
 849
 850         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 851         if (res == NULL) {
 852                 dev_err(&pdev->dev, "cannot find IO resource\n");
 853                 ret = -ENOENT;
 854                 goto err_clk;
 855         }
 856
 857         i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
 858                                          pdev->name);
 859
 860         if (i2c->ioarea == NULL) {
 861                 dev_err(&pdev->dev, "cannot request IO\n");
 862                 ret = -ENXIO;
 863                 goto err_clk;
 864         }
 865
 866         i2c->regs = ioremap(res->start, (res->end-res->start)+1);
 867
 868         if (i2c->regs == NULL) {
 869                 dev_err(&pdev->dev, "cannot map IO\n");
 870                 ret = -ENXIO;
 871                 goto err_ioarea;
 872         }
 873
 874         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 875                 i2c->regs, i2c->ioarea, res);
 876
 877         /* setup info block for the i2c core */
 878
 879         i2c->adap.algo_data = i2c;
 880         i2c->adap.dev.parent = &pdev->dev;
 881
 882         /* initialise the i2c controller */
 883
 884         ret = s3c24xx_i2c_init(i2c);
 885         if (ret != 0)
 886                 goto err_iomap;
 887
 888         /* find the IRQ for this unit (note, this relies on the init call to
 889          * ensure no current IRQs pending
 890          */
 891
 892         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 893         if (res == NULL) {
 894                 dev_err(&pdev->dev, "cannot find IRQ\n");
 895                 ret = -ENOENT;
 896                 goto err_iomap;
 897         }
 898
 899         ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
 900                           pdev->name, i2c);
 901
 902         if (ret != 0) {
 903                 dev_err(&pdev->dev, "cannot claim IRQ\n");
 904                 goto err_iomap;
 905         }
 906
 907         i2c->irq = res;
 908
 909         dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
 910                 (unsigned long)res->start);
 911
 912         ret = s3c24xx_i2c_register_cpufreq(i2c);
 913         if (ret < 0) {
 914                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
 915                 goto err_irq;
 916         }
 917
 918         /* Note, previous versions of the driver used i2c_add_adapter()
 919          * to add the bus at any number. We now pass the bus number via
 920          * the platform data, so if unset it will now default to always
 921          * being bus 0.
 922          */
 923
 924         i2c->adap.nr = pdata->bus_num;
 925
 926         ret = i2c_add_numbered_adapter(&i2c->adap);
 927         if (ret < 0) {
 928                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 929                 goto err_cpufreq;
 930         }
 931
 932         platform_set_drvdata(pdev, i2c);
 933
 934         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
 935         return 0;
 936
 937  err_cpufreq:
 938         s3c24xx_i2c_deregister_cpufreq(i2c);
 939
 940  err_irq:
 941         free_irq(i2c->irq->start, i2c);
 942
 943  err_iomap:
 944         iounmap(i2c->regs);
 945
 946  err_ioarea:
 947         release_resource(i2c->ioarea);
 948         kfree(i2c->ioarea);
 949
 950  err_clk:
 951         clk_disable(i2c->clk);
 952         clk_put(i2c->clk);
 953
 954  err_noclk:
 955         return ret;
 956 }
 957
 958 /* s3c24xx_i2c_remove
 959  *
 960  * called when device is removed from the bus
 961 */
 962
 963 static int s3c24xx_i2c_remove(struct platform_device *pdev)
 964 {
 965         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
 966
 967         s3c24xx_i2c_deregister_cpufreq(i2c);
 968
 969         i2c_del_adapter(&i2c->adap);
 970         free_irq(i2c->irq->start, i2c);
 971
 972         clk_disable(i2c->clk);
 973         clk_put(i2c->clk);
 974
 975         iounmap(i2c->regs);
 976
 977         release_resource(i2c->ioarea);
 978         kfree(i2c->ioarea);
 979
 980         return 0;
 981 }
 982
 983 #ifdef CONFIG_PM
 984 static int s3c24xx_i2c_resume(struct platform_device *dev)
 985 {
 986         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
 987
 988         if (i2c != NULL)
 989                 s3c24xx_i2c_init(i2c);
 990
 991         return 0;
 992 }
 993
 994 #else
 995 #define s3c24xx_i2c_resume NULL
 996 #endif
 997
 998 /* device driver for platform bus bits */
 999
1000 static struct platform_driver s3c2410_i2c_driver = {
1001         .probe          = s3c24xx_i2c_probe,
1002         .remove         = s3c24xx_i2c_remove,
1003         .resume         = s3c24xx_i2c_resume,
1004         .driver         = {
1005                 .owner  = THIS_MODULE,
1006                 .name   = "s3c2410-i2c",
1007         },
1008 };
1009
1010 static struct platform_driver s3c2440_i2c_driver = {
1011         .probe          = s3c24xx_i2c_probe,
1012         .remove         = s3c24xx_i2c_remove,
1013         .resume         = s3c24xx_i2c_resume,
1014         .driver         = {
1015                 .owner  = THIS_MODULE,
1016                 .name   = "s3c2440-i2c",
1017         },
1018 };
1019
1020 static int __init i2c_adap_s3c_init(void)
1021 {
1022         int ret;
1023
1024         ret = platform_driver_register(&s3c2410_i2c_driver);
1025         if (ret == 0) {
1026                 ret = platform_driver_register(&s3c2440_i2c_driver);
1027                 if (ret)
1028                         platform_driver_unregister(&s3c2410_i2c_driver);
1029         }
1030
1031         return ret;
1032 }
1033
1034 static void __exit i2c_adap_s3c_exit(void)
1035 {
1036         platform_driver_unregister(&s3c2410_i2c_driver);
1037         platform_driver_unregister(&s3c2440_i2c_driver);
1038 }
1039
1040 module_init(i2c_adap_s3c_init);
1041 module_exit(i2c_adap_s3c_exit);
1042
1043 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1044 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1045 MODULE_LICENSE("GPL");
1046 MODULE_ALIAS("platform:s3c2410-i2c");
1047 MODULE_ALIAS("platform:s3c2440-i2c");