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   1 /* mach/dma.h - arch-specific DMA defines
   2  *
   3  * Copyright 2004-2008 Analog Devices Inc.
   4  *
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #ifndef _MACH_DMA_H_
   9 #define _MACH_DMA_H_
  10
  11 #define MAX_DMA_CHANNELS 16
  12
  13 #define CH_PPI                  0       /* PPI receive/transmit */
  14 #define CH_EMAC_RX              1       /* Ethernet MAC receive */
  15 #define CH_EMAC_TX              2       /* Ethernet MAC transmit */
  16 #define CH_SPORT0_RX            3       /* SPORT0 receive */
  17 #define CH_SPORT0_TX            4       /* SPORT0 transmit */
  18 #define CH_RSI                  4       /* RSI */
  19 #define CH_SPORT1_RX            5       /* SPORT1 receive */
  20 #define CH_SPI1                 5       /* SPI1 transmit/receive */
  21 #define CH_SPORT1_TX            6       /* SPORT1 transmit */
  22 #define CH_SPI0                 7       /* SPI0 transmit/receive */
  23 #define CH_UART0_RX             8       /* UART0 receive */
  24 #define CH_UART0_TX             9       /* UART0 transmit */
  25 #define CH_UART1_RX             10      /* UART1 receive */
  26 #define CH_UART1_TX             11      /* UART1 transmit */
  27
  28 #define CH_MEM_STREAM0_SRC      12      /* RX */
  29 #define CH_MEM_STREAM0_DEST     13      /* TX */
  30 #define CH_MEM_STREAM1_SRC      14      /* RX */
  31 #define CH_MEM_STREAM1_DEST     15      /* TX */
  32
  33 #endif