git.oblomov.eu Git - linux-2.6/blob - drivers/media/common/tuners/mxl5005s.c

   1 /*
   2  * For the Realtek RTL chip RTL2831U
   3  * Realtek Release Date: 2008-03-14, ver 080314
   4  * Realtek version RTL2831 Linux driver version 080314
   5  * ver 080314
   6  *
   7  * for linux kernel version 2.6.21.4 - 2.6.22-14
   8  * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
   9  * support two IR types -- RC5 and NEC
  10  *
  11  * Known boards with Realtek RTL chip RTL2821U
  12  *    Freecom USB stick 14aa:0160 (version 4)
  13  *    Conceptronic CTVDIGRCU
  14  *
  15  * Copyright (c) 2008 Realtek
  16  * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
  17  * This code is placed under the terms of the GNU General Public License
  18  *
  19  * Released by Realtek under GPLv2.
  20  * Thanks to Realtek for a lot of support we received !
  21  *
  22  *  Revision: 080314 - original version
  23  */
  24
  25 #include "mxl5005s.h"
  26
  27 static int debug = 2;
  28
  29 #define dprintk(level, arg...) do {    \
  30         if (level <= debug)            \
  31                 printk(arg);    \
  32         } while (0)
  33
  34 #define TUNER_REGS_NUM          104
  35 #define INITCTRL_NUM            40
  36
  37 #ifdef _MXL_PRODUCTION
  38 #define CHCTRL_NUM              39
  39 #else
  40 #define CHCTRL_NUM              36
  41 #endif
  42
  43 #define MXLCTRL_NUM             189
  44 #define MASTER_CONTROL_ADDR     9
  45
  46 /* Enumeration of Master Control Register State */
  47 typedef enum
  48 {
  49         MC_LOAD_START = 1,
  50         MC_POWER_DOWN,
  51         MC_SYNTH_RESET,
  52         MC_SEQ_OFF
  53 } Master_Control_State;
  54
  55 /* Enumeration of MXL5005 Tuner Modulation Type */
  56 typedef enum
  57 {
  58         MXL_DEFAULT_MODULATION = 0,
  59         MXL_DVBT,
  60         MXL_ATSC,
  61         MXL_QAM,
  62         MXL_ANALOG_CABLE,
  63         MXL_ANALOG_OTA
  64 } Tuner_Modu_Type;
  65
  66 /* MXL5005 Tuner Register Struct */
  67 typedef struct _TunerReg_struct
  68 {
  69         u16 Reg_Num;    /* Tuner Register Address */
  70         u16 Reg_Val;    /* Current sofware programmed value waiting to be writen */
  71 } TunerReg_struct;
  72
  73 typedef enum
  74 {
  75         /* Initialization Control Names */
  76         DN_IQTN_AMP_CUT = 1,       /* 1 */
  77         BB_MODE,                   /* 2 */
  78         BB_BUF,                    /* 3 */
  79         BB_BUF_OA,                 /* 4 */
  80         BB_ALPF_BANDSELECT,        /* 5 */
  81         BB_IQSWAP,                 /* 6 */
  82         BB_DLPF_BANDSEL,           /* 7 */
  83         RFSYN_CHP_GAIN,            /* 8 */
  84         RFSYN_EN_CHP_HIGAIN,       /* 9 */
  85         AGC_IF,                    /* 10 */
  86         AGC_RF,                    /* 11 */
  87         IF_DIVVAL,                 /* 12 */
  88         IF_VCO_BIAS,               /* 13 */
  89         CHCAL_INT_MOD_IF,          /* 14 */
  90         CHCAL_FRAC_MOD_IF,         /* 15 */
  91         DRV_RES_SEL,               /* 16 */
  92         I_DRIVER,                  /* 17 */
  93         EN_AAF,                    /* 18 */
  94         EN_3P,                     /* 19 */
  95         EN_AUX_3P,                 /* 20 */
  96         SEL_AAF_BAND,              /* 21 */
  97         SEQ_ENCLK16_CLK_OUT,       /* 22 */
  98         SEQ_SEL4_16B,              /* 23 */
  99         XTAL_CAPSELECT,            /* 24 */
 100         IF_SEL_DBL,                /* 25 */
 101         RFSYN_R_DIV,               /* 26 */
 102         SEQ_EXTSYNTHCALIF,         /* 27 */
 103         SEQ_EXTDCCAL,              /* 28 */
 104         AGC_EN_RSSI,               /* 29 */
 105         RFA_ENCLKRFAGC,            /* 30 */
 106         RFA_RSSI_REFH,             /* 31 */
 107         RFA_RSSI_REF,              /* 32 */
 108         RFA_RSSI_REFL,             /* 33 */
 109         RFA_FLR,                   /* 34 */
 110         RFA_CEIL,                  /* 35 */
 111         SEQ_EXTIQFSMPULSE,         /* 36 */
 112         OVERRIDE_1,                /* 37 */
 113         BB_INITSTATE_DLPF_TUNE,    /* 38 */
 114         TG_R_DIV,                  /* 39 */
 115         EN_CHP_LIN_B,              /* 40 */
 116
 117         /* Channel Change Control Names */
 118         DN_POLY = 51,              /* 51 */
 119         DN_RFGAIN,                 /* 52 */
 120         DN_CAP_RFLPF,              /* 53 */
 121         DN_EN_VHFUHFBAR,           /* 54 */
 122         DN_GAIN_ADJUST,            /* 55 */
 123         DN_IQTNBUF_AMP,            /* 56 */
 124         DN_IQTNGNBFBIAS_BST,       /* 57 */
 125         RFSYN_EN_OUTMUX,           /* 58 */
 126         RFSYN_SEL_VCO_OUT,         /* 59 */
 127         RFSYN_SEL_VCO_HI,          /* 60 */
 128         RFSYN_SEL_DIVM,            /* 61 */
 129         RFSYN_RF_DIV_BIAS,         /* 62 */
 130         DN_SEL_FREQ,               /* 63 */
 131         RFSYN_VCO_BIAS,            /* 64 */
 132         CHCAL_INT_MOD_RF,          /* 65 */
 133         CHCAL_FRAC_MOD_RF,         /* 66 */
 134         RFSYN_LPF_R,               /* 67 */
 135         CHCAL_EN_INT_RF,           /* 68 */
 136         TG_LO_DIVVAL,              /* 69 */
 137         TG_LO_SELVAL,              /* 70 */
 138         TG_DIV_VAL,                /* 71 */
 139         TG_VCO_BIAS,               /* 72 */
 140         SEQ_EXTPOWERUP,            /* 73 */
 141         OVERRIDE_2,                /* 74 */
 142         OVERRIDE_3,                /* 75 */
 143         OVERRIDE_4,                /* 76 */
 144         SEQ_FSM_PULSE,             /* 77 */
 145         GPIO_4B,                   /* 78 */
 146         GPIO_3B,                   /* 79 */
 147         GPIO_4,                    /* 80 */
 148         GPIO_3,                    /* 81 */
 149         GPIO_1B,                   /* 82 */
 150         DAC_A_ENABLE,              /* 83 */
 151         DAC_B_ENABLE,              /* 84 */
 152         DAC_DIN_A,                 /* 85 */
 153         DAC_DIN_B,                 /* 86 */
 154 #ifdef _MXL_PRODUCTION
 155         RFSYN_EN_DIV,              /* 87 */
 156         RFSYN_DIVM,                /* 88 */
 157         DN_BYPASS_AGC_I2C          /* 89 */
 158 #endif
 159 } MXL5005_ControlName;
 160
 161 /*
 162  * The following context is source code provided by MaxLinear.
 163  * MaxLinear source code - Common_MXL.h (?)
 164  */
 165
 166 /* Constants */
 167 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX      104
 168 #define MXL5005S_LATCH_BYTE                     0xfe
 169
 170 /* Register address, MSB, and LSB */
 171 #define MXL5005S_BB_IQSWAP_ADDR                 59
 172 #define MXL5005S_BB_IQSWAP_MSB                  0
 173 #define MXL5005S_BB_IQSWAP_LSB                  0
 174
 175 #define MXL5005S_BB_DLPF_BANDSEL_ADDR           53
 176 #define MXL5005S_BB_DLPF_BANDSEL_MSB            4
 177 #define MXL5005S_BB_DLPF_BANDSEL_LSB            3
 178
 179 /* Standard modes */
 180 enum
 181 {
 182         MXL5005S_STANDARD_DVBT,
 183         MXL5005S_STANDARD_ATSC,
 184 };
 185 #define MXL5005S_STANDARD_MODE_NUM              2
 186
 187 /* Bandwidth modes */
 188 enum
 189 {
 190         MXL5005S_BANDWIDTH_6MHZ = 6000000,
 191         MXL5005S_BANDWIDTH_7MHZ = 7000000,
 192         MXL5005S_BANDWIDTH_8MHZ = 8000000,
 193 };
 194 #define MXL5005S_BANDWIDTH_MODE_NUM             3
 195
 196 /* MXL5005 Tuner Control Struct */
 197 typedef struct _TunerControl_struct {
 198         u16 Ctrl_Num;   /* Control Number */
 199         u16 size;       /* Number of bits to represent Value */
 200         u16 addr[25];   /* Array of Tuner Register Address for each bit position */
 201         u16 bit[25];    /* Array of bit position in Register Address for each bit position */
 202         u16 val[25];    /* Binary representation of Value */
 203 } TunerControl_struct;
 204
 205 /* MXL5005 Tuner Struct */
 206 struct mxl5005s_state
 207 {
 208         u8      Mode;           /* 0: Analog Mode ; 1: Digital Mode */
 209         u8      IF_Mode;        /* for Analog Mode, 0: zero IF; 1: low IF */
 210         u32     Chan_Bandwidth; /* filter  channel bandwidth (6, 7, 8) */
 211         u32     IF_OUT;         /* Desired IF Out Frequency */
 212         u16     IF_OUT_LOAD;    /* IF Out Load Resistor (200/300 Ohms) */
 213         u32     RF_IN;          /* RF Input Frequency */
 214         u32     Fxtal;          /* XTAL Frequency */
 215         u8      AGC_Mode;       /* AGC Mode 0: Dual AGC; 1: Single AGC */
 216         u16     TOP;            /* Value: take over point */
 217         u8      CLOCK_OUT;      /* 0: turn off clock out; 1: turn on clock out */
 218         u8      DIV_OUT;        /* 4MHz or 16MHz */
 219         u8      CAPSELECT;      /* 0: disable On-Chip pulling cap; 1: enable */
 220         u8      EN_RSSI;        /* 0: disable RSSI; 1: enable RSSI */
 221         u8      Mod_Type;       /* Modulation Type; */
 222                                 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
 223         u8      TF_Type;        /* Tracking Filter Type */
 224                                 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
 225
 226         /* Calculated Settings */
 227         u32     RF_LO;          /* Synth RF LO Frequency */
 228         u32     IF_LO;          /* Synth IF LO Frequency */
 229         u32     TG_LO;          /* Synth TG_LO Frequency */
 230
 231         /* Pointers to ControlName Arrays */
 232         u16     Init_Ctrl_Num;                  /* Number of INIT Control Names */
 233         TunerControl_struct
 234                 Init_Ctrl[INITCTRL_NUM];        /* INIT Control Names Array Pointer */
 235
 236         u16     CH_Ctrl_Num;                    /* Number of CH Control Names */
 237         TunerControl_struct
 238                 CH_Ctrl[CHCTRL_NUM];            /* CH Control Name Array Pointer */
 239
 240         u16     MXL_Ctrl_Num;                   /* Number of MXL Control Names */
 241         TunerControl_struct
 242                 MXL_Ctrl[MXLCTRL_NUM];          /* MXL Control Name Array Pointer */
 243
 244         /* Pointer to Tuner Register Array */
 245         u16     TunerRegs_Num;                  /* Number of Tuner Registers */
 246         TunerReg_struct
 247                 TunerRegs[TUNER_REGS_NUM];      /* Tuner Register Array Pointer */
 248
 249         /* Linux driver framework specific */
 250         struct mxl5005s_config *config;
 251         struct dvb_frontend *frontend;
 252         struct i2c_adapter *i2c;
 253 };
 254
 255 // funcs
 256 u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
 257 u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
 258 u16 MXL_GetMasterControl(u8 *MasterReg, int state);
 259 void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
 260 u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
 261 u32 MXL_Ceiling(u32 value, u32 resolution);
 262 u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
 263 u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
 264 u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup);
 265 u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
 266 u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count);
 267 u32 MXL_GetXtalInt(u32 Xtal_Freq);
 268 u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
 269 void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
 270 void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
 271 u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
 272 int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen);
 273 u16 MXL_IFSynthInit(struct dvb_frontend *fe);
 274 int mxl5005s_AssignTunerMode(struct dvb_frontend *fe);
 275
 276 int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
 277 {
 278         struct mxl5005s_state *state = fe->tuner_priv;
 279         unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 280         unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 281         int TableLen;
 282
 283         u32 IfDivval;
 284         unsigned char MasterControlByte;
 285
 286         dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
 287
 288         // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
 289
 290         // Tuner RF frequency setting stage 0
 291         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
 292         AddrTable[0] = MASTER_CONTROL_ADDR;
 293         ByteTable[0] |= state->config->AgcMasterByte;
 294
 295         mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
 296
 297         // Tuner RF frequency setting stage 1
 298         MXL_TuneRF(fe, RfFreqHz);
 299
 300         MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
 301
 302         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
 303         MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
 304         MXL_ControlWrite(fe, IF_DIVVAL, 8);
 305         MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ;
 306
 307         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
 308         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 309         ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte;
 310         TableLen += 1;
 311
 312         mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
 313
 314         // Wait 30 ms.
 315         msleep(150);
 316
 317         // Tuner RF frequency setting stage 2
 318         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
 319         MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ;
 320         MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ;
 321
 322         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
 323         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 324         ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ;
 325         TableLen += 1;
 326
 327         mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
 328
 329         msleep(100);
 330
 331         return 0;
 332 }
 333
 334 static int mxl5005s_reset(struct dvb_frontend *fe)
 335 {
 336         struct mxl5005s_state *state = fe->tuner_priv;
 337         int ret = 0;
 338
 339         u8 buf[2] = { 0xff, 0x00 };
 340         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
 341                                .buf = buf, .len = 2 };
 342
 343         dprintk(2, "%s()\n", __func__);
 344
 345         if (fe->ops.i2c_gate_ctrl)
 346                 fe->ops.i2c_gate_ctrl(fe, 1);
 347
 348         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
 349                 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
 350                 ret = -EREMOTEIO;
 351         }
 352
 353         if (fe->ops.i2c_gate_ctrl)
 354                 fe->ops.i2c_gate_ctrl(fe, 0);
 355
 356         return ret;
 357 }
 358
 359 /* Write a single byte to a single reg */
 360 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
 361 {
 362         struct mxl5005s_state *state = fe->tuner_priv;
 363         u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
 364         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
 365                                .buf = buf, .len = 3 };
 366
 367         if(latch == 0)
 368                 msg.len = 2;
 369
 370         dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr);
 371
 372         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
 373                 printk(KERN_WARNING "mxl5005s I2C write failed\n");
 374                 return -EREMOTEIO;
 375         }
 376         return 0;
 377 }
 378
 379 int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen)
 380 {
 381         int     i, ret = 0;
 382
 383         if (fe->ops.i2c_gate_ctrl)
 384                 fe->ops.i2c_gate_ctrl(fe, 1);
 385
 386         for( i = 0 ; i < TableLen - 1 ; i++)
 387         {
 388                 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0);
 389                 if (ret < 0)
 390                         break;
 391         }
 392
 393         ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1);
 394
 395         if (fe->ops.i2c_gate_ctrl)
 396                 fe->ops.i2c_gate_ctrl(fe, 0);
 397
 398         return ret;
 399 }
 400
 401 int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
 402         unsigned char RegAddr,
 403         unsigned char Msb,
 404         unsigned char Lsb,
 405         const unsigned char WritingValue
 406         )
 407 {
 408         int i;
 409
 410         unsigned char Mask;
 411         unsigned char Shift;
 412         unsigned char RegByte;
 413
 414         /* Generate mask and shift according to MSB and LSB. */
 415         Mask = 0;
 416         for(i = Lsb; i < (unsigned char)(Msb + 1); i++)
 417                 Mask |= 0x1 << i;
 418
 419         Shift = Lsb;
 420
 421         /* Get tuner register byte according to register adddress. */
 422         MXL_RegRead(fe, RegAddr, &RegByte);
 423
 424         /* Reserve register byte unmask bit with mask and inlay writing value into it. */
 425         RegByte &= ~Mask;
 426         RegByte |= (WritingValue << Shift) & Mask;
 427
 428         /* Update tuner register byte table. */
 429         MXL_RegWrite(fe, RegAddr, RegByte);
 430
 431         /* Write tuner register byte with writing byte. */
 432         return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1);
 433 }
 434
 435
 436 // The following context is source code provided by MaxLinear.
 437 // MaxLinear source code - MXL5005_Initialize.cpp
 438 // DONE
 439 u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
 440 {
 441         struct mxl5005s_state *state = fe->tuner_priv;
 442         state->TunerRegs_Num = TUNER_REGS_NUM ;
 443 //      state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
 444
 445         state->TunerRegs[0].Reg_Num = 9 ;
 446         state->TunerRegs[0].Reg_Val = 0x40 ;
 447
 448         state->TunerRegs[1].Reg_Num = 11 ;
 449         state->TunerRegs[1].Reg_Val = 0x19 ;
 450
 451         state->TunerRegs[2].Reg_Num = 12 ;
 452         state->TunerRegs[2].Reg_Val = 0x60 ;
 453
 454         state->TunerRegs[3].Reg_Num = 13 ;
 455         state->TunerRegs[3].Reg_Val = 0x00 ;
 456
 457         state->TunerRegs[4].Reg_Num = 14 ;
 458         state->TunerRegs[4].Reg_Val = 0x00 ;
 459
 460         state->TunerRegs[5].Reg_Num = 15 ;
 461         state->TunerRegs[5].Reg_Val = 0xC0 ;
 462
 463         state->TunerRegs[6].Reg_Num = 16 ;
 464         state->TunerRegs[6].Reg_Val = 0x00 ;
 465
 466         state->TunerRegs[7].Reg_Num = 17 ;
 467         state->TunerRegs[7].Reg_Val = 0x00 ;
 468
 469         state->TunerRegs[8].Reg_Num = 18 ;
 470         state->TunerRegs[8].Reg_Val = 0x00 ;
 471
 472         state->TunerRegs[9].Reg_Num = 19 ;
 473         state->TunerRegs[9].Reg_Val = 0x34 ;
 474
 475         state->TunerRegs[10].Reg_Num = 21 ;
 476         state->TunerRegs[10].Reg_Val = 0x00 ;
 477
 478         state->TunerRegs[11].Reg_Num = 22 ;
 479         state->TunerRegs[11].Reg_Val = 0x6B ;
 480
 481         state->TunerRegs[12].Reg_Num = 23 ;
 482         state->TunerRegs[12].Reg_Val = 0x35 ;
 483
 484         state->TunerRegs[13].Reg_Num = 24 ;
 485         state->TunerRegs[13].Reg_Val = 0x70 ;
 486
 487         state->TunerRegs[14].Reg_Num = 25 ;
 488         state->TunerRegs[14].Reg_Val = 0x3E ;
 489
 490         state->TunerRegs[15].Reg_Num = 26 ;
 491         state->TunerRegs[15].Reg_Val = 0x82 ;
 492
 493         state->TunerRegs[16].Reg_Num = 31 ;
 494         state->TunerRegs[16].Reg_Val = 0x00 ;
 495
 496         state->TunerRegs[17].Reg_Num = 32 ;
 497         state->TunerRegs[17].Reg_Val = 0x40 ;
 498
 499         state->TunerRegs[18].Reg_Num = 33 ;
 500         state->TunerRegs[18].Reg_Val = 0x53 ;
 501
 502         state->TunerRegs[19].Reg_Num = 34 ;
 503         state->TunerRegs[19].Reg_Val = 0x81 ;
 504
 505         state->TunerRegs[20].Reg_Num = 35 ;
 506         state->TunerRegs[20].Reg_Val = 0xC9 ;
 507
 508         state->TunerRegs[21].Reg_Num = 36 ;
 509         state->TunerRegs[21].Reg_Val = 0x01 ;
 510
 511         state->TunerRegs[22].Reg_Num = 37 ;
 512         state->TunerRegs[22].Reg_Val = 0x00 ;
 513
 514         state->TunerRegs[23].Reg_Num = 41 ;
 515         state->TunerRegs[23].Reg_Val = 0x00 ;
 516
 517         state->TunerRegs[24].Reg_Num = 42 ;
 518         state->TunerRegs[24].Reg_Val = 0xF8 ;
 519
 520         state->TunerRegs[25].Reg_Num = 43 ;
 521         state->TunerRegs[25].Reg_Val = 0x43 ;
 522
 523         state->TunerRegs[26].Reg_Num = 44 ;
 524         state->TunerRegs[26].Reg_Val = 0x20 ;
 525
 526         state->TunerRegs[27].Reg_Num = 45 ;
 527         state->TunerRegs[27].Reg_Val = 0x80 ;
 528
 529         state->TunerRegs[28].Reg_Num = 46 ;
 530         state->TunerRegs[28].Reg_Val = 0x88 ;
 531
 532         state->TunerRegs[29].Reg_Num = 47 ;
 533         state->TunerRegs[29].Reg_Val = 0x86 ;
 534
 535         state->TunerRegs[30].Reg_Num = 48 ;
 536         state->TunerRegs[30].Reg_Val = 0x00 ;
 537
 538         state->TunerRegs[31].Reg_Num = 49 ;
 539         state->TunerRegs[31].Reg_Val = 0x00 ;
 540
 541         state->TunerRegs[32].Reg_Num = 53 ;
 542         state->TunerRegs[32].Reg_Val = 0x94 ;
 543
 544         state->TunerRegs[33].Reg_Num = 54 ;
 545         state->TunerRegs[33].Reg_Val = 0xFA ;
 546
 547         state->TunerRegs[34].Reg_Num = 55 ;
 548         state->TunerRegs[34].Reg_Val = 0x92 ;
 549
 550         state->TunerRegs[35].Reg_Num = 56 ;
 551         state->TunerRegs[35].Reg_Val = 0x80 ;
 552
 553         state->TunerRegs[36].Reg_Num = 57 ;
 554         state->TunerRegs[36].Reg_Val = 0x41 ;
 555
 556         state->TunerRegs[37].Reg_Num = 58 ;
 557         state->TunerRegs[37].Reg_Val = 0xDB ;
 558
 559         state->TunerRegs[38].Reg_Num = 59 ;
 560         state->TunerRegs[38].Reg_Val = 0x00 ;
 561
 562         state->TunerRegs[39].Reg_Num = 60 ;
 563         state->TunerRegs[39].Reg_Val = 0x00 ;
 564
 565         state->TunerRegs[40].Reg_Num = 61 ;
 566         state->TunerRegs[40].Reg_Val = 0x00 ;
 567
 568         state->TunerRegs[41].Reg_Num = 62 ;
 569         state->TunerRegs[41].Reg_Val = 0x00 ;
 570
 571         state->TunerRegs[42].Reg_Num = 65 ;
 572         state->TunerRegs[42].Reg_Val = 0xF8 ;
 573
 574         state->TunerRegs[43].Reg_Num = 66 ;
 575         state->TunerRegs[43].Reg_Val = 0xE4 ;
 576
 577         state->TunerRegs[44].Reg_Num = 67 ;
 578         state->TunerRegs[44].Reg_Val = 0x90 ;
 579
 580         state->TunerRegs[45].Reg_Num = 68 ;
 581         state->TunerRegs[45].Reg_Val = 0xC0 ;
 582
 583         state->TunerRegs[46].Reg_Num = 69 ;
 584         state->TunerRegs[46].Reg_Val = 0x01 ;
 585
 586         state->TunerRegs[47].Reg_Num = 70 ;
 587         state->TunerRegs[47].Reg_Val = 0x50 ;
 588
 589         state->TunerRegs[48].Reg_Num = 71 ;
 590         state->TunerRegs[48].Reg_Val = 0x06 ;
 591
 592         state->TunerRegs[49].Reg_Num = 72 ;
 593         state->TunerRegs[49].Reg_Val = 0x00 ;
 594
 595         state->TunerRegs[50].Reg_Num = 73 ;
 596         state->TunerRegs[50].Reg_Val = 0x20 ;
 597
 598         state->TunerRegs[51].Reg_Num = 76 ;
 599         state->TunerRegs[51].Reg_Val = 0xBB ;
 600
 601         state->TunerRegs[52].Reg_Num = 77 ;
 602         state->TunerRegs[52].Reg_Val = 0x13 ;
 603
 604         state->TunerRegs[53].Reg_Num = 81 ;
 605         state->TunerRegs[53].Reg_Val = 0x04 ;
 606
 607         state->TunerRegs[54].Reg_Num = 82 ;
 608         state->TunerRegs[54].Reg_Val = 0x75 ;
 609
 610         state->TunerRegs[55].Reg_Num = 83 ;
 611         state->TunerRegs[55].Reg_Val = 0x00 ;
 612
 613         state->TunerRegs[56].Reg_Num = 84 ;
 614         state->TunerRegs[56].Reg_Val = 0x00 ;
 615
 616         state->TunerRegs[57].Reg_Num = 85 ;
 617         state->TunerRegs[57].Reg_Val = 0x00 ;
 618
 619         state->TunerRegs[58].Reg_Num = 91 ;
 620         state->TunerRegs[58].Reg_Val = 0x70 ;
 621
 622         state->TunerRegs[59].Reg_Num = 92 ;
 623         state->TunerRegs[59].Reg_Val = 0x00 ;
 624
 625         state->TunerRegs[60].Reg_Num = 93 ;
 626         state->TunerRegs[60].Reg_Val = 0x00 ;
 627
 628         state->TunerRegs[61].Reg_Num = 94 ;
 629         state->TunerRegs[61].Reg_Val = 0x00 ;
 630
 631         state->TunerRegs[62].Reg_Num = 95 ;
 632         state->TunerRegs[62].Reg_Val = 0x0C ;
 633
 634         state->TunerRegs[63].Reg_Num = 96 ;
 635         state->TunerRegs[63].Reg_Val = 0x00 ;
 636
 637         state->TunerRegs[64].Reg_Num = 97 ;
 638         state->TunerRegs[64].Reg_Val = 0x00 ;
 639
 640         state->TunerRegs[65].Reg_Num = 98 ;
 641         state->TunerRegs[65].Reg_Val = 0xE2 ;
 642
 643         state->TunerRegs[66].Reg_Num = 99 ;
 644         state->TunerRegs[66].Reg_Val = 0x00 ;
 645
 646         state->TunerRegs[67].Reg_Num = 100 ;
 647         state->TunerRegs[67].Reg_Val = 0x00 ;
 648
 649         state->TunerRegs[68].Reg_Num = 101 ;
 650         state->TunerRegs[68].Reg_Val = 0x12 ;
 651
 652         state->TunerRegs[69].Reg_Num = 102 ;
 653         state->TunerRegs[69].Reg_Val = 0x80 ;
 654
 655         state->TunerRegs[70].Reg_Num = 103 ;
 656         state->TunerRegs[70].Reg_Val = 0x32 ;
 657
 658         state->TunerRegs[71].Reg_Num = 104 ;
 659         state->TunerRegs[71].Reg_Val = 0xB4 ;
 660
 661         state->TunerRegs[72].Reg_Num = 105 ;
 662         state->TunerRegs[72].Reg_Val = 0x60 ;
 663
 664         state->TunerRegs[73].Reg_Num = 106 ;
 665         state->TunerRegs[73].Reg_Val = 0x83 ;
 666
 667         state->TunerRegs[74].Reg_Num = 107 ;
 668         state->TunerRegs[74].Reg_Val = 0x84 ;
 669
 670         state->TunerRegs[75].Reg_Num = 108 ;
 671         state->TunerRegs[75].Reg_Val = 0x9C ;
 672
 673         state->TunerRegs[76].Reg_Num = 109 ;
 674         state->TunerRegs[76].Reg_Val = 0x02 ;
 675
 676         state->TunerRegs[77].Reg_Num = 110 ;
 677         state->TunerRegs[77].Reg_Val = 0x81 ;
 678
 679         state->TunerRegs[78].Reg_Num = 111 ;
 680         state->TunerRegs[78].Reg_Val = 0xC0 ;
 681
 682         state->TunerRegs[79].Reg_Num = 112 ;
 683         state->TunerRegs[79].Reg_Val = 0x10 ;
 684
 685         state->TunerRegs[80].Reg_Num = 131 ;
 686         state->TunerRegs[80].Reg_Val = 0x8A ;
 687
 688         state->TunerRegs[81].Reg_Num = 132 ;
 689         state->TunerRegs[81].Reg_Val = 0x10 ;
 690
 691         state->TunerRegs[82].Reg_Num = 133 ;
 692         state->TunerRegs[82].Reg_Val = 0x24 ;
 693
 694         state->TunerRegs[83].Reg_Num = 134 ;
 695         state->TunerRegs[83].Reg_Val = 0x00 ;
 696
 697         state->TunerRegs[84].Reg_Num = 135 ;
 698         state->TunerRegs[84].Reg_Val = 0x00 ;
 699
 700         state->TunerRegs[85].Reg_Num = 136 ;
 701         state->TunerRegs[85].Reg_Val = 0x7E ;
 702
 703         state->TunerRegs[86].Reg_Num = 137 ;
 704         state->TunerRegs[86].Reg_Val = 0x40 ;
 705
 706         state->TunerRegs[87].Reg_Num = 138 ;
 707         state->TunerRegs[87].Reg_Val = 0x38 ;
 708
 709         state->TunerRegs[88].Reg_Num = 146 ;
 710         state->TunerRegs[88].Reg_Val = 0xF6 ;
 711
 712         state->TunerRegs[89].Reg_Num = 147 ;
 713         state->TunerRegs[89].Reg_Val = 0x1A ;
 714
 715         state->TunerRegs[90].Reg_Num = 148 ;
 716         state->TunerRegs[90].Reg_Val = 0x62 ;
 717
 718         state->TunerRegs[91].Reg_Num = 149 ;
 719         state->TunerRegs[91].Reg_Val = 0x33 ;
 720
 721         state->TunerRegs[92].Reg_Num = 150 ;
 722         state->TunerRegs[92].Reg_Val = 0x80 ;
 723
 724         state->TunerRegs[93].Reg_Num = 156 ;
 725         state->TunerRegs[93].Reg_Val = 0x56 ;
 726
 727         state->TunerRegs[94].Reg_Num = 157 ;
 728         state->TunerRegs[94].Reg_Val = 0x17 ;
 729
 730         state->TunerRegs[95].Reg_Num = 158 ;
 731         state->TunerRegs[95].Reg_Val = 0xA9 ;
 732
 733         state->TunerRegs[96].Reg_Num = 159 ;
 734         state->TunerRegs[96].Reg_Val = 0x00 ;
 735
 736         state->TunerRegs[97].Reg_Num = 160 ;
 737         state->TunerRegs[97].Reg_Val = 0x00 ;
 738
 739         state->TunerRegs[98].Reg_Num = 161 ;
 740         state->TunerRegs[98].Reg_Val = 0x00 ;
 741
 742         state->TunerRegs[99].Reg_Num = 162 ;
 743         state->TunerRegs[99].Reg_Val = 0x40 ;
 744
 745         state->TunerRegs[100].Reg_Num = 166 ;
 746         state->TunerRegs[100].Reg_Val = 0xAE ;
 747
 748         state->TunerRegs[101].Reg_Num = 167 ;
 749         state->TunerRegs[101].Reg_Val = 0x1B ;
 750
 751         state->TunerRegs[102].Reg_Num = 168 ;
 752         state->TunerRegs[102].Reg_Val = 0xF2 ;
 753
 754         state->TunerRegs[103].Reg_Num = 195 ;
 755         state->TunerRegs[103].Reg_Val = 0x00 ;
 756
 757         return 0 ;
 758 }
 759
 760 // DONE
 761 u16 MXL5005_ControlInit(struct dvb_frontend *fe)
 762 {
 763         struct mxl5005s_state *state = fe->tuner_priv;
 764         state->Init_Ctrl_Num = INITCTRL_NUM;
 765
 766         state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
 767         state->Init_Ctrl[0].size = 1 ;
 768         state->Init_Ctrl[0].addr[0] = 73;
 769         state->Init_Ctrl[0].bit[0] = 7;
 770         state->Init_Ctrl[0].val[0] = 0;
 771
 772         state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
 773         state->Init_Ctrl[1].size = 1 ;
 774         state->Init_Ctrl[1].addr[0] = 53;
 775         state->Init_Ctrl[1].bit[0] = 2;
 776         state->Init_Ctrl[1].val[0] = 1;
 777
 778         state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
 779         state->Init_Ctrl[2].size = 2 ;
 780         state->Init_Ctrl[2].addr[0] = 53;
 781         state->Init_Ctrl[2].bit[0] = 1;
 782         state->Init_Ctrl[2].val[0] = 0;
 783         state->Init_Ctrl[2].addr[1] = 57;
 784         state->Init_Ctrl[2].bit[1] = 0;
 785         state->Init_Ctrl[2].val[1] = 1;
 786
 787         state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
 788         state->Init_Ctrl[3].size = 1 ;
 789         state->Init_Ctrl[3].addr[0] = 53;
 790         state->Init_Ctrl[3].bit[0] = 0;
 791         state->Init_Ctrl[3].val[0] = 0;
 792
 793         state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
 794         state->Init_Ctrl[4].size = 3 ;
 795         state->Init_Ctrl[4].addr[0] = 53;
 796         state->Init_Ctrl[4].bit[0] = 5;
 797         state->Init_Ctrl[4].val[0] = 0;
 798         state->Init_Ctrl[4].addr[1] = 53;
 799         state->Init_Ctrl[4].bit[1] = 6;
 800         state->Init_Ctrl[4].val[1] = 0;
 801         state->Init_Ctrl[4].addr[2] = 53;
 802         state->Init_Ctrl[4].bit[2] = 7;
 803         state->Init_Ctrl[4].val[2] = 1;
 804
 805         state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
 806         state->Init_Ctrl[5].size = 1 ;
 807         state->Init_Ctrl[5].addr[0] = 59;
 808         state->Init_Ctrl[5].bit[0] = 0;
 809         state->Init_Ctrl[5].val[0] = 0;
 810
 811         state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
 812         state->Init_Ctrl[6].size = 2 ;
 813         state->Init_Ctrl[6].addr[0] = 53;
 814         state->Init_Ctrl[6].bit[0] = 3;
 815         state->Init_Ctrl[6].val[0] = 0;
 816         state->Init_Ctrl[6].addr[1] = 53;
 817         state->Init_Ctrl[6].bit[1] = 4;
 818         state->Init_Ctrl[6].val[1] = 1;
 819
 820         state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
 821         state->Init_Ctrl[7].size = 4 ;
 822         state->Init_Ctrl[7].addr[0] = 22;
 823         state->Init_Ctrl[7].bit[0] = 4;
 824         state->Init_Ctrl[7].val[0] = 0;
 825         state->Init_Ctrl[7].addr[1] = 22;
 826         state->Init_Ctrl[7].bit[1] = 5;
 827         state->Init_Ctrl[7].val[1] = 1;
 828         state->Init_Ctrl[7].addr[2] = 22;
 829         state->Init_Ctrl[7].bit[2] = 6;
 830         state->Init_Ctrl[7].val[2] = 1;
 831         state->Init_Ctrl[7].addr[3] = 22;
 832         state->Init_Ctrl[7].bit[3] = 7;
 833         state->Init_Ctrl[7].val[3] = 0;
 834
 835         state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
 836         state->Init_Ctrl[8].size = 1 ;
 837         state->Init_Ctrl[8].addr[0] = 22;
 838         state->Init_Ctrl[8].bit[0] = 2;
 839         state->Init_Ctrl[8].val[0] = 0;
 840
 841         state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
 842         state->Init_Ctrl[9].size = 4 ;
 843         state->Init_Ctrl[9].addr[0] = 76;
 844         state->Init_Ctrl[9].bit[0] = 0;
 845         state->Init_Ctrl[9].val[0] = 1;
 846         state->Init_Ctrl[9].addr[1] = 76;
 847         state->Init_Ctrl[9].bit[1] = 1;
 848         state->Init_Ctrl[9].val[1] = 1;
 849         state->Init_Ctrl[9].addr[2] = 76;
 850         state->Init_Ctrl[9].bit[2] = 2;
 851         state->Init_Ctrl[9].val[2] = 0;
 852         state->Init_Ctrl[9].addr[3] = 76;
 853         state->Init_Ctrl[9].bit[3] = 3;
 854         state->Init_Ctrl[9].val[3] = 1;
 855
 856         state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
 857         state->Init_Ctrl[10].size = 4 ;
 858         state->Init_Ctrl[10].addr[0] = 76;
 859         state->Init_Ctrl[10].bit[0] = 4;
 860         state->Init_Ctrl[10].val[0] = 1;
 861         state->Init_Ctrl[10].addr[1] = 76;
 862         state->Init_Ctrl[10].bit[1] = 5;
 863         state->Init_Ctrl[10].val[1] = 1;
 864         state->Init_Ctrl[10].addr[2] = 76;
 865         state->Init_Ctrl[10].bit[2] = 6;
 866         state->Init_Ctrl[10].val[2] = 0;
 867         state->Init_Ctrl[10].addr[3] = 76;
 868         state->Init_Ctrl[10].bit[3] = 7;
 869         state->Init_Ctrl[10].val[3] = 1;
 870
 871         state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
 872         state->Init_Ctrl[11].size = 5 ;
 873         state->Init_Ctrl[11].addr[0] = 43;
 874         state->Init_Ctrl[11].bit[0] = 3;
 875         state->Init_Ctrl[11].val[0] = 0;
 876         state->Init_Ctrl[11].addr[1] = 43;
 877         state->Init_Ctrl[11].bit[1] = 4;
 878         state->Init_Ctrl[11].val[1] = 0;
 879         state->Init_Ctrl[11].addr[2] = 43;
 880         state->Init_Ctrl[11].bit[2] = 5;
 881         state->Init_Ctrl[11].val[2] = 0;
 882         state->Init_Ctrl[11].addr[3] = 43;
 883         state->Init_Ctrl[11].bit[3] = 6;
 884         state->Init_Ctrl[11].val[3] = 1;
 885         state->Init_Ctrl[11].addr[4] = 43;
 886         state->Init_Ctrl[11].bit[4] = 7;
 887         state->Init_Ctrl[11].val[4] = 0;
 888
 889         state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
 890         state->Init_Ctrl[12].size = 6 ;
 891         state->Init_Ctrl[12].addr[0] = 44;
 892         state->Init_Ctrl[12].bit[0] = 2;
 893         state->Init_Ctrl[12].val[0] = 0;
 894         state->Init_Ctrl[12].addr[1] = 44;
 895         state->Init_Ctrl[12].bit[1] = 3;
 896         state->Init_Ctrl[12].val[1] = 0;
 897         state->Init_Ctrl[12].addr[2] = 44;
 898         state->Init_Ctrl[12].bit[2] = 4;
 899         state->Init_Ctrl[12].val[2] = 0;
 900         state->Init_Ctrl[12].addr[3] = 44;
 901         state->Init_Ctrl[12].bit[3] = 5;
 902         state->Init_Ctrl[12].val[3] = 1;
 903         state->Init_Ctrl[12].addr[4] = 44;
 904         state->Init_Ctrl[12].bit[4] = 6;
 905         state->Init_Ctrl[12].val[4] = 0;
 906         state->Init_Ctrl[12].addr[5] = 44;
 907         state->Init_Ctrl[12].bit[5] = 7;
 908         state->Init_Ctrl[12].val[5] = 0;
 909
 910         state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
 911         state->Init_Ctrl[13].size = 7 ;
 912         state->Init_Ctrl[13].addr[0] = 11;
 913         state->Init_Ctrl[13].bit[0] = 0;
 914         state->Init_Ctrl[13].val[0] = 1;
 915         state->Init_Ctrl[13].addr[1] = 11;
 916         state->Init_Ctrl[13].bit[1] = 1;
 917         state->Init_Ctrl[13].val[1] = 0;
 918         state->Init_Ctrl[13].addr[2] = 11;
 919         state->Init_Ctrl[13].bit[2] = 2;
 920         state->Init_Ctrl[13].val[2] = 0;
 921         state->Init_Ctrl[13].addr[3] = 11;
 922         state->Init_Ctrl[13].bit[3] = 3;
 923         state->Init_Ctrl[13].val[3] = 1;
 924         state->Init_Ctrl[13].addr[4] = 11;
 925         state->Init_Ctrl[13].bit[4] = 4;
 926         state->Init_Ctrl[13].val[4] = 1;
 927         state->Init_Ctrl[13].addr[5] = 11;
 928         state->Init_Ctrl[13].bit[5] = 5;
 929         state->Init_Ctrl[13].val[5] = 0;
 930         state->Init_Ctrl[13].addr[6] = 11;
 931         state->Init_Ctrl[13].bit[6] = 6;
 932         state->Init_Ctrl[13].val[6] = 0;
 933
 934         state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
 935         state->Init_Ctrl[14].size = 16 ;
 936         state->Init_Ctrl[14].addr[0] = 13;
 937         state->Init_Ctrl[14].bit[0] = 0;
 938         state->Init_Ctrl[14].val[0] = 0;
 939         state->Init_Ctrl[14].addr[1] = 13;
 940         state->Init_Ctrl[14].bit[1] = 1;
 941         state->Init_Ctrl[14].val[1] = 0;
 942         state->Init_Ctrl[14].addr[2] = 13;
 943         state->Init_Ctrl[14].bit[2] = 2;
 944         state->Init_Ctrl[14].val[2] = 0;
 945         state->Init_Ctrl[14].addr[3] = 13;
 946         state->Init_Ctrl[14].bit[3] = 3;
 947         state->Init_Ctrl[14].val[3] = 0;
 948         state->Init_Ctrl[14].addr[4] = 13;
 949         state->Init_Ctrl[14].bit[4] = 4;
 950         state->Init_Ctrl[14].val[4] = 0;
 951         state->Init_Ctrl[14].addr[5] = 13;
 952         state->Init_Ctrl[14].bit[5] = 5;
 953         state->Init_Ctrl[14].val[5] = 0;
 954         state->Init_Ctrl[14].addr[6] = 13;
 955         state->Init_Ctrl[14].bit[6] = 6;
 956         state->Init_Ctrl[14].val[6] = 0;
 957         state->Init_Ctrl[14].addr[7] = 13;
 958         state->Init_Ctrl[14].bit[7] = 7;
 959         state->Init_Ctrl[14].val[7] = 0;
 960         state->Init_Ctrl[14].addr[8] = 12;
 961         state->Init_Ctrl[14].bit[8] = 0;
 962         state->Init_Ctrl[14].val[8] = 0;
 963         state->Init_Ctrl[14].addr[9] = 12;
 964         state->Init_Ctrl[14].bit[9] = 1;
 965         state->Init_Ctrl[14].val[9] = 0;
 966         state->Init_Ctrl[14].addr[10] = 12;
 967         state->Init_Ctrl[14].bit[10] = 2;
 968         state->Init_Ctrl[14].val[10] = 0;
 969         state->Init_Ctrl[14].addr[11] = 12;
 970         state->Init_Ctrl[14].bit[11] = 3;
 971         state->Init_Ctrl[14].val[11] = 0;
 972         state->Init_Ctrl[14].addr[12] = 12;
 973         state->Init_Ctrl[14].bit[12] = 4;
 974         state->Init_Ctrl[14].val[12] = 0;
 975         state->Init_Ctrl[14].addr[13] = 12;
 976         state->Init_Ctrl[14].bit[13] = 5;
 977         state->Init_Ctrl[14].val[13] = 1;
 978         state->Init_Ctrl[14].addr[14] = 12;
 979         state->Init_Ctrl[14].bit[14] = 6;
 980         state->Init_Ctrl[14].val[14] = 1;
 981         state->Init_Ctrl[14].addr[15] = 12;
 982         state->Init_Ctrl[14].bit[15] = 7;
 983         state->Init_Ctrl[14].val[15] = 0;
 984
 985         state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
 986         state->Init_Ctrl[15].size = 3 ;
 987         state->Init_Ctrl[15].addr[0] = 147;
 988         state->Init_Ctrl[15].bit[0] = 2;
 989         state->Init_Ctrl[15].val[0] = 0;
 990         state->Init_Ctrl[15].addr[1] = 147;
 991         state->Init_Ctrl[15].bit[1] = 3;
 992         state->Init_Ctrl[15].val[1] = 1;
 993         state->Init_Ctrl[15].addr[2] = 147;
 994         state->Init_Ctrl[15].bit[2] = 4;
 995         state->Init_Ctrl[15].val[2] = 1;
 996
 997         state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
 998         state->Init_Ctrl[16].size = 2 ;
 999         state->Init_Ctrl[16].addr[0] = 147;
1000         state->Init_Ctrl[16].bit[0] = 0;
1001         state->Init_Ctrl[16].val[0] = 0;
1002         state->Init_Ctrl[16].addr[1] = 147;
1003         state->Init_Ctrl[16].bit[1] = 1;
1004         state->Init_Ctrl[16].val[1] = 1;
1005
1006         state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
1007         state->Init_Ctrl[17].size = 1 ;
1008         state->Init_Ctrl[17].addr[0] = 147;
1009         state->Init_Ctrl[17].bit[0] = 7;
1010         state->Init_Ctrl[17].val[0] = 0;
1011
1012         state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
1013         state->Init_Ctrl[18].size = 1 ;
1014         state->Init_Ctrl[18].addr[0] = 147;
1015         state->Init_Ctrl[18].bit[0] = 6;
1016         state->Init_Ctrl[18].val[0] = 0;
1017
1018         state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
1019         state->Init_Ctrl[19].size = 1 ;
1020         state->Init_Ctrl[19].addr[0] = 156;
1021         state->Init_Ctrl[19].bit[0] = 0;
1022         state->Init_Ctrl[19].val[0] = 0;
1023
1024         state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
1025         state->Init_Ctrl[20].size = 1 ;
1026         state->Init_Ctrl[20].addr[0] = 147;
1027         state->Init_Ctrl[20].bit[0] = 5;
1028         state->Init_Ctrl[20].val[0] = 0;
1029
1030         state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
1031         state->Init_Ctrl[21].size = 1 ;
1032         state->Init_Ctrl[21].addr[0] = 137;
1033         state->Init_Ctrl[21].bit[0] = 4;
1034         state->Init_Ctrl[21].val[0] = 0;
1035
1036         state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
1037         state->Init_Ctrl[22].size = 1 ;
1038         state->Init_Ctrl[22].addr[0] = 137;
1039         state->Init_Ctrl[22].bit[0] = 7;
1040         state->Init_Ctrl[22].val[0] = 0;
1041
1042         state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1043         state->Init_Ctrl[23].size = 1 ;
1044         state->Init_Ctrl[23].addr[0] = 91;
1045         state->Init_Ctrl[23].bit[0] = 5;
1046         state->Init_Ctrl[23].val[0] = 1;
1047
1048         state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1049         state->Init_Ctrl[24].size = 1 ;
1050         state->Init_Ctrl[24].addr[0] = 43;
1051         state->Init_Ctrl[24].bit[0] = 0;
1052         state->Init_Ctrl[24].val[0] = 1;
1053
1054         state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1055         state->Init_Ctrl[25].size = 2 ;
1056         state->Init_Ctrl[25].addr[0] = 22;
1057         state->Init_Ctrl[25].bit[0] = 0;
1058         state->Init_Ctrl[25].val[0] = 1;
1059         state->Init_Ctrl[25].addr[1] = 22;
1060         state->Init_Ctrl[25].bit[1] = 1;
1061         state->Init_Ctrl[25].val[1] = 1;
1062
1063         state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1064         state->Init_Ctrl[26].size = 1 ;
1065         state->Init_Ctrl[26].addr[0] = 134;
1066         state->Init_Ctrl[26].bit[0] = 2;
1067         state->Init_Ctrl[26].val[0] = 0;
1068
1069         state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1070         state->Init_Ctrl[27].size = 1 ;
1071         state->Init_Ctrl[27].addr[0] = 137;
1072         state->Init_Ctrl[27].bit[0] = 3;
1073         state->Init_Ctrl[27].val[0] = 0;
1074
1075         state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1076         state->Init_Ctrl[28].size = 1 ;
1077         state->Init_Ctrl[28].addr[0] = 77;
1078         state->Init_Ctrl[28].bit[0] = 7;
1079         state->Init_Ctrl[28].val[0] = 0;
1080
1081         state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1082         state->Init_Ctrl[29].size = 1 ;
1083         state->Init_Ctrl[29].addr[0] = 166;
1084         state->Init_Ctrl[29].bit[0] = 7;
1085         state->Init_Ctrl[29].val[0] = 1;
1086
1087         state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1088         state->Init_Ctrl[30].size = 3 ;
1089         state->Init_Ctrl[30].addr[0] = 166;
1090         state->Init_Ctrl[30].bit[0] = 0;
1091         state->Init_Ctrl[30].val[0] = 0;
1092         state->Init_Ctrl[30].addr[1] = 166;
1093         state->Init_Ctrl[30].bit[1] = 1;
1094         state->Init_Ctrl[30].val[1] = 1;
1095         state->Init_Ctrl[30].addr[2] = 166;
1096         state->Init_Ctrl[30].bit[2] = 2;
1097         state->Init_Ctrl[30].val[2] = 1;
1098
1099         state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1100         state->Init_Ctrl[31].size = 3 ;
1101         state->Init_Ctrl[31].addr[0] = 166;
1102         state->Init_Ctrl[31].bit[0] = 3;
1103         state->Init_Ctrl[31].val[0] = 1;
1104         state->Init_Ctrl[31].addr[1] = 166;
1105         state->Init_Ctrl[31].bit[1] = 4;
1106         state->Init_Ctrl[31].val[1] = 0;
1107         state->Init_Ctrl[31].addr[2] = 166;
1108         state->Init_Ctrl[31].bit[2] = 5;
1109         state->Init_Ctrl[31].val[2] = 1;
1110
1111         state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1112         state->Init_Ctrl[32].size = 3 ;
1113         state->Init_Ctrl[32].addr[0] = 167;
1114         state->Init_Ctrl[32].bit[0] = 0;
1115         state->Init_Ctrl[32].val[0] = 1;
1116         state->Init_Ctrl[32].addr[1] = 167;
1117         state->Init_Ctrl[32].bit[1] = 1;
1118         state->Init_Ctrl[32].val[1] = 1;
1119         state->Init_Ctrl[32].addr[2] = 167;
1120         state->Init_Ctrl[32].bit[2] = 2;
1121         state->Init_Ctrl[32].val[2] = 0;
1122
1123         state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1124         state->Init_Ctrl[33].size = 4 ;
1125         state->Init_Ctrl[33].addr[0] = 168;
1126         state->Init_Ctrl[33].bit[0] = 0;
1127         state->Init_Ctrl[33].val[0] = 0;
1128         state->Init_Ctrl[33].addr[1] = 168;
1129         state->Init_Ctrl[33].bit[1] = 1;
1130         state->Init_Ctrl[33].val[1] = 1;
1131         state->Init_Ctrl[33].addr[2] = 168;
1132         state->Init_Ctrl[33].bit[2] = 2;
1133         state->Init_Ctrl[33].val[2] = 0;
1134         state->Init_Ctrl[33].addr[3] = 168;
1135         state->Init_Ctrl[33].bit[3] = 3;
1136         state->Init_Ctrl[33].val[3] = 0;
1137
1138         state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1139         state->Init_Ctrl[34].size = 4 ;
1140         state->Init_Ctrl[34].addr[0] = 168;
1141         state->Init_Ctrl[34].bit[0] = 4;
1142         state->Init_Ctrl[34].val[0] = 1;
1143         state->Init_Ctrl[34].addr[1] = 168;
1144         state->Init_Ctrl[34].bit[1] = 5;
1145         state->Init_Ctrl[34].val[1] = 1;
1146         state->Init_Ctrl[34].addr[2] = 168;
1147         state->Init_Ctrl[34].bit[2] = 6;
1148         state->Init_Ctrl[34].val[2] = 1;
1149         state->Init_Ctrl[34].addr[3] = 168;
1150         state->Init_Ctrl[34].bit[3] = 7;
1151         state->Init_Ctrl[34].val[3] = 1;
1152
1153         state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1154         state->Init_Ctrl[35].size = 1 ;
1155         state->Init_Ctrl[35].addr[0] = 135;
1156         state->Init_Ctrl[35].bit[0] = 0;
1157         state->Init_Ctrl[35].val[0] = 0;
1158
1159         state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1160         state->Init_Ctrl[36].size = 1 ;
1161         state->Init_Ctrl[36].addr[0] = 56;
1162         state->Init_Ctrl[36].bit[0] = 3;
1163         state->Init_Ctrl[36].val[0] = 0;
1164
1165         state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1166         state->Init_Ctrl[37].size = 7 ;
1167         state->Init_Ctrl[37].addr[0] = 59;
1168         state->Init_Ctrl[37].bit[0] = 1;
1169         state->Init_Ctrl[37].val[0] = 0;
1170         state->Init_Ctrl[37].addr[1] = 59;
1171         state->Init_Ctrl[37].bit[1] = 2;
1172         state->Init_Ctrl[37].val[1] = 0;
1173         state->Init_Ctrl[37].addr[2] = 59;
1174         state->Init_Ctrl[37].bit[2] = 3;
1175         state->Init_Ctrl[37].val[2] = 0;
1176         state->Init_Ctrl[37].addr[3] = 59;
1177         state->Init_Ctrl[37].bit[3] = 4;
1178         state->Init_Ctrl[37].val[3] = 0;
1179         state->Init_Ctrl[37].addr[4] = 59;
1180         state->Init_Ctrl[37].bit[4] = 5;
1181         state->Init_Ctrl[37].val[4] = 0;
1182         state->Init_Ctrl[37].addr[5] = 59;
1183         state->Init_Ctrl[37].bit[5] = 6;
1184         state->Init_Ctrl[37].val[5] = 0;
1185         state->Init_Ctrl[37].addr[6] = 59;
1186         state->Init_Ctrl[37].bit[6] = 7;
1187         state->Init_Ctrl[37].val[6] = 0;
1188
1189         state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1190         state->Init_Ctrl[38].size = 6 ;
1191         state->Init_Ctrl[38].addr[0] = 32;
1192         state->Init_Ctrl[38].bit[0] = 2;
1193         state->Init_Ctrl[38].val[0] = 0;
1194         state->Init_Ctrl[38].addr[1] = 32;
1195         state->Init_Ctrl[38].bit[1] = 3;
1196         state->Init_Ctrl[38].val[1] = 0;
1197         state->Init_Ctrl[38].addr[2] = 32;
1198         state->Init_Ctrl[38].bit[2] = 4;
1199         state->Init_Ctrl[38].val[2] = 0;
1200         state->Init_Ctrl[38].addr[3] = 32;
1201         state->Init_Ctrl[38].bit[3] = 5;
1202         state->Init_Ctrl[38].val[3] = 0;
1203         state->Init_Ctrl[38].addr[4] = 32;
1204         state->Init_Ctrl[38].bit[4] = 6;
1205         state->Init_Ctrl[38].val[4] = 1;
1206         state->Init_Ctrl[38].addr[5] = 32;
1207         state->Init_Ctrl[38].bit[5] = 7;
1208         state->Init_Ctrl[38].val[5] = 0;
1209
1210         state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1211         state->Init_Ctrl[39].size = 1 ;
1212         state->Init_Ctrl[39].addr[0] = 25;
1213         state->Init_Ctrl[39].bit[0] = 3;
1214         state->Init_Ctrl[39].val[0] = 1;
1215
1216
1217         state->CH_Ctrl_Num = CHCTRL_NUM ;
1218
1219         state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1220         state->CH_Ctrl[0].size = 2 ;
1221         state->CH_Ctrl[0].addr[0] = 68;
1222         state->CH_Ctrl[0].bit[0] = 6;
1223         state->CH_Ctrl[0].val[0] = 1;
1224         state->CH_Ctrl[0].addr[1] = 68;
1225         state->CH_Ctrl[0].bit[1] = 7;
1226         state->CH_Ctrl[0].val[1] = 1;
1227
1228         state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1229         state->CH_Ctrl[1].size = 2 ;
1230         state->CH_Ctrl[1].addr[0] = 70;
1231         state->CH_Ctrl[1].bit[0] = 6;
1232         state->CH_Ctrl[1].val[0] = 1;
1233         state->CH_Ctrl[1].addr[1] = 70;
1234         state->CH_Ctrl[1].bit[1] = 7;
1235         state->CH_Ctrl[1].val[1] = 0;
1236
1237         state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1238         state->CH_Ctrl[2].size = 9 ;
1239         state->CH_Ctrl[2].addr[0] = 69;
1240         state->CH_Ctrl[2].bit[0] = 5;
1241         state->CH_Ctrl[2].val[0] = 0;
1242         state->CH_Ctrl[2].addr[1] = 69;
1243         state->CH_Ctrl[2].bit[1] = 6;
1244         state->CH_Ctrl[2].val[1] = 0;
1245         state->CH_Ctrl[2].addr[2] = 69;
1246         state->CH_Ctrl[2].bit[2] = 7;
1247         state->CH_Ctrl[2].val[2] = 0;
1248         state->CH_Ctrl[2].addr[3] = 68;
1249         state->CH_Ctrl[2].bit[3] = 0;
1250         state->CH_Ctrl[2].val[3] = 0;
1251         state->CH_Ctrl[2].addr[4] = 68;
1252         state->CH_Ctrl[2].bit[4] = 1;
1253         state->CH_Ctrl[2].val[4] = 0;
1254         state->CH_Ctrl[2].addr[5] = 68;
1255         state->CH_Ctrl[2].bit[5] = 2;
1256         state->CH_Ctrl[2].val[5] = 0;
1257         state->CH_Ctrl[2].addr[6] = 68;
1258         state->CH_Ctrl[2].bit[6] = 3;
1259         state->CH_Ctrl[2].val[6] = 0;
1260         state->CH_Ctrl[2].addr[7] = 68;
1261         state->CH_Ctrl[2].bit[7] = 4;
1262         state->CH_Ctrl[2].val[7] = 0;
1263         state->CH_Ctrl[2].addr[8] = 68;
1264         state->CH_Ctrl[2].bit[8] = 5;
1265         state->CH_Ctrl[2].val[8] = 0;
1266
1267         state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1268         state->CH_Ctrl[3].size = 1 ;
1269         state->CH_Ctrl[3].addr[0] = 70;
1270         state->CH_Ctrl[3].bit[0] = 5;
1271         state->CH_Ctrl[3].val[0] = 0;
1272
1273         state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1274         state->CH_Ctrl[4].size = 3 ;
1275         state->CH_Ctrl[4].addr[0] = 73;
1276         state->CH_Ctrl[4].bit[0] = 4;
1277         state->CH_Ctrl[4].val[0] = 0;
1278         state->CH_Ctrl[4].addr[1] = 73;
1279         state->CH_Ctrl[4].bit[1] = 5;
1280         state->CH_Ctrl[4].val[1] = 1;
1281         state->CH_Ctrl[4].addr[2] = 73;
1282         state->CH_Ctrl[4].bit[2] = 6;
1283         state->CH_Ctrl[4].val[2] = 0;
1284
1285         state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1286         state->CH_Ctrl[5].size = 4 ;
1287         state->CH_Ctrl[5].addr[0] = 70;
1288         state->CH_Ctrl[5].bit[0] = 0;
1289         state->CH_Ctrl[5].val[0] = 0;
1290         state->CH_Ctrl[5].addr[1] = 70;
1291         state->CH_Ctrl[5].bit[1] = 1;
1292         state->CH_Ctrl[5].val[1] = 0;
1293         state->CH_Ctrl[5].addr[2] = 70;
1294         state->CH_Ctrl[5].bit[2] = 2;
1295         state->CH_Ctrl[5].val[2] = 0;
1296         state->CH_Ctrl[5].addr[3] = 70;
1297         state->CH_Ctrl[5].bit[3] = 3;
1298         state->CH_Ctrl[5].val[3] = 0;
1299
1300         state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1301         state->CH_Ctrl[6].size = 1 ;
1302         state->CH_Ctrl[6].addr[0] = 70;
1303         state->CH_Ctrl[6].bit[0] = 4;
1304         state->CH_Ctrl[6].val[0] = 1;
1305
1306         state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1307         state->CH_Ctrl[7].size = 1 ;
1308         state->CH_Ctrl[7].addr[0] = 111;
1309         state->CH_Ctrl[7].bit[0] = 4;
1310         state->CH_Ctrl[7].val[0] = 0;
1311
1312         state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1313         state->CH_Ctrl[8].size = 1 ;
1314         state->CH_Ctrl[8].addr[0] = 111;
1315         state->CH_Ctrl[8].bit[0] = 7;
1316         state->CH_Ctrl[8].val[0] = 1;
1317
1318         state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1319         state->CH_Ctrl[9].size = 1 ;
1320         state->CH_Ctrl[9].addr[0] = 111;
1321         state->CH_Ctrl[9].bit[0] = 6;
1322         state->CH_Ctrl[9].val[0] = 1;
1323
1324         state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1325         state->CH_Ctrl[10].size = 1 ;
1326         state->CH_Ctrl[10].addr[0] = 111;
1327         state->CH_Ctrl[10].bit[0] = 5;
1328         state->CH_Ctrl[10].val[0] = 0;
1329
1330         state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1331         state->CH_Ctrl[11].size = 2 ;
1332         state->CH_Ctrl[11].addr[0] = 110;
1333         state->CH_Ctrl[11].bit[0] = 0;
1334         state->CH_Ctrl[11].val[0] = 1;
1335         state->CH_Ctrl[11].addr[1] = 110;
1336         state->CH_Ctrl[11].bit[1] = 1;
1337         state->CH_Ctrl[11].val[1] = 0;
1338
1339         state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1340         state->CH_Ctrl[12].size = 3 ;
1341         state->CH_Ctrl[12].addr[0] = 69;
1342         state->CH_Ctrl[12].bit[0] = 2;
1343         state->CH_Ctrl[12].val[0] = 0;
1344         state->CH_Ctrl[12].addr[1] = 69;
1345         state->CH_Ctrl[12].bit[1] = 3;
1346         state->CH_Ctrl[12].val[1] = 0;
1347         state->CH_Ctrl[12].addr[2] = 69;
1348         state->CH_Ctrl[12].bit[2] = 4;
1349         state->CH_Ctrl[12].val[2] = 0;
1350
1351         state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1352         state->CH_Ctrl[13].size = 6 ;
1353         state->CH_Ctrl[13].addr[0] = 110;
1354         state->CH_Ctrl[13].bit[0] = 2;
1355         state->CH_Ctrl[13].val[0] = 0;
1356         state->CH_Ctrl[13].addr[1] = 110;
1357         state->CH_Ctrl[13].bit[1] = 3;
1358         state->CH_Ctrl[13].val[1] = 0;
1359         state->CH_Ctrl[13].addr[2] = 110;
1360         state->CH_Ctrl[13].bit[2] = 4;
1361         state->CH_Ctrl[13].val[2] = 0;
1362         state->CH_Ctrl[13].addr[3] = 110;
1363         state->CH_Ctrl[13].bit[3] = 5;
1364         state->CH_Ctrl[13].val[3] = 0;
1365         state->CH_Ctrl[13].addr[4] = 110;
1366         state->CH_Ctrl[13].bit[4] = 6;
1367         state->CH_Ctrl[13].val[4] = 0;
1368         state->CH_Ctrl[13].addr[5] = 110;
1369         state->CH_Ctrl[13].bit[5] = 7;
1370         state->CH_Ctrl[13].val[5] = 1;
1371
1372         state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1373         state->CH_Ctrl[14].size = 7 ;
1374         state->CH_Ctrl[14].addr[0] = 14;
1375         state->CH_Ctrl[14].bit[0] = 0;
1376         state->CH_Ctrl[14].val[0] = 0;
1377         state->CH_Ctrl[14].addr[1] = 14;
1378         state->CH_Ctrl[14].bit[1] = 1;
1379         state->CH_Ctrl[14].val[1] = 0;
1380         state->CH_Ctrl[14].addr[2] = 14;
1381         state->CH_Ctrl[14].bit[2] = 2;
1382         state->CH_Ctrl[14].val[2] = 0;
1383         state->CH_Ctrl[14].addr[3] = 14;
1384         state->CH_Ctrl[14].bit[3] = 3;
1385         state->CH_Ctrl[14].val[3] = 0;
1386         state->CH_Ctrl[14].addr[4] = 14;
1387         state->CH_Ctrl[14].bit[4] = 4;
1388         state->CH_Ctrl[14].val[4] = 0;
1389         state->CH_Ctrl[14].addr[5] = 14;
1390         state->CH_Ctrl[14].bit[5] = 5;
1391         state->CH_Ctrl[14].val[5] = 0;
1392         state->CH_Ctrl[14].addr[6] = 14;
1393         state->CH_Ctrl[14].bit[6] = 6;
1394         state->CH_Ctrl[14].val[6] = 0;
1395
1396         state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1397         state->CH_Ctrl[15].size = 18 ;
1398         state->CH_Ctrl[15].addr[0] = 17;
1399         state->CH_Ctrl[15].bit[0] = 6;
1400         state->CH_Ctrl[15].val[0] = 0;
1401         state->CH_Ctrl[15].addr[1] = 17;
1402         state->CH_Ctrl[15].bit[1] = 7;
1403         state->CH_Ctrl[15].val[1] = 0;
1404         state->CH_Ctrl[15].addr[2] = 16;
1405         state->CH_Ctrl[15].bit[2] = 0;
1406         state->CH_Ctrl[15].val[2] = 0;
1407         state->CH_Ctrl[15].addr[3] = 16;
1408         state->CH_Ctrl[15].bit[3] = 1;
1409         state->CH_Ctrl[15].val[3] = 0;
1410         state->CH_Ctrl[15].addr[4] = 16;
1411         state->CH_Ctrl[15].bit[4] = 2;
1412         state->CH_Ctrl[15].val[4] = 0;
1413         state->CH_Ctrl[15].addr[5] = 16;
1414         state->CH_Ctrl[15].bit[5] = 3;
1415         state->CH_Ctrl[15].val[5] = 0;
1416         state->CH_Ctrl[15].addr[6] = 16;
1417         state->CH_Ctrl[15].bit[6] = 4;
1418         state->CH_Ctrl[15].val[6] = 0;
1419         state->CH_Ctrl[15].addr[7] = 16;
1420         state->CH_Ctrl[15].bit[7] = 5;
1421         state->CH_Ctrl[15].val[7] = 0;
1422         state->CH_Ctrl[15].addr[8] = 16;
1423         state->CH_Ctrl[15].bit[8] = 6;
1424         state->CH_Ctrl[15].val[8] = 0;
1425         state->CH_Ctrl[15].addr[9] = 16;
1426         state->CH_Ctrl[15].bit[9] = 7;
1427         state->CH_Ctrl[15].val[9] = 0;
1428         state->CH_Ctrl[15].addr[10] = 15;
1429         state->CH_Ctrl[15].bit[10] = 0;
1430         state->CH_Ctrl[15].val[10] = 0;
1431         state->CH_Ctrl[15].addr[11] = 15;
1432         state->CH_Ctrl[15].bit[11] = 1;
1433         state->CH_Ctrl[15].val[11] = 0;
1434         state->CH_Ctrl[15].addr[12] = 15;
1435         state->CH_Ctrl[15].bit[12] = 2;
1436         state->CH_Ctrl[15].val[12] = 0;
1437         state->CH_Ctrl[15].addr[13] = 15;
1438         state->CH_Ctrl[15].bit[13] = 3;
1439         state->CH_Ctrl[15].val[13] = 0;
1440         state->CH_Ctrl[15].addr[14] = 15;
1441         state->CH_Ctrl[15].bit[14] = 4;
1442         state->CH_Ctrl[15].val[14] = 0;
1443         state->CH_Ctrl[15].addr[15] = 15;
1444         state->CH_Ctrl[15].bit[15] = 5;
1445         state->CH_Ctrl[15].val[15] = 0;
1446         state->CH_Ctrl[15].addr[16] = 15;
1447         state->CH_Ctrl[15].bit[16] = 6;
1448         state->CH_Ctrl[15].val[16] = 1;
1449         state->CH_Ctrl[15].addr[17] = 15;
1450         state->CH_Ctrl[15].bit[17] = 7;
1451         state->CH_Ctrl[15].val[17] = 1;
1452
1453         state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1454         state->CH_Ctrl[16].size = 5 ;
1455         state->CH_Ctrl[16].addr[0] = 112;
1456         state->CH_Ctrl[16].bit[0] = 0;
1457         state->CH_Ctrl[16].val[0] = 0;
1458         state->CH_Ctrl[16].addr[1] = 112;
1459         state->CH_Ctrl[16].bit[1] = 1;
1460         state->CH_Ctrl[16].val[1] = 0;
1461         state->CH_Ctrl[16].addr[2] = 112;
1462         state->CH_Ctrl[16].bit[2] = 2;
1463         state->CH_Ctrl[16].val[2] = 0;
1464         state->CH_Ctrl[16].addr[3] = 112;
1465         state->CH_Ctrl[16].bit[3] = 3;
1466         state->CH_Ctrl[16].val[3] = 0;
1467         state->CH_Ctrl[16].addr[4] = 112;
1468         state->CH_Ctrl[16].bit[4] = 4;
1469         state->CH_Ctrl[16].val[4] = 1;
1470
1471         state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1472         state->CH_Ctrl[17].size = 1 ;
1473         state->CH_Ctrl[17].addr[0] = 14;
1474         state->CH_Ctrl[17].bit[0] = 7;
1475         state->CH_Ctrl[17].val[0] = 0;
1476
1477         state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1478         state->CH_Ctrl[18].size = 4 ;
1479         state->CH_Ctrl[18].addr[0] = 107;
1480         state->CH_Ctrl[18].bit[0] = 3;
1481         state->CH_Ctrl[18].val[0] = 0;
1482         state->CH_Ctrl[18].addr[1] = 107;
1483         state->CH_Ctrl[18].bit[1] = 4;
1484         state->CH_Ctrl[18].val[1] = 0;
1485         state->CH_Ctrl[18].addr[2] = 107;
1486         state->CH_Ctrl[18].bit[2] = 5;
1487         state->CH_Ctrl[18].val[2] = 0;
1488         state->CH_Ctrl[18].addr[3] = 107;
1489         state->CH_Ctrl[18].bit[3] = 6;
1490         state->CH_Ctrl[18].val[3] = 0;
1491
1492         state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1493         state->CH_Ctrl[19].size = 3 ;
1494         state->CH_Ctrl[19].addr[0] = 107;
1495         state->CH_Ctrl[19].bit[0] = 7;
1496         state->CH_Ctrl[19].val[0] = 1;
1497         state->CH_Ctrl[19].addr[1] = 106;
1498         state->CH_Ctrl[19].bit[1] = 0;
1499         state->CH_Ctrl[19].val[1] = 1;
1500         state->CH_Ctrl[19].addr[2] = 106;
1501         state->CH_Ctrl[19].bit[2] = 1;
1502         state->CH_Ctrl[19].val[2] = 1;
1503
1504         state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1505         state->CH_Ctrl[20].size = 11 ;
1506         state->CH_Ctrl[20].addr[0] = 109;
1507         state->CH_Ctrl[20].bit[0] = 2;
1508         state->CH_Ctrl[20].val[0] = 0;
1509         state->CH_Ctrl[20].addr[1] = 109;
1510         state->CH_Ctrl[20].bit[1] = 3;
1511         state->CH_Ctrl[20].val[1] = 0;
1512         state->CH_Ctrl[20].addr[2] = 109;
1513         state->CH_Ctrl[20].bit[2] = 4;
1514         state->CH_Ctrl[20].val[2] = 0;
1515         state->CH_Ctrl[20].addr[3] = 109;
1516         state->CH_Ctrl[20].bit[3] = 5;
1517         state->CH_Ctrl[20].val[3] = 0;
1518         state->CH_Ctrl[20].addr[4] = 109;
1519         state->CH_Ctrl[20].bit[4] = 6;
1520         state->CH_Ctrl[20].val[4] = 0;
1521         state->CH_Ctrl[20].addr[5] = 109;
1522         state->CH_Ctrl[20].bit[5] = 7;
1523         state->CH_Ctrl[20].val[5] = 0;
1524         state->CH_Ctrl[20].addr[6] = 108;
1525         state->CH_Ctrl[20].bit[6] = 0;
1526         state->CH_Ctrl[20].val[6] = 0;
1527         state->CH_Ctrl[20].addr[7] = 108;
1528         state->CH_Ctrl[20].bit[7] = 1;
1529         state->CH_Ctrl[20].val[7] = 0;
1530         state->CH_Ctrl[20].addr[8] = 108;
1531         state->CH_Ctrl[20].bit[8] = 2;
1532         state->CH_Ctrl[20].val[8] = 1;
1533         state->CH_Ctrl[20].addr[9] = 108;
1534         state->CH_Ctrl[20].bit[9] = 3;
1535         state->CH_Ctrl[20].val[9] = 1;
1536         state->CH_Ctrl[20].addr[10] = 108;
1537         state->CH_Ctrl[20].bit[10] = 4;
1538         state->CH_Ctrl[20].val[10] = 1;
1539
1540         state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1541         state->CH_Ctrl[21].size = 6 ;
1542         state->CH_Ctrl[21].addr[0] = 106;
1543         state->CH_Ctrl[21].bit[0] = 2;
1544         state->CH_Ctrl[21].val[0] = 0;
1545         state->CH_Ctrl[21].addr[1] = 106;
1546         state->CH_Ctrl[21].bit[1] = 3;
1547         state->CH_Ctrl[21].val[1] = 0;
1548         state->CH_Ctrl[21].addr[2] = 106;
1549         state->CH_Ctrl[21].bit[2] = 4;
1550         state->CH_Ctrl[21].val[2] = 0;
1551         state->CH_Ctrl[21].addr[3] = 106;
1552         state->CH_Ctrl[21].bit[3] = 5;
1553         state->CH_Ctrl[21].val[3] = 0;
1554         state->CH_Ctrl[21].addr[4] = 106;
1555         state->CH_Ctrl[21].bit[4] = 6;
1556         state->CH_Ctrl[21].val[4] = 0;
1557         state->CH_Ctrl[21].addr[5] = 106;
1558         state->CH_Ctrl[21].bit[5] = 7;
1559         state->CH_Ctrl[21].val[5] = 1;
1560
1561         state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1562         state->CH_Ctrl[22].size = 1 ;
1563         state->CH_Ctrl[22].addr[0] = 138;
1564         state->CH_Ctrl[22].bit[0] = 4;
1565         state->CH_Ctrl[22].val[0] = 1;
1566
1567         state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1568         state->CH_Ctrl[23].size = 1 ;
1569         state->CH_Ctrl[23].addr[0] = 17;
1570         state->CH_Ctrl[23].bit[0] = 5;
1571         state->CH_Ctrl[23].val[0] = 0;
1572
1573         state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1574         state->CH_Ctrl[24].size = 1 ;
1575         state->CH_Ctrl[24].addr[0] = 111;
1576         state->CH_Ctrl[24].bit[0] = 3;
1577         state->CH_Ctrl[24].val[0] = 0;
1578
1579         state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1580         state->CH_Ctrl[25].size = 1 ;
1581         state->CH_Ctrl[25].addr[0] = 112;
1582         state->CH_Ctrl[25].bit[0] = 7;
1583         state->CH_Ctrl[25].val[0] = 0;
1584
1585         state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1586         state->CH_Ctrl[26].size = 1 ;
1587         state->CH_Ctrl[26].addr[0] = 136;
1588         state->CH_Ctrl[26].bit[0] = 7;
1589         state->CH_Ctrl[26].val[0] = 0;
1590
1591         state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1592         state->CH_Ctrl[27].size = 1 ;
1593         state->CH_Ctrl[27].addr[0] = 149;
1594         state->CH_Ctrl[27].bit[0] = 7;
1595         state->CH_Ctrl[27].val[0] = 0;
1596
1597         state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1598         state->CH_Ctrl[28].size = 1 ;
1599         state->CH_Ctrl[28].addr[0] = 149;
1600         state->CH_Ctrl[28].bit[0] = 6;
1601         state->CH_Ctrl[28].val[0] = 0;
1602
1603         state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1604         state->CH_Ctrl[29].size = 1 ;
1605         state->CH_Ctrl[29].addr[0] = 149;
1606         state->CH_Ctrl[29].bit[0] = 5;
1607         state->CH_Ctrl[29].val[0] = 1;
1608
1609         state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1610         state->CH_Ctrl[30].size = 1 ;
1611         state->CH_Ctrl[30].addr[0] = 149;
1612         state->CH_Ctrl[30].bit[0] = 4;
1613         state->CH_Ctrl[30].val[0] = 1;
1614
1615         state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1616         state->CH_Ctrl[31].size = 1 ;
1617         state->CH_Ctrl[31].addr[0] = 149;
1618         state->CH_Ctrl[31].bit[0] = 3;
1619         state->CH_Ctrl[31].val[0] = 0;
1620
1621         state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1622         state->CH_Ctrl[32].size = 1 ;
1623         state->CH_Ctrl[32].addr[0] = 93;
1624         state->CH_Ctrl[32].bit[0] = 1;
1625         state->CH_Ctrl[32].val[0] = 0;
1626
1627         state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1628         state->CH_Ctrl[33].size = 1 ;
1629         state->CH_Ctrl[33].addr[0] = 93;
1630         state->CH_Ctrl[33].bit[0] = 0;
1631         state->CH_Ctrl[33].val[0] = 0;
1632
1633         state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1634         state->CH_Ctrl[34].size = 6 ;
1635         state->CH_Ctrl[34].addr[0] = 92;
1636         state->CH_Ctrl[34].bit[0] = 2;
1637         state->CH_Ctrl[34].val[0] = 0;
1638         state->CH_Ctrl[34].addr[1] = 92;
1639         state->CH_Ctrl[34].bit[1] = 3;
1640         state->CH_Ctrl[34].val[1] = 0;
1641         state->CH_Ctrl[34].addr[2] = 92;
1642         state->CH_Ctrl[34].bit[2] = 4;
1643         state->CH_Ctrl[34].val[2] = 0;
1644         state->CH_Ctrl[34].addr[3] = 92;
1645         state->CH_Ctrl[34].bit[3] = 5;
1646         state->CH_Ctrl[34].val[3] = 0;
1647         state->CH_Ctrl[34].addr[4] = 92;
1648         state->CH_Ctrl[34].bit[4] = 6;
1649         state->CH_Ctrl[34].val[4] = 0;
1650         state->CH_Ctrl[34].addr[5] = 92;
1651         state->CH_Ctrl[34].bit[5] = 7;
1652         state->CH_Ctrl[34].val[5] = 0;
1653
1654         state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1655         state->CH_Ctrl[35].size = 6 ;
1656         state->CH_Ctrl[35].addr[0] = 93;
1657         state->CH_Ctrl[35].bit[0] = 2;
1658         state->CH_Ctrl[35].val[0] = 0;
1659         state->CH_Ctrl[35].addr[1] = 93;
1660         state->CH_Ctrl[35].bit[1] = 3;
1661         state->CH_Ctrl[35].val[1] = 0;
1662         state->CH_Ctrl[35].addr[2] = 93;
1663         state->CH_Ctrl[35].bit[2] = 4;
1664         state->CH_Ctrl[35].val[2] = 0;
1665         state->CH_Ctrl[35].addr[3] = 93;
1666         state->CH_Ctrl[35].bit[3] = 5;
1667         state->CH_Ctrl[35].val[3] = 0;
1668         state->CH_Ctrl[35].addr[4] = 93;
1669         state->CH_Ctrl[35].bit[4] = 6;
1670         state->CH_Ctrl[35].val[4] = 0;
1671         state->CH_Ctrl[35].addr[5] = 93;
1672         state->CH_Ctrl[35].bit[5] = 7;
1673         state->CH_Ctrl[35].val[5] = 0;
1674
1675 #ifdef _MXL_PRODUCTION
1676         state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1677         state->CH_Ctrl[36].size = 1 ;
1678         state->CH_Ctrl[36].addr[0] = 109;
1679         state->CH_Ctrl[36].bit[0] = 1;
1680         state->CH_Ctrl[36].val[0] = 1;
1681
1682         state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1683         state->CH_Ctrl[37].size = 2 ;
1684         state->CH_Ctrl[37].addr[0] = 112;
1685         state->CH_Ctrl[37].bit[0] = 5;
1686         state->CH_Ctrl[37].val[0] = 0;
1687         state->CH_Ctrl[37].addr[1] = 112;
1688         state->CH_Ctrl[37].bit[1] = 6;
1689         state->CH_Ctrl[37].val[1] = 0;
1690
1691         state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1692         state->CH_Ctrl[38].size = 1 ;
1693         state->CH_Ctrl[38].addr[0] = 65;
1694         state->CH_Ctrl[38].bit[0] = 1;
1695         state->CH_Ctrl[38].val[0] = 0;
1696 #endif
1697
1698         return 0 ;
1699 }
1700
1701 // MaxLinear source code - MXL5005_c.cpp
1702 // MXL5005.cpp : Defines the initialization routines for the DLL.
1703 // 2.6.12
1704 // DONE
1705 void InitTunerControls(struct dvb_frontend *fe)
1706 {
1707         MXL5005_RegisterInit(fe);
1708         MXL5005_ControlInit(fe);
1709 #ifdef _MXL_INTERNAL
1710         MXL5005_MXLControlInit(fe);
1711 #endif
1712 }
1713
1714 ///////////////////////////////////////////////////////////////////////////////
1715 //                                                                           //
1716 // Function:       MXL_ConfigTuner                                           //
1717 //                                                                           //
1718 // Description:    Configure MXL5005Tuner structure for desired              //
1719 //                 Channel Bandwidth/Channel Frequency                       //
1720 //                                                                           //
1721 //                                                                           //
1722 // Functions used:                                                           //
1723 //                 MXL_SynthIFLO_Calc                                        //
1724 //                                                                           //
1725 // Inputs:                                                                   //
1726 //                 Tuner_struct: structure defined at higher level           //
1727 //                 Mode:         Tuner Mode (Analog/Digital)                 //
1728 //                 IF_Mode:      IF Mode ( Zero/Low )                        //
1729 //                 Bandwidth:    Filter Channel Bandwidth (in Hz)            //
1730 //                 IF_out:       Desired IF out Frequency (in Hz)            //
1731 //                 Fxtal:        Crystal Frerquency (in Hz)                  //
1732 //                 TOP:          0: Dual AGC; Value: take over point         //
1733 //                 IF_OUT_LOAD:  IF out load resistor (200/300 Ohms)     //
1734 //                 CLOCK_OUT:    0: Turn off clock out; 1: turn on clock out //
1735 //                 DIV_OUT:      0: Div-1; 1: Div-4                      //
1736 //                 CAPSELECT:    0: Disable On-chip pulling cap; 1: Enable   //
1737 //                 EN_RSSI:      0: Disable RSSI; 1: Enable RSSI         //
1738 //                                                                           //
1739 // Outputs:                                                                  //
1740 //                 Tuner                                                     //
1741 //                                                                           //
1742 // Return:                                                                   //
1743 //                 0 : Successful                                            //
1744 //               > 0 : Failed                                                //
1745 //                                                                           //
1746 ///////////////////////////////////////////////////////////////////////////////
1747 // DONE
1748 u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1749                 u8      Mode,           /* 0: Analog Mode ; 1: Digital Mode */
1750                 u8      IF_mode,        /* for Analog Mode, 0: zero IF; 1: low IF */
1751                 u32     Bandwidth,      /* filter  channel bandwidth (6, 7, 8) */
1752                 u32     IF_out,         /* Desired IF Out Frequency */
1753                 u32     Fxtal,          /* XTAL Frequency */
1754                 u8      AGC_Mode,       /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1755                 u16     TOP,            /* 0: Dual AGC; Value: take over point */
1756                 u16     IF_OUT_LOAD,    /* IF Out Load Resistor (200 / 300 Ohms) */
1757                 u8      CLOCK_OUT,      /* 0: turn off clock out; 1: turn on clock out */
1758                 u8      DIV_OUT,        /* 0: Div-1; 1: Div-4 */
1759                 u8      CAPSELECT,      /* 0: disable On-Chip pulling cap; 1: enable */
1760                 u8      EN_RSSI,        /* 0: disable RSSI; 1: enable RSSI */
1761                 u8      Mod_Type,       /* Modulation Type; */
1762                                         /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1763                 u8      TF_Type         /* Tracking Filter */
1764                                         /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1765                 )
1766 {
1767         struct mxl5005s_state *state = fe->tuner_priv;
1768         u16 status = 0;
1769
1770         state->Mode = Mode;
1771         state->IF_Mode = IF_mode;
1772         state->Chan_Bandwidth = Bandwidth;
1773         state->IF_OUT = IF_out;
1774         state->Fxtal = Fxtal;
1775         state->AGC_Mode = AGC_Mode;
1776         state->TOP = TOP;
1777         state->IF_OUT_LOAD = IF_OUT_LOAD;
1778         state->CLOCK_OUT = CLOCK_OUT;
1779         state->DIV_OUT = DIV_OUT;
1780         state->CAPSELECT = CAPSELECT;
1781         state->EN_RSSI = EN_RSSI;
1782         state->Mod_Type = Mod_Type;
1783         state->TF_Type = TF_Type;
1784
1785         /* Initialize all the controls and registers */
1786         InitTunerControls(fe);
1787
1788         /* Synthesizer LO frequency calculation */
1789         MXL_SynthIFLO_Calc(fe);
1790
1791         return status;
1792 }
1793
1794 ///////////////////////////////////////////////////////////////////////////////
1795 //                                                                           //
1796 // Function:       MXL_SynthIFLO_Calc                                        //
1797 //                                                                           //
1798 // Description:    Calculate Internal IF-LO Frequency                        //
1799 //                                                                           //
1800 // Globals:                                                                  //
1801 //                 NONE                                                      //
1802 //                                                                           //
1803 // Functions used:                                                           //
1804 //                 NONE                                                      //
1805 //                                                                           //
1806 // Inputs:                                                                   //
1807 //                 Tuner_struct: structure defined at higher level           //
1808 //                                                                           //
1809 // Outputs:                                                                  //
1810 //                 Tuner                                                     //
1811 //                                                                           //
1812 // Return:                                                                   //
1813 //                 0 : Successful                                            //
1814 //               > 0 : Failed                                                //
1815 //                                                                           //
1816 ///////////////////////////////////////////////////////////////////////////////
1817 // DONE
1818 void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1819 {
1820         struct mxl5005s_state *state = fe->tuner_priv;
1821         if (state->Mode == 1) /* Digital Mode */
1822                 state->IF_LO = state->IF_OUT;
1823         else /* Analog Mode */
1824         {
1825                 if(state->IF_Mode == 0) /* Analog Zero IF mode */
1826                         state->IF_LO = state->IF_OUT + 400000;
1827                 else /* Analog Low IF mode */
1828                         state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1829         }
1830 }
1831
1832 ///////////////////////////////////////////////////////////////////////////////
1833 //                                                                           //
1834 // Function:       MXL_SynthRFTGLO_Calc                                      //
1835 //                                                                           //
1836 // Description:    Calculate Internal RF-LO frequency and                    //
1837 //                 internal Tone-Gen(TG)-LO frequency                        //
1838 //                                                                           //
1839 // Globals:                                                                  //
1840 //                 NONE                                                      //
1841 //                                                                           //
1842 // Functions used:                                                           //
1843 //                 NONE                                                      //
1844 //                                                                           //
1845 // Inputs:                                                                   //
1846 //                 Tuner_struct: structure defined at higher level           //
1847 //                                                                           //
1848 // Outputs:                                                                  //
1849 //                 Tuner                                                     //
1850 //                                                                           //
1851 // Return:                                                                   //
1852 //                 0 : Successful                                            //
1853 //               > 0 : Failed                                                //
1854 //                                                                           //
1855 ///////////////////////////////////////////////////////////////////////////////
1856 // DONE
1857 void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1858 {
1859         struct mxl5005s_state *state = fe->tuner_priv;
1860
1861         if (state->Mode == 1) /* Digital Mode */ {
1862                         //remove 20.48MHz setting for 2.6.10
1863                         state->RF_LO = state->RF_IN;
1864                         state->TG_LO = state->RF_IN - 750000;  //change for 2.6.6
1865         } else /* Analog Mode */ {
1866                 if(state->IF_Mode == 0) /* Analog Zero IF mode */ {
1867                         state->RF_LO = state->RF_IN - 400000;
1868                         state->TG_LO = state->RF_IN - 1750000;
1869                 } else /* Analog Low IF mode */ {
1870                         state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1871                         state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000;
1872                 }
1873         }
1874 }
1875
1876 ///////////////////////////////////////////////////////////////////////////////
1877 //                                                                           //
1878 // Function:       MXL_OverwriteICDefault                                    //
1879 //                                                                           //
1880 // Description:    Overwrite the Default Register Setting                    //
1881 //                                                                           //
1882 //                                                                           //
1883 // Functions used:                                                           //
1884 //                                                                           //
1885 // Inputs:                                                                   //
1886 //                 Tuner_struct: structure defined at higher level           //
1887 // Outputs:                                                                  //
1888 //                 Tuner                                                     //
1889 //                                                                           //
1890 // Return:                                                                   //
1891 //                 0 : Successful                                            //
1892 //               > 0 : Failed                                                //
1893 //                                                                           //
1894 ///////////////////////////////////////////////////////////////////////////////
1895 // DONE
1896 u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1897 {
1898         u16 status = 0;
1899
1900         status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1901         status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1902         status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1903         status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1904
1905         return status;
1906 }
1907
1908 ///////////////////////////////////////////////////////////////////////////////
1909 //                                                                           //
1910 // Function:       MXL_BlockInit                                             //
1911 //                                                                           //
1912 // Description:    Tuner Initialization as a function of 'User Settings'     //
1913 //                  * User settings in Tuner strcuture must be assigned      //
1914 //                    first                                                  //
1915 //                                                                           //
1916 // Globals:                                                                  //
1917 //                 NONE                                                      //
1918 //                                                                           //
1919 // Functions used:                                                           //
1920 //                 Tuner_struct: structure defined at higher level           //
1921 //                                                                           //
1922 // Inputs:                                                                   //
1923 //                 Tuner       : Tuner structure defined at higher level     //
1924 //                                                                           //
1925 // Outputs:                                                                  //
1926 //                 Tuner                                                     //
1927 //                                                                           //
1928 // Return:                                                                   //
1929 //                 0 : Successful                                            //
1930 //               > 0 : Failed                                                //
1931 //                                                                           //
1932 ///////////////////////////////////////////////////////////////////////////////
1933 // DONE
1934 u16 MXL_BlockInit(struct dvb_frontend *fe)
1935 {
1936         struct mxl5005s_state *state = fe->tuner_priv;
1937         u16 status = 0;
1938
1939         status += MXL_OverwriteICDefault(fe);
1940
1941         /* Downconverter Control Dig Ana */
1942         status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1943
1944         /* Filter Control  Dig  Ana */
1945         status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1946         status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1947         status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1948         status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1949         status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1950
1951         /* Initialize Low-Pass Filter */
1952         if (state->Mode) { /* Digital Mode */
1953                 switch (state->Chan_Bandwidth) {
1954                         case 8000000:
1955                                 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1956                                 break;
1957                         case 7000000:
1958                                 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1959                                 break;
1960                         case 6000000:
1961                                 printk("%s() doing 6MHz digital\n", __func__);
1962                                 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
1963                                 break;
1964                 }
1965         } else { /* Analog Mode */
1966                 switch (state->Chan_Bandwidth) {
1967                         case 8000000:   /* Low Zero */
1968                                 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3));
1969                                 break;
1970                         case 7000000:
1971                                 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4));
1972                                 break;
1973                         case 6000000:
1974                                 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5));
1975                                 break;
1976                 }
1977         }
1978
1979         /* Charge Pump Control Dig  Ana */
1980         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,      state->Mode ? 5 : 8);
1981         status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1982         status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1983
1984         /* AGC TOP Control */
1985         if (state->AGC_Mode == 0) /* Dual AGC */ {
1986                 status += MXL_ControlWrite(fe, AGC_IF, 15);
1987                 status += MXL_ControlWrite(fe, AGC_RF, 15);
1988         }
1989         else /*  Single AGC Mode Dig  Ana */
1990                 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1991
1992         if (state->TOP == 55) /* TOP == 5.5 */
1993                 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1994
1995         if (state->TOP == 72) /* TOP == 7.2 */
1996                 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1997
1998         if (state->TOP == 92) /* TOP == 9.2 */
1999                 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
2000
2001         if (state->TOP == 110) /* TOP == 11.0 */
2002                 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
2003
2004         if (state->TOP == 129) /* TOP == 12.9 */
2005                 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
2006
2007         if (state->TOP == 147) /* TOP == 14.7 */
2008                 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
2009
2010         if (state->TOP == 168) /* TOP == 16.8 */
2011                 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
2012
2013         if (state->TOP == 194) /* TOP == 19.4 */
2014                 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
2015
2016         if (state->TOP == 212) /* TOP == 21.2 */
2017                 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
2018
2019         if (state->TOP == 232) /* TOP == 23.2 */
2020                 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
2021
2022         if (state->TOP == 252) /* TOP == 25.2 */
2023                 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
2024
2025         if (state->TOP == 271) /* TOP == 27.1 */
2026                 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
2027
2028         if (state->TOP == 292) /* TOP == 29.2 */
2029                 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
2030
2031         if (state->TOP == 317) /* TOP == 31.7 */
2032                 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
2033
2034         if (state->TOP == 349) /* TOP == 34.9 */
2035                 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
2036
2037         /* IF Synthesizer Control */
2038         status += MXL_IFSynthInit(fe);
2039
2040         /* IF UpConverter Control */
2041         if (state->IF_OUT_LOAD == 200) {
2042                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
2043                 status += MXL_ControlWrite(fe, I_DRIVER, 2);
2044         }
2045         if (state->IF_OUT_LOAD == 300) {
2046                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
2047                 status += MXL_ControlWrite(fe, I_DRIVER, 1);
2048         }
2049
2050         /* Anti-Alias Filtering Control
2051          * initialise Anti-Aliasing Filter
2052          */
2053         if (state->Mode) { /* Digital Mode */
2054                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
2055                         status += MXL_ControlWrite(fe, EN_AAF, 1);
2056                         status += MXL_ControlWrite(fe, EN_3P, 1);
2057                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2058                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2059                 }
2060                 if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) {
2061                         status += MXL_ControlWrite(fe, EN_AAF, 1);
2062                         status += MXL_ControlWrite(fe, EN_3P, 1);
2063                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2064                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2065                 }
2066                 if (state->IF_OUT > 36150000UL) {
2067                         status += MXL_ControlWrite(fe, EN_AAF, 0);
2068                         status += MXL_ControlWrite(fe, EN_3P, 1);
2069                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2070                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2071                 }
2072         } else { /* Analog Mode */
2073                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL)
2074                 {
2075                         status += MXL_ControlWrite(fe, EN_AAF, 1);
2076                         status += MXL_ControlWrite(fe, EN_3P, 1);
2077                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2078                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2079                 }
2080                 if (state->IF_OUT > 5000000UL)
2081                 {
2082                         status += MXL_ControlWrite(fe, EN_AAF, 0);
2083                         status += MXL_ControlWrite(fe, EN_3P, 0);
2084                         status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
2085                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2086                 }
2087         }
2088
2089         /* Demod Clock Out */
2090         if (state->CLOCK_OUT)
2091                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
2092         else
2093                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
2094
2095         if (state->DIV_OUT == 1)
2096                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
2097         if (state->DIV_OUT == 0)
2098                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
2099
2100         /* Crystal Control */
2101         if (state->CAPSELECT)
2102                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
2103         else
2104                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
2105
2106         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2107                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
2108         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2109                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
2110
2111         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2112                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
2113         if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
2114                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
2115
2116         /* Misc Controls */
2117         if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
2118                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
2119         else
2120                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
2121
2122         /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
2123
2124         /* Set TG_R_DIV */
2125         status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000));
2126
2127         /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
2128
2129         /* RSSI Control */
2130         if (state->EN_RSSI)
2131         {
2132                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2133                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2134                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2135                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2136
2137                 /* RSSI reference point */
2138                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2139                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
2140                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2141
2142                 /* TOP point */
2143                 status += MXL_ControlWrite(fe, RFA_FLR, 0);
2144                 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
2145         }
2146
2147         /* Modulation type bit settings
2148          * Override the control values preset
2149          */
2150         if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */
2151         {
2152                 state->AGC_Mode = 1; /* Single AGC Mode */
2153
2154                 /* Enable RSSI */
2155                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2156                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2157                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2158                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2159
2160                 /* RSSI reference point */
2161                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2162                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2163                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2164
2165                 /* TOP point */
2166                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2167                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2168                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2169                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2170                 else /* High IF */
2171                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2172
2173         }
2174         if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */
2175         {
2176                 state->AGC_Mode = 1;    /* Single AGC Mode */
2177
2178                 /* Enable RSSI */
2179                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2180                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2181                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2182                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2183
2184                 /* RSSI reference point */
2185                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2186                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2187                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2188
2189                 /* TOP point */
2190                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2191                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2192                 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2193                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */
2194                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2195                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2196                 else /* High IF */
2197                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2198         }
2199         if (state->Mod_Type == MXL_QAM) /* QAM Mode */
2200         {
2201                 state->Mode = MXL_DIGITAL_MODE;
2202
2203                 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2204
2205                 /* Disable RSSI */      /* change here for v2.6.5 */
2206                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2207                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2208                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2209                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2210
2211                 /* RSSI reference point */
2212                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2213                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2214                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2215                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);      /* change here for v2.6.5 */
2216
2217                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2218                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2219                 else /* High IF */
2220                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2221                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2222
2223         }
2224         if (state->Mod_Type == MXL_ANALOG_CABLE) {
2225                 /* Analog Cable Mode */
2226                 /* state->Mode = MXL_DIGITAL_MODE; */
2227
2228                 state->AGC_Mode = 1; /* Single AGC Mode */
2229
2230                 /* Disable RSSI */
2231                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2232                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2233                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2234                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2235                 status += MXL_ControlWrite(fe, AGC_IF, 1);  /* change for 2.6.3 */
2236                 status += MXL_ControlWrite(fe, AGC_RF, 15);
2237                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2238         }
2239
2240         if (state->Mod_Type == MXL_ANALOG_OTA) {
2241                 /* Analog OTA Terrestrial mode add for 2.6.7 */
2242                 /* state->Mode = MXL_ANALOG_MODE; */
2243
2244                 /* Enable RSSI */
2245                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2246                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2247                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2248                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2249
2250                 /* RSSI reference point */
2251                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2252                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2253                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2254                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2255                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2256         }
2257
2258         /* RSSI disable */
2259         if(state->EN_RSSI == 0) {
2260                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2261                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2262                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2263                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2264         }
2265
2266         return status;
2267 }
2268
2269 ///////////////////////////////////////////////////////////////////////////////
2270 //                                                                           //
2271 // Function:       MXL_IFSynthInit                                           //
2272 //                                                                           //
2273 // Description:    Tuner IF Synthesizer related register initialization      //
2274 //                                                                           //
2275 // Globals:                                                                  //
2276 //                 NONE                                                      //
2277 //                                                                           //
2278 // Functions used:                                                           //
2279 //                 Tuner_struct: structure defined at higher level           //
2280 //                                                                           //
2281 // Inputs:                                                                   //
2282 //                 Tuner       : Tuner structure defined at higher level     //
2283 //                                                                           //
2284 // Outputs:                                                                  //
2285 //                 Tuner                                                     //
2286 //                                                                           //
2287 // Return:                                                                   //
2288 //                 0 : Successful                                            //
2289 //               > 0 : Failed                                                //
2290 //                                                                           //
2291 ///////////////////////////////////////////////////////////////////////////////
2292 u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2293 {
2294         struct mxl5005s_state *state = fe->tuner_priv;
2295         u16 status = 0 ;
2296         // Declare Local Variables
2297         u32     Fref = 0 ;
2298         u32     Kdbl, intModVal ;
2299         u32     fracModVal ;
2300         Kdbl = 2 ;
2301
2302         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2303                 Kdbl = 2 ;
2304         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2305                 Kdbl = 1 ;
2306
2307         //
2308         // IF Synthesizer Control
2309         //
2310         if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
2311         {
2312                 if (state->IF_LO == 41000000UL) {
2313                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2314                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2315                         Fref = 328000000UL ;
2316                 }
2317                 if (state->IF_LO == 47000000UL) {
2318                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2319                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2320                         Fref = 376000000UL ;
2321                 }
2322                 if (state->IF_LO == 54000000UL) {
2323                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
2324                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2325                         Fref = 324000000UL ;
2326                 }
2327                 if (state->IF_LO == 60000000UL) {
2328                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
2329                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2330                         Fref = 360000000UL ;
2331                 }
2332                 if (state->IF_LO == 39250000UL) {
2333                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2334                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2335                         Fref = 314000000UL ;
2336                 }
2337                 if (state->IF_LO == 39650000UL) {
2338                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2339                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2340                         Fref = 317200000UL ;
2341                 }
2342                 if (state->IF_LO == 40150000UL) {
2343                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2344                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2345                         Fref = 321200000UL ;
2346                 }
2347                 if (state->IF_LO == 40650000UL) {
2348                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2349                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2350                         Fref = 325200000UL ;
2351                 }
2352         }
2353
2354         if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0))
2355         {
2356                 if (state->IF_LO == 57000000UL) {
2357                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
2358                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2359                         Fref = 342000000UL ;
2360                 }
2361                 if (state->IF_LO == 44000000UL) {
2362                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2363                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2364                         Fref = 352000000UL ;
2365                 }
2366                 if (state->IF_LO == 43750000UL) {
2367                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2368                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2369                         Fref = 350000000UL ;
2370                 }
2371                 if (state->IF_LO == 36650000UL) {
2372                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2373                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2374                         Fref = 366500000UL ;
2375                 }
2376                 if (state->IF_LO == 36150000UL) {
2377                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2378                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2379                         Fref = 361500000UL ;
2380                 }
2381                 if (state->IF_LO == 36000000UL) {
2382                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2383                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2384                         Fref = 360000000UL ;
2385                 }
2386                 if (state->IF_LO == 35250000UL) {
2387                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2388                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2389                         Fref = 352500000UL ;
2390                 }
2391                 if (state->IF_LO == 34750000UL) {
2392                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2393                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2394                         Fref = 347500000UL ;
2395                 }
2396                 if (state->IF_LO == 6280000UL) {
2397                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07) ;
2398                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2399                         Fref = 376800000UL ;
2400                 }
2401                 if (state->IF_LO == 5000000UL) {
2402                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09) ;
2403                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2404                         Fref = 360000000UL ;
2405                 }
2406                 if (state->IF_LO == 4500000UL) {
2407                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06) ;
2408                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2409                         Fref = 360000000UL ;
2410                 }
2411                 if (state->IF_LO == 4570000UL) {
2412                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06) ;
2413                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2414                         Fref = 365600000UL ;
2415                 }
2416                 if (state->IF_LO == 4000000UL) {
2417                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05) ;
2418                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2419                         Fref = 360000000UL ;
2420                 }
2421                 if (state->IF_LO == 57400000UL)
2422                 {
2423                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10) ;
2424                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2425                         Fref = 344400000UL ;
2426                 }
2427                 if (state->IF_LO == 44400000UL)
2428                 {
2429                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2430                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2431                         Fref = 355200000UL ;
2432                 }
2433                 if (state->IF_LO == 44150000UL)
2434                 {
2435                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08) ;
2436                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2437                         Fref = 353200000UL ;
2438                 }
2439                 if (state->IF_LO == 37050000UL)
2440                 {
2441                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2442                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2443                         Fref = 370500000UL ;
2444                 }
2445                 if (state->IF_LO == 36550000UL)
2446                 {
2447                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2448                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2449                         Fref = 365500000UL ;
2450                 }
2451                 if (state->IF_LO == 36125000UL) {
2452                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04) ;
2453                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2454                         Fref = 361250000UL ;
2455                 }
2456                 if (state->IF_LO == 6000000UL) {
2457                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07) ;
2458                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2459                         Fref = 360000000UL ;
2460                 }
2461                 if (state->IF_LO == 5400000UL)
2462                 {
2463                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07) ;
2464                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2465                         Fref = 324000000UL ;
2466                 }
2467                 if (state->IF_LO == 5380000UL) {
2468                         printk("%s() doing 5.38\n", __func__);
2469                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07) ;
2470                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2471                         Fref = 322800000UL ;
2472                 }
2473                 if (state->IF_LO == 5200000UL) {
2474                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09) ;
2475                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2476                         Fref = 374400000UL ;
2477                 }
2478                 if (state->IF_LO == 4900000UL)
2479                 {
2480                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09) ;
2481                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2482                         Fref = 352800000UL ;
2483                 }
2484                 if (state->IF_LO == 4400000UL)
2485                 {
2486                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06) ;
2487                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2488                         Fref = 352000000UL ;
2489                 }
2490                 if (state->IF_LO == 4063000UL)  //add for 2.6.8
2491                 {
2492                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05) ;
2493                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2494                         Fref = 365670000UL ;
2495                 }
2496         }
2497         // CHCAL_INT_MOD_IF
2498         // CHCAL_FRAC_MOD_IF
2499         intModVal = Fref / (state->Fxtal * Kdbl/2) ;
2500         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ;
2501
2502         fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal);
2503         fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ;
2504         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ;
2505
2506         return status ;
2507 }
2508
2509 ///////////////////////////////////////////////////////////////////////////////
2510 //                                                                           //
2511 // Function:       MXL_GetXtalInt                                            //
2512 //                                                                           //
2513 // Description:    return the Crystal Integration Value for                  //
2514 //                                 TG_VCO_BIAS calculation               //
2515 //                                                                           //
2516 // Globals:                                                                  //
2517 //                 NONE                                                      //
2518 //                                                                           //
2519 // Functions used:                                                           //
2520 //                 NONE                                                      //
2521 //                                                                           //
2522 // Inputs:                                                                   //
2523 //                 Crystal Frequency Value in Hz                                                     //
2524 //                                                                           //
2525 // Outputs:                                                                  //
2526 //                 Calculated Crystal Frequency Integration Value            //
2527 //                                                                           //
2528 // Return:                                                                   //
2529 //                 0 : Successful                                            //
2530 //               > 0 : Failed                                                //
2531 //                                                                           //
2532 ///////////////////////////////////////////////////////////////////////////////
2533 u32 MXL_GetXtalInt(u32 Xtal_Freq)
2534 {
2535         if ((Xtal_Freq % 1000000) == 0)
2536                 return (Xtal_Freq / 10000) ;
2537         else
2538                 return (((Xtal_Freq / 1000000) + 1)*100) ;
2539 }
2540
2541 ///////////////////////////////////////////////////////////////////////////////
2542 //                                                                           //
2543 // Function:       MXL5005_TuneRF                                            //
2544 //                                                                           //
2545 // Description:    Set control names to tune to requested RF_IN frequency    //
2546 //                                                                           //
2547 // Globals:                                                                  //
2548 //                 None                                                      //
2549 //                                                                           //
2550 // Functions used:                                                           //
2551 //                 MXL_SynthRFTGLO_Calc                                      //
2552 //                 MXL5005_ControlWrite                                      //
2553 //                 MXL_GetXtalInt                                            //
2554 //                                                                           //
2555 // Inputs:                                                                   //
2556 //                 Tuner       : Tuner structure defined at higher level     //
2557 //                                                                           //
2558 // Outputs:                                                                  //
2559 //                 Tuner                                                     //
2560 //                                                                           //
2561 // Return:                                                                   //
2562 //                 0 : Successful                                            //
2563 //                 1 : Unsuccessful                                          //
2564 ///////////////////////////////////////////////////////////////////////////////
2565 u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2566 {
2567         struct mxl5005s_state *state = fe->tuner_priv;
2568         // Declare Local Variables
2569         u16 status = 0;
2570         u32 divider_val, E3, E4, E5, E5A;
2571         u32 Fmax, Fmin, FmaxBin, FminBin;
2572         u32 Kdbl_RF = 2;
2573         u32 tg_divval;
2574         u32 tg_lo;
2575         u32 Xtal_Int;
2576
2577         u32 Fref_TG;
2578         u32 Fvco;
2579 //      u32 temp;
2580
2581
2582         Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2583
2584         state->RF_IN = RF_Freq;
2585
2586         MXL_SynthRFTGLO_Calc(fe);
2587
2588         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2589                 Kdbl_RF = 2;
2590         if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2591                 Kdbl_RF = 1;
2592
2593         //
2594         // Downconverter Controls
2595         //
2596         // Look-Up Table Implementation for:
2597         //      DN_POLY
2598         //      DN_RFGAIN
2599         //      DN_CAP_RFLPF
2600         //      DN_EN_VHFUHFBAR
2601         //      DN_GAIN_ADJUST
2602         // Change the boundary reference from RF_IN to RF_LO
2603         if (state->RF_LO < 40000000UL) {
2604                 return -1;
2605         }
2606         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2607                 // Look-Up Table implementation
2608                 status += MXL_ControlWrite(fe, DN_POLY,              2);
2609                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2610                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         423);
2611                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2612                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2613         }
2614         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2615                 // Look-Up Table implementation
2616                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2617                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2618                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         222);
2619                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2620                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2621         }
2622         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2623                 // Look-Up Table implementation
2624                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2625                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2626                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         147);
2627                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2628                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2629         }
2630         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2631                 // Look-Up Table implementation
2632                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2633                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2634                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         9);
2635                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2636                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2637         }
2638         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2639                 // Look-Up Table implementation
2640                 status += MXL_ControlWrite(fe, DN_POLY,              3) ;
2641                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3) ;
2642                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0) ;
2643                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1) ;
2644                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3) ;
2645         }
2646         if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2647                 // Look-Up Table implementation
2648                 status += MXL_ControlWrite(fe, DN_POLY,              3) ;
2649                 status += MXL_ControlWrite(fe, DN_RFGAIN,            1) ;
2650                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0) ;
2651                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0) ;
2652                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3) ;
2653         }
2654         if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2655                 // Look-Up Table implementation
2656                 status += MXL_ControlWrite(fe, DN_POLY,              3) ;
2657                 status += MXL_ControlWrite(fe, DN_RFGAIN,            2) ;
2658                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0) ;
2659                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0) ;
2660                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3) ;
2661         }
2662         if (state->RF_LO > 900000000UL) {
2663                 return -1;
2664         }
2665         //      DN_IQTNBUF_AMP
2666         //      DN_IQTNGNBFBIAS_BST
2667         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2668                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2669                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2670         }
2671         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2672                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2673                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2674         }
2675         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2676                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2677                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2678         }
2679         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2680                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2681                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2682         }
2683         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2684                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2685                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2686         }
2687         if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2688                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2689                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2690         }
2691         if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2692                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2693                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2694         }
2695         if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2696                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2697                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2698         }
2699         if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2700                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2701                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2702         }
2703         if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2704                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2705                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2706         }
2707         if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2708                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2709                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2710         }
2711         if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2712                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2713                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2714         }
2715         if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2716                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2717                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2718         }
2719         if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2720                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2721                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2722         }
2723         if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2724                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2725                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2726         }
2727         if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2728                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2729                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2730         }
2731
2732         //
2733         // Set RF Synth and LO Path Control
2734         //
2735         // Look-Up table implementation for:
2736         //      RFSYN_EN_OUTMUX
2737         //      RFSYN_SEL_VCO_OUT
2738         //      RFSYN_SEL_VCO_HI
2739         //  RFSYN_SEL_DIVM
2740         //      RFSYN_RF_DIV_BIAS
2741         //      DN_SEL_FREQ
2742         //
2743         // Set divider_val, Fmax, Fmix to use in Equations
2744         FminBin = 28000000UL ;
2745         FmaxBin = 42500000UL ;
2746         if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2747                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2748                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2749                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2750                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2751                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2752                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2753                 divider_val = 64 ;
2754                 Fmax = FmaxBin ;
2755                 Fmin = FminBin ;
2756         }
2757         FminBin = 42500000UL ;
2758         FmaxBin = 56000000UL ;
2759         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2760                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2761                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2762                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2763                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2764                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2765                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2766                 divider_val = 64 ;
2767                 Fmax = FmaxBin ;
2768                 Fmin = FminBin ;
2769         }
2770         FminBin = 56000000UL ;
2771         FmaxBin = 85000000UL ;
2772         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2773                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2774                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2775                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0) ;
2776                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2777                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2778                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1) ;
2779                 divider_val = 32 ;
2780                 Fmax = FmaxBin ;
2781                 Fmin = FminBin ;
2782         }
2783         FminBin = 85000000UL ;
2784         FmaxBin = 112000000UL ;
2785         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2786                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2787                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2788                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1) ;
2789                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2790                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2791                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1) ;
2792                 divider_val = 32 ;
2793                 Fmax = FmaxBin ;
2794                 Fmin = FminBin ;
2795         }
2796         FminBin = 112000000UL ;
2797         FmaxBin = 170000000UL ;
2798         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2799                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2800                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2801                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0) ;
2802                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2803                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2804                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2) ;
2805                 divider_val = 16 ;
2806                 Fmax = FmaxBin ;
2807                 Fmin = FminBin ;
2808         }
2809         FminBin = 170000000UL ;
2810         FmaxBin = 225000000UL ;
2811         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2812                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2813                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2814                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1) ;
2815                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2816                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2817                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2) ;
2818                 divider_val = 16 ;
2819                 Fmax = FmaxBin ;
2820                 Fmin = FminBin ;
2821         }
2822         FminBin = 225000000UL ;
2823         FmaxBin = 300000000UL ;
2824         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2825                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2826                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2827                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0) ;
2828                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2829                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2830                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         4) ;
2831                 divider_val = 8 ;
2832                 Fmax = 340000000UL ;
2833                 Fmin = FminBin ;
2834         }
2835         FminBin = 300000000UL ;
2836         FmaxBin = 340000000UL ;
2837         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2838                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1) ;
2839                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0) ;
2840                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0) ;
2841                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2842                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2843                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0) ;
2844                 divider_val = 8 ;
2845                 Fmax = FmaxBin ;
2846                 Fmin = 225000000UL ;
2847         }
2848         FminBin = 340000000UL ;
2849         FmaxBin = 450000000UL ;
2850         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2851                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1) ;
2852                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0) ;
2853                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1) ;
2854                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0) ;
2855                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   2) ;
2856                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0) ;
2857                 divider_val = 8 ;
2858                 Fmax = FmaxBin ;
2859                 Fmin = FminBin ;
2860         }
2861         FminBin = 450000000UL ;
2862         FmaxBin = 680000000UL ;
2863         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2864                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2865                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2866                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0) ;
2867                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1) ;
2868                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2869                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0) ;
2870                 divider_val = 4 ;
2871                 Fmax = FmaxBin ;
2872                 Fmin = FminBin ;
2873         }
2874         FminBin = 680000000UL ;
2875         FmaxBin = 900000000UL ;
2876         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2877                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0) ;
2878                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1) ;
2879                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1) ;
2880                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1) ;
2881                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1) ;
2882                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0) ;
2883                 divider_val = 4 ;
2884                 Fmax = FmaxBin ;
2885                 Fmin = FminBin ;
2886         }
2887
2888         //      CHCAL_INT_MOD_RF
2889         //      CHCAL_FRAC_MOD_RF
2890         //      RFSYN_LPF_R
2891         //      CHCAL_EN_INT_RF
2892
2893         // Equation E3
2894         //      RFSYN_VCO_BIAS
2895         E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2896         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ;
2897
2898         // Equation E4
2899         //      CHCAL_INT_MOD_RF
2900         E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ;
2901         MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ;
2902
2903         // Equation E5
2904         //      CHCAL_FRAC_MOD_RF
2905         //  CHCAL_EN_INT_RF
2906         E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ;
2907         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
2908
2909         // Equation E5A
2910         //  RFSYN_LPF_R
2911         E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2912         status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ;
2913
2914         // Euqation E5B
2915         //      CHCAL_EN_INIT_RF
2916         status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2917         //if (E5 == 0)
2918         //      status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2919         //else
2920         //      status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
2921
2922         //
2923         // Set TG Synth
2924         //
2925         // Look-Up table implementation for:
2926         //      TG_LO_DIVVAL
2927         //      TG_LO_SELVAL
2928         //
2929         // Set divider_val, Fmax, Fmix to use in Equations
2930         if (state->TG_LO < 33000000UL) {
2931                 return -1;
2932         }
2933         FminBin = 33000000UL ;
2934         FmaxBin = 50000000UL ;
2935         if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2936                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x6) ;
2937                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0) ;
2938                 divider_val = 36 ;
2939                 Fmax = FmaxBin ;
2940                 Fmin = FminBin ;
2941         }
2942         FminBin = 50000000UL ;
2943         FmaxBin = 67000000UL ;
2944         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2945                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x1) ;
2946                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0) ;
2947                 divider_val = 24 ;
2948                 Fmax = FmaxBin ;
2949                 Fmin = FminBin ;
2950         }
2951         FminBin = 67000000UL ;
2952         FmaxBin = 100000000UL ;
2953         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2954                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0xC) ;
2955                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2) ;
2956                 divider_val = 18 ;
2957                 Fmax = FmaxBin ;
2958                 Fmin = FminBin ;
2959         }
2960         FminBin = 100000000UL ;
2961         FmaxBin = 150000000UL ;
2962         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2963                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8) ;
2964                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2) ;
2965                 divider_val = 12 ;
2966                 Fmax = FmaxBin ;
2967                 Fmin = FminBin ;
2968         }
2969         FminBin = 150000000UL ;
2970         FmaxBin = 200000000UL ;
2971         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2972                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0) ;
2973                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2) ;
2974                 divider_val = 8 ;
2975                 Fmax = FmaxBin ;
2976                 Fmin = FminBin ;
2977         }
2978         FminBin = 200000000UL ;
2979         FmaxBin = 300000000UL ;
2980         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2981                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8) ;
2982                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3) ;
2983                 divider_val = 6 ;
2984                 Fmax = FmaxBin ;
2985                 Fmin = FminBin ;
2986         }
2987         FminBin = 300000000UL ;
2988         FmaxBin = 400000000UL ;
2989         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2990                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0) ;
2991                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3) ;
2992                 divider_val = 4 ;
2993                 Fmax = FmaxBin ;
2994                 Fmin = FminBin ;
2995         }
2996         FminBin = 400000000UL ;
2997         FmaxBin = 600000000UL ;
2998         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2999                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8) ;
3000                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7) ;
3001                 divider_val = 3 ;
3002                 Fmax = FmaxBin ;
3003                 Fmin = FminBin ;
3004         }
3005         FminBin = 600000000UL ;
3006         FmaxBin = 900000000UL ;
3007         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3008                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0) ;
3009                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7) ;
3010                 divider_val = 2 ;
3011                 Fmax = FmaxBin ;
3012                 Fmin = FminBin ;
3013         }
3014
3015         // TG_DIV_VAL
3016         tg_divval = (state->TG_LO*divider_val/100000)
3017                          *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ;
3018         status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ;
3019
3020         if (state->TG_LO > 600000000UL)
3021                 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ;
3022
3023         Fmax = 1800000000UL ;
3024         Fmin = 1200000000UL ;
3025
3026
3027
3028         // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
3029         Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
3030
3031         Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;  //Fvco = Fvco/10
3032
3033         tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
3034
3035         //below equation is same as above but much harder to debug.
3036         //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
3037
3038
3039         status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ;
3040
3041
3042
3043         //add for 2.6.5
3044         //Special setting for QAM
3045         if(state->Mod_Type == MXL_QAM)
3046         {
3047         if(state->RF_IN < 680000000)
3048                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
3049         else
3050                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ;
3051         }
3052
3053
3054         //remove 20.48MHz setting for 2.6.10
3055
3056         //
3057         // Off Chip Tracking Filter Control
3058         //
3059         if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
3060         {
3061                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3062                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
3063
3064                 status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1
3065                 status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2
3066                 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3
3067         }
3068
3069         if (state->TF_Type == MXL_TF_C) // Tracking Filter type C
3070         {
3071                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ;
3072                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3073
3074                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
3075                 {
3076
3077                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3078                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3079                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On
3080                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3081                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3082                 }
3083                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
3084                 {
3085                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3086                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3087                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3088                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3089                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3090                 }
3091                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
3092                 {
3093                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3094                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3095                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3096                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3097                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
3098                 }
3099                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
3100                 {
3101                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3102                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3103                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3104                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3105                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
3106                 }
3107                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
3108                 {
3109                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3110                         status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ;
3111                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3112                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3113                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
3114                 }
3115                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
3116                 {
3117                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3118                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3119                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3120                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3121                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
3122                 }
3123                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
3124                 {
3125                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3126                         status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ;
3127                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3128                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3129                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3130                 }
3131                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
3132                 {
3133                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3134                         status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ;
3135                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3136                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3137                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3138                 }
3139                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
3140                 {
3141                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3142                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3143                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3144                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3145                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3146                 }
3147         }
3148
3149         if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
3150         {
3151                 printk("%s() CH filter\n", __func__);
3152                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3153
3154                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
3155                 {
3156
3157                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3158                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3159                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3160                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3161                 }
3162                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
3163                 {
3164                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3165                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3166                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3167                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3168                 }
3169                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
3170                 {
3171                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3172                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3173                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3174                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
3175                 }
3176                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
3177                 {
3178                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3179                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3180                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3181                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
3182                 }
3183                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
3184                 {
3185                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3186                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3187                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3188                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
3189                 }
3190                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
3191                 {
3192                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3193                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3194                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3195                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
3196                 }
3197                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
3198                 {
3199                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3200                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3201                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3202                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3203                 }
3204                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
3205                 {
3206                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3207                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3208                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3209                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3210                 }
3211                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
3212                 {
3213                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3214                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3215                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3216                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3217                 }
3218         }
3219
3220         if (state->TF_Type == MXL_TF_D) // Tracking Filter type D
3221         {
3222                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3223
3224                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
3225                 {
3226
3227                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3228                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3229                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3230                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3231                 }
3232                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
3233                 {
3234                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3235                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3236                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3237                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3238                 }
3239                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
3240                 {
3241                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3242                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3243                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3244                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3245                 }
3246                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
3247                 {
3248                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3249                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3250                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3251                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3252                 }
3253                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
3254                 {
3255                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3256                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3257                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3258                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3259                 }
3260                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
3261                 {
3262                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3263                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3264                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3265                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3266                 }
3267                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
3268                 {
3269                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3270                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3271                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3272                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3273                 }
3274         }
3275
3276
3277         if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY  change for 2.6.3
3278         {
3279                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3280
3281                 // if UHF and terrestrial => Turn off Tracking Filter
3282                 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
3283                 {
3284                         // Turn off all the banks
3285                         status += MXL_SetGPIO(fe, 3, 1) ;
3286                         status += MXL_SetGPIO(fe, 1, 1) ;
3287                         status += MXL_SetGPIO(fe, 4, 1) ;
3288                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3289
3290                         status += MXL_ControlWrite(fe, AGC_IF, 10) ;
3291                 }
3292
3293                 else  // if VHF or cable => Turn on Tracking Filter
3294                 {
3295                         if (state->RF_IN >= 43000000 && state->RF_IN < 140000000)
3296                         {
3297
3298                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3299                                 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3300                                 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3301                                 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
3302                         }
3303                         if (state->RF_IN >= 140000000 && state->RF_IN < 240000000)
3304                         {
3305                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3306                                 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3307                                 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3308                                 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
3309                         }
3310                         if (state->RF_IN >= 240000000 && state->RF_IN < 340000000)
3311                         {
3312                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3313                                 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3314                                 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On
3315                                 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
3316                         }
3317                         if (state->RF_IN >= 340000000 && state->RF_IN < 430000000)
3318                         {
3319                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3320                                 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3321                                 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3322                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
3323                         }
3324                         if (state->RF_IN >= 430000000 && state->RF_IN < 470000000)
3325                         {
3326                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off
3327                                 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3328                                 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3329                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
3330                         }
3331                         if (state->RF_IN >= 470000000 && state->RF_IN < 570000000)
3332                         {
3333                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3334                                 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3335                                 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3336                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
3337                         }
3338                         if (state->RF_IN >= 570000000 && state->RF_IN < 620000000)
3339                         {
3340                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On
3341                                 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3342                                 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3343                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq
3344                         }
3345                         if (state->RF_IN >= 620000000 && state->RF_IN < 760000000)
3346                         {
3347                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3348                                 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3349                                 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3350                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3351                         }
3352                         if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
3353                         {
3354                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3355                                 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3356                                 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3357                                 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3358                         }
3359                 }
3360         }
3361
3362         if (state->TF_Type == MXL_TF_E) // Tracking Filter type E
3363         {
3364                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3365
3366                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
3367                 {
3368
3369                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3370                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3371                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3372                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3373                 }
3374                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
3375                 {
3376                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3377                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3378                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3379                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3380                 }
3381                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
3382                 {
3383                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3384                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3385                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3386                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3387                 }
3388                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
3389                 {
3390                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3391                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3392                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3393                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3394                 }
3395                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
3396                 {
3397                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3398                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3399                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3400                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3401                 }
3402                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
3403                 {
3404                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3405                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3406                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3407                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3408                 }
3409                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
3410                 {
3411                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3412                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3413                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3414                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3415                 }
3416         }
3417
3418         if (state->TF_Type == MXL_TF_F) // Tracking Filter type F
3419         {
3420                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3421
3422                 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000)
3423                 {
3424
3425                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3426                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3427                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3428                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3429                 }
3430                 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000)
3431                 {
3432                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3433                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3434                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3435                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3436                 }
3437                 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000)
3438                 {
3439                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3440                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3441                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3442                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3443                 }
3444                 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000)
3445                 {
3446                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3447                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3448                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3449                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3450                 }
3451                 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000)
3452                 {
3453                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3454                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3455                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3456                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3457                 }
3458                 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000)
3459                 {
3460                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3461                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3462                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3463                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3464                 }
3465                 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000)
3466                 {
3467                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3468                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3469                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3470                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3471                 }
3472         }
3473
3474         if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
3475         {
3476                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3477
3478                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
3479                 {
3480
3481                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3482                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3483                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3484                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3485                 }
3486                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
3487                 {
3488                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3489                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3490                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3491                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3492                 }
3493                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
3494                 {
3495                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3496                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3497                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3498                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3499                 }
3500                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
3501                 {
3502                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3503                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3504                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3505                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3506                 }
3507                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
3508                 {
3509                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3510                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3511                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3512                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3513                 }
3514                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
3515                 {
3516                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3517                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3518                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3519                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3520                 }
3521                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
3522                 {
3523                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3524                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3525                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3526                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3527                 }
3528         }
3529
3530         if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
3531         {
3532                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3533
3534                 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000)
3535                 {
3536
3537                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3538                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3539                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3540                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3541                 }
3542                 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000)
3543                 {
3544                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3545                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3546                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3547                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3548                 }
3549                 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000)
3550                 {
3551                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3552                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3553                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3554                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3555                 }
3556                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
3557                 {
3558                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3559                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3560                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3561                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3562                 }
3563                 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000)              //modified for 2.6.11
3564                 {
3565                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3566                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3567                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3568                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3569                 }
3570                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
3571                 {
3572                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3573                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3574                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3575                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3576                 }
3577                 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000)
3578                 {
3579                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3580                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3581                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3582                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3583                 }
3584                 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000)
3585                 {
3586                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3587                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3588                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3589                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3590                 }
3591         }
3592
3593         if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY  change for 2.6.8
3594         {
3595                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3596
3597                 // if UHF and terrestrial=> Turn off Tracking Filter
3598                 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
3599                 {
3600                         // Turn off all the banks
3601                         status += MXL_SetGPIO(fe, 3, 1) ;
3602                         status += MXL_SetGPIO(fe, 1, 1) ;
3603                         status += MXL_SetGPIO(fe, 4, 1) ;
3604                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
3605
3606                         //2.6.12
3607                         //Turn on RSSI
3608                         status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ;
3609                         status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ;
3610                         status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ;
3611                         status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ;
3612
3613                         // RSSI reference point
3614                         status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ;
3615                         status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ;
3616                         status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ;
3617
3618
3619             //status += MXL_ControlWrite(fe, AGC_IF, 10) ;              //doesn't matter since RSSI is turn on
3620
3621                         //following parameter is from analog OTA mode, can be change to seek better performance
3622                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
3623                 }
3624
3625                 else  //if VHF or Cable =>  Turn on Tracking Filter
3626                 {
3627                 //2.6.12
3628                 //Turn off RSSI
3629                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ;
3630
3631                 //change back from above condition
3632                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ;
3633
3634
3635                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
3636                 {
3637
3638                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3639                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3640                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3641                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3642                 }
3643                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
3644                 {
3645                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3646                         status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3647                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3648                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3649                 }
3650                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
3651                 {
3652                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3653                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3654                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3655                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3656                 }
3657                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
3658                 {
3659                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3660                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3661                         status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3662                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3663                 }
3664                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
3665                 {
3666                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3667                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3668                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3669                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3670                 }
3671                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
3672                 {
3673                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3674                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3675                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3676                         status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3677                 }
3678                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
3679                 {
3680                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3681                         status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3682                         status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3683                         status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3684                 }
3685                 }
3686         }
3687         return status ;
3688 }
3689
3690 // DONE
3691 u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3692 {
3693         u16 status = 0;
3694
3695         if (GPIO_Num == 1)
3696                 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3697
3698         /* GPIO2 is not available */
3699
3700         if (GPIO_Num == 3) {
3701                 if (GPIO_Val == 1) {
3702                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3703                         status += MXL_ControlWrite(fe, GPIO_3B, 0);
3704                 }
3705                 if (GPIO_Val == 0) {
3706                         status += MXL_ControlWrite(fe, GPIO_3, 1);
3707                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3708                 }
3709                 if (GPIO_Val == 3) { /* tri-state */
3710                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3711                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3712                 }
3713         }
3714         if (GPIO_Num == 4) {
3715                 if (GPIO_Val == 1) {
3716                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3717                         status += MXL_ControlWrite(fe, GPIO_4B, 0);
3718                 }
3719                 if (GPIO_Val == 0) {
3720                         status += MXL_ControlWrite(fe, GPIO_4, 1);
3721                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3722                 }
3723                 if (GPIO_Val == 3) { /* tri-state */
3724                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3725                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3726                 }
3727         }
3728
3729         return status;
3730 }
3731
3732 ///////////////////////////////////////////////////////////////////////////////
3733 //                                                                           //
3734 // Function:       MXL_ControlWrite                                          //
3735 //                                                                           //
3736 // Description:    Update control name value                                 //
3737 //                                                                           //
3738 // Globals:                                                                  //
3739 //                 NONE                                                      //
3740 //                                                                           //
3741 // Functions used:                                                           //
3742 //                 MXL_ControlWrite( Tuner, controlName, value, Group )      //
3743 //                                                                           //
3744 // Inputs:                                                                   //
3745 //                 Tuner         : Tuner structure                           //
3746 //                 ControlName   : Control name to be updated                //
3747 //                 value         : Value to be written                       //
3748 //                                                                           //
3749 // Outputs:                                                                  //
3750 //                 Tuner       : Tuner structure defined at higher level     //
3751 //                                                                           //
3752 // Return:                                                                   //
3753 //                 0 : Successful write                                      //
3754 //                 >0 : Value exceed maximum allowed for control number      //
3755 //                                                                           //
3756 ///////////////////////////////////////////////////////////////////////////////
3757 // DONE
3758 u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3759 {
3760         u16 status = 0;
3761
3762         /* Will write ALL Matching Control Name */
3763         status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);    /* Write Matching INIT Control */
3764         status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);    /* Write Matching CH Control */
3765 #ifdef _MXL_INTERNAL
3766         status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);    /* Write Matching MXL Control */
3767 #endif
3768         return status;
3769 }
3770
3771 ///////////////////////////////////////////////////////////////////////////////
3772 //                                                                           //
3773 // Function:       MXL_ControlWrite                                          //
3774 //                                                                           //
3775 // Description:    Update control name value                                 //
3776 //                                                                           //
3777 // Globals:                                                                  //
3778 //                 NONE                                                      //
3779 //                                                                           //
3780 // Functions used:                                                           //
3781 //                 strcmp                                                    //
3782 //                                                                           //
3783 // Inputs:                                                                   //
3784 //                 Tuner_struct: structure defined at higher level           //
3785 //                 ControlName      : Control Name                           //
3786 //                 value            : Value Assigned to Control Name         //
3787 //                 controlGroup     : Control Register Group                 //
3788 //                                                                           //
3789 // Outputs:                                                                  //
3790 //                 NONE                                                      //
3791 //                                                                           //
3792 // Return:                                                                   //
3793 //                 0 : Successful write                                      //
3794 //                 1 : Value exceed maximum allowed for control name         //
3795 //                 2 : Control name not found                                //
3796 //                                                                           //
3797 ///////////////////////////////////////////////////////////////////////////////
3798 // DONE
3799 u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
3800 {
3801         struct mxl5005s_state *state = fe->tuner_priv;
3802         u16 i, j, k;
3803         u32 highLimit;
3804         u32 ctrlVal;
3805
3806         if (controlGroup == 1) /* Initial Control */ {
3807
3808                 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3809
3810                         if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3811
3812                                 highLimit = 1 << state->Init_Ctrl[i].size;
3813                                 if (value < highLimit) {
3814                                         for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3815                                                 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3816                                                 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3817                                                         (u8)(state->Init_Ctrl[i].bit[j]),
3818                                                         (u8)((value>>j) & 0x01) );
3819                                         }
3820                                         ctrlVal = 0;
3821                                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3822                                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3823                                 }
3824                                 else
3825                                         return -1;
3826                         }
3827                 }
3828         }
3829         if (controlGroup == 2) /* Chan change Control */ {
3830
3831                 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3832
3833                         if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
3834
3835                                 highLimit = 1 << state->CH_Ctrl[i].size;
3836                                 if (value < highLimit) {
3837                                         for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3838                                                 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3839                                                 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3840                                                         (u8)(state->CH_Ctrl[i].bit[j]),
3841                                                         (u8)((value>>j) & 0x01) );
3842                                         }
3843                                         ctrlVal = 0;
3844                                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
3845                                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3846                                 }
3847                                 else
3848                                         return -1;
3849                         }
3850                 }
3851         }
3852 #ifdef _MXL_INTERNAL
3853         if (controlGroup == 3) /* Maxlinear Control */ {
3854
3855                 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3856
3857                         if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
3858
3859                                 highLimit = (1 << state->MXL_Ctrl[i].size) ;
3860                                 if (value < highLimit) {
3861                                         for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3862                                                 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3863                                                 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3864                                                         (u8)(state->MXL_Ctrl[i].bit[j]),
3865                                                         (u8)((value>>j) & 0x01) );
3866                                         }
3867                                         ctrlVal = 0;
3868                                         for(k = 0; k < state->MXL_Ctrl[i].size; k++)
3869                                                 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
3870                                 }
3871                                 else
3872                                         return -1;
3873                         }
3874                 }
3875         }
3876 #endif
3877         return 0 ; /* successful return */
3878 }
3879
3880 ///////////////////////////////////////////////////////////////////////////////
3881 //                                                                           //
3882 // Function:       MXL_RegWrite                                              //
3883 //                                                                           //
3884 // Description:    Update tuner register value                               //
3885 //                                                                           //
3886 // Globals:                                                                  //
3887 //                 NONE                                                      //
3888 //                                                                           //
3889 // Functions used:                                                           //
3890 //                 NONE                                                      //
3891 //                                                                           //
3892 // Inputs:                                                                   //
3893 //                 Tuner_struct: structure defined at higher level           //
3894 //                 RegNum    : Register address to be assigned a value       //
3895 //                 RegVal    : Register value to write                       //
3896 //                                                                           //
3897 // Outputs:                                                                  //
3898 //                 NONE                                                      //
3899 //                                                                           //
3900 // Return:                                                                   //
3901 //                 0 : Successful write                                      //
3902 //                 -1 : Invalid Register Address                             //
3903 //                                                                           //
3904 ///////////////////////////////////////////////////////////////////////////////
3905 // DONE
3906 u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3907 {
3908         struct mxl5005s_state *state = fe->tuner_priv;
3909         int i ;
3910
3911         for (i = 0; i < 104; i++) {
3912                 if (RegNum == state->TunerRegs[i].Reg_Num) {
3913                         state->TunerRegs[i].Reg_Val = RegVal;
3914                         return 0;
3915                 }
3916         }
3917
3918         return 1;
3919 }
3920
3921 ///////////////////////////////////////////////////////////////////////////////
3922 //                                                                           //
3923 // Function:       MXL_RegRead                                               //
3924 //                                                                           //
3925 // Description:    Retrieve tuner register value                             //
3926 //                                                                           //
3927 // Globals:                                                                  //
3928 //                 NONE                                                      //
3929 //                                                                           //
3930 // Functions used:                                                           //
3931 //                 NONE                                                      //
3932 //                                                                           //
3933 // Inputs:                                                                   //
3934 //                 Tuner_struct: structure defined at higher level           //
3935 //                 RegNum    : Register address to be assigned a value       //
3936 //                                                                           //
3937 // Outputs:                                                                  //
3938 //                 RegVal    : Retrieved register value                      //
3939 //                                                                           //
3940 // Return:                                                                   //
3941 //                 0 : Successful read                                       //
3942 //                 -1 : Invalid Register Address                             //
3943 //                                                                           //
3944 ///////////////////////////////////////////////////////////////////////////////
3945 // DONE
3946 u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3947 {
3948         struct mxl5005s_state *state = fe->tuner_priv;
3949         int i ;
3950
3951         for (i = 0; i < 104; i++) {
3952                 if (RegNum == state->TunerRegs[i].Reg_Num ) {
3953                         *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3954                         return 0;
3955                 }
3956         }
3957
3958         return 1;
3959 }
3960
3961 ///////////////////////////////////////////////////////////////////////////////
3962 //                                                                           //
3963 // Function:       MXL_ControlRead                                           //
3964 //                                                                           //
3965 // Description:    Retrieve the control value based on the control name      //
3966 //                                                                           //
3967 // Globals:                                                                  //
3968 //                 NONE                                                      //
3969 //                                                                           //
3970 // Inputs:                                                                   //
3971 //                 Tuner_struct  : structure defined at higher level         //
3972 //                 ControlName   : Control Name                              //
3973 //                                                                           //
3974 // Outputs:                                                                  //
3975 //                 value  : returned control value                           //
3976 //                                                                           //
3977 // Return:                                                                   //
3978 //                 0 : Successful read                                       //
3979 //                 -1 : Invalid control name                                 //
3980 //                                                                           //
3981 ///////////////////////////////////////////////////////////////////////////////
3982 // DONE
3983 u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3984 {
3985         struct mxl5005s_state *state = fe->tuner_priv;
3986         u32 ctrlVal ;
3987         u16 i, k ;
3988
3989         for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3990
3991                 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3992
3993                         ctrlVal = 0;
3994                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3995                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3996                         *value = ctrlVal;
3997                         return 0;
3998                 }
3999         }
4000
4001         for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4002
4003                 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
4004
4005                         ctrlVal = 0;
4006                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
4007                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
4008                         *value = ctrlVal;
4009                         return 0;
4010
4011                 }
4012         }
4013
4014 #ifdef _MXL_INTERNAL
4015         for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4016
4017                 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
4018
4019                         ctrlVal = 0;
4020                         for (k = 0; k < state->MXL_Ctrl[i].size; k++)
4021                                 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
4022                         *value = ctrlVal;
4023                         return 0;
4024
4025                 }
4026         }
4027 #endif
4028         return 1;
4029 }
4030
4031 ///////////////////////////////////////////////////////////////////////////////
4032 //                                                                           //
4033 // Function:       MXL_ControlRegRead                                        //
4034 //                                                                           //
4035 // Description:    Retrieve the register addresses and count related to a    //
4036 //                 a specific control name                               //
4037 //                                                                           //
4038 // Globals:                                                                  //
4039 //                 NONE                                                      //
4040 //                                                                           //
4041 // Inputs:                                                                   //
4042 //                 Tuner_struct  : structure defined at higher level         //
4043 //                 ControlName   : Control Name                              //
4044 //                                                                           //
4045 // Outputs:                                                                  //
4046 //                 RegNum  : returned register address array                 //
4047 //                 count   : returned register count related to a control    //
4048 //                                                                           //
4049 // Return:                                                                   //
4050 //                 0 : Successful read                                       //
4051 //                 -1 : Invalid control name                                 //
4052 //                                                                           //
4053 ///////////////////////////////////////////////////////////////////////////////
4054 // DONE
4055 u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
4056 {
4057         struct mxl5005s_state *state = fe->tuner_priv;
4058         u16 i, j, k ;
4059         u16 Count ;
4060
4061         for (i = 0; i < state->Init_Ctrl_Num ; i++) {
4062
4063                 if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) {
4064
4065                         Count = 1;
4066                         RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
4067
4068                         for (k = 1; k < state->Init_Ctrl[i].size; k++) {
4069
4070                                 for (j = 0; j < Count; j++) {
4071
4072                                         if (state->Init_Ctrl[i].addr[k] != RegNum[j]) {
4073
4074                                                 Count ++;
4075                                                 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
4076
4077                                         }
4078                                 }
4079
4080                         }
4081                         *count = Count;
4082                         return 0;
4083                 }
4084         }
4085         for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4086
4087                 if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
4088
4089                         Count = 1;
4090                         RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
4091
4092                         for (k = 1; k < state->CH_Ctrl[i].size; k++) {
4093
4094                                 for (j= 0; j<Count; j++) {
4095
4096                                         if (state->CH_Ctrl[i].addr[k] != RegNum[j]) {
4097
4098                                                 Count ++;
4099                                                 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
4100
4101                                         }
4102                                 }
4103                         }
4104                         *count = Count;
4105                         return 0;
4106                 }
4107         }
4108 #ifdef _MXL_INTERNAL
4109         for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4110
4111                 if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
4112
4113                         Count = 1;
4114                         RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
4115
4116                         for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
4117
4118                                 for (j = 0; j<Count; j++) {
4119
4120                                         if (state->MXL_Ctrl[i].addr[k] != RegNum[j]) {
4121
4122                                                 Count ++;
4123                                                 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
4124
4125                                         }
4126                                 }
4127                         }
4128                         *count = Count;
4129                         return 0;
4130                 }
4131         }
4132 #endif
4133         *count = 0;
4134         return 1;
4135 }
4136
4137 ///////////////////////////////////////////////////////////////////////////////
4138 //                                                                           //
4139 // Function:       MXL_RegWriteBit                                           //
4140 //                                                                           //
4141 // Description:    Write a register for specified register address,          //
4142 //                 register bit and register bit value                       //
4143 //                                                                           //
4144 // Globals:                                                                  //
4145 //                 NONE                                                      //
4146 //                                                                           //
4147 // Inputs:                                                                   //
4148 //                 Tuner_struct  : structure defined at higher level         //
4149 //                 address       : register address                          //
4150 //                 bit           : register bit number                       //
4151 //                 bitVal        : register bit value                        //
4152 //                                                                           //
4153 // Outputs:                                                                  //
4154 //                 NONE                                                      //
4155 //                                                                           //
4156 // Return:                                                                   //
4157 //                 NONE                                                      //
4158 //                                                                           //
4159 ///////////////////////////////////////////////////////////////////////////////
4160 // DONE
4161 void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
4162 {
4163         struct mxl5005s_state *state = fe->tuner_priv;
4164         int i ;
4165
4166         const u8 AND_MAP[8] = {
4167                 0xFE, 0xFD, 0xFB, 0xF7,
4168                 0xEF, 0xDF, 0xBF, 0x7F } ;
4169
4170         const u8 OR_MAP[8] = {
4171                 0x01, 0x02, 0x04, 0x08,
4172                 0x10, 0x20, 0x40, 0x80 } ;
4173
4174         for (i = 0; i < state->TunerRegs_Num; i++) {
4175                 if (state->TunerRegs[i].Reg_Num == address) {
4176                         if (bitVal)
4177                                 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
4178                         else
4179                                 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
4180                         break ;
4181                 }
4182         }
4183 }
4184
4185 ///////////////////////////////////////////////////////////////////////////////
4186 //                                                                           //
4187 // Function:       MXL_Ceiling                                               //
4188 //                                                                           //
4189 // Description:    Complete to closest increment of resolution               //
4190 //                                                                           //
4191 // Globals:                                                                  //
4192 //                 NONE                                                      //
4193 //                                                                           //
4194 // Functions used:                                                           //
4195 //                 NONE                                                      //
4196 //                                                                           //
4197 // Inputs:                                                                   //
4198 //                 value       : Input number to compute                     //
4199 //                 resolution  : Increment step                              //
4200 //                                                                           //
4201 // Outputs:                                                                  //
4202 //                 NONE                                                      //
4203 //                                                                           //
4204 // Return:                                                                   //
4205 //                Computed value                                             //
4206 //                                                                           //
4207 ///////////////////////////////////////////////////////////////////////////////
4208 // DONE
4209 u32 MXL_Ceiling(u32 value, u32 resolution)
4210 {
4211         return (value/resolution + (value % resolution > 0 ? 1 : 0));
4212 }
4213
4214 //
4215 // Retrieve the Initialzation Registers
4216 //
4217 // DONE
4218 u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4219 {
4220         u16 status = 0;
4221         int i ;
4222
4223         u8 RegAddr[] = {
4224                 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
4225                 76, 77, 91, 134, 135, 137, 147,
4226                 156, 166, 167, 168, 25 };
4227
4228         *count = sizeof(RegAddr) / sizeof(u8);
4229
4230         status += MXL_BlockInit(fe);
4231
4232         for (i = 0 ; i < *count; i++) {
4233                 RegNum[i] = RegAddr[i];
4234                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
4235         }
4236
4237         return status;
4238 }
4239
4240 // DONE
4241 u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4242 {
4243         u16 status = 0;
4244         int i ;
4245
4246 //add 77, 166, 167, 168 register for 2.6.12
4247 #ifdef _MXL_PRODUCTION
4248         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4249            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4250 #else
4251         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4252            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4253         //u8 RegAddr[171];
4254         //for (i=0; i<=170; i++)
4255         //      RegAddr[i] = i;
4256 #endif
4257
4258         *count = sizeof(RegAddr) / sizeof(u8);
4259
4260         for (i = 0 ; i < *count; i++) {
4261                 RegNum[i] = RegAddr[i];
4262                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
4263         }
4264
4265         return status;
4266 }
4267
4268 // DONE
4269 u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4270 {
4271         u16 status = 0;
4272         int i;
4273
4274         u8 RegAddr[] = {43, 136};
4275
4276         *count = sizeof(RegAddr) / sizeof(u8);
4277
4278         for (i = 0; i < *count; i++) {
4279                 RegNum[i] = RegAddr[i];
4280                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
4281         }
4282
4283         return status;
4284 }
4285
4286 // DONE
4287 u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4288 {
4289         u16 status = 0;
4290         int i;
4291
4292         u8 RegAddr[] = { 138 };
4293
4294         *count = sizeof(RegAddr) / sizeof(u8);
4295
4296         for (i = 0; i < *count; i++) {
4297                 RegNum[i] = RegAddr[i];
4298                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
4299         }
4300
4301         return status;
4302 }
4303
4304 // DONE
4305 u16 MXL_GetMasterControl(u8 *MasterReg, int state)
4306 {
4307         if (state == 1) /* Load_Start */
4308                 *MasterReg = 0xF3;
4309         if (state == 2) /* Power_Down */
4310                 *MasterReg = 0x41;
4311         if (state == 3) /* Synth_Reset */
4312                 *MasterReg = 0xB1;
4313         if (state == 4) /* Seq_Off */
4314                 *MasterReg = 0xF1;
4315
4316         return 0;
4317 }
4318
4319 #ifdef _MXL_PRODUCTION
4320 u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4321 {
4322         struct mxl5005s_state *state = fe->tuner_priv;
4323         u16 status = 0 ;
4324
4325         if (VCO_Range == 1) {
4326                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4327                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4328                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4329                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4330                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4331                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4332                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4333                 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4334                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4335                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4336                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4337                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224);
4338                 }
4339                 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4340                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4341                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4342                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4343                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822);
4344                 }
4345                 if (state->Mode == 1) /* Digital Mode */ {
4346                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4347                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4348                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4349                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376);
4350                 }
4351         }
4352
4353         if (VCO_Range == 2) {
4354                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4355                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4356                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4357                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4358                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4359                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4360                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4361                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4362                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4363                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4364                 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4365                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4366                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4367                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4368                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4369                 }
4370                 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4371                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4372                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4373                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4374                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4375                 }
4376                 if (state->Mode == 1) /* Digital Mode */ {
4377                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4378                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4379                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4380                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384);
4381                 }
4382         }
4383
4384         if (VCO_Range == 3) {
4385                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4386                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4387                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4388                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4389                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4390                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4391                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4392                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4393                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4394                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4395                 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4396                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4397                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4398                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4399                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4400                 }
4401                 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4402                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4403                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4404                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4405                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4406                 }
4407                 if (state->Mode == 1) /* Digital Mode */ {
4408                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4409                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4410                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4411                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760);
4412                 }
4413         }
4414
4415         if (VCO_Range == 4) {
4416                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4417                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4418                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4419                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4420                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4421                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4422                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4423                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4424                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4425                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4426                 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4427                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4428                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4429                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4430                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4431                 }
4432                 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4433                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4434                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4435                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4436                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4437                 }
4438                 if (state->Mode == 1) /* Digital Mode */ {
4439                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4440                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4441                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4442                         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992);
4443                 }
4444         }
4445
4446         return status;
4447 }
4448
4449 // DONE
4450 u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
4451 {
4452         struct mxl5005s_state *state = fe->tuner_priv;
4453         u16 status = 0;
4454
4455         if (Hystersis == 1)
4456                 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
4457
4458         return status;
4459 }
4460
4461 #endif
4462
4463 /* Linux driver related functions */
4464
4465 int mxl5005s_init(struct dvb_frontend *fe)
4466 {
4467         struct mxl5005s_state *state = fe->tuner_priv;
4468
4469         u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4470         u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4471         int TableLen;
4472
4473         dprintk(1, "%s()\n", __func__);
4474
4475         mxl5005s_reset(fe);
4476
4477         /* Tuner initialization stage 0 */
4478         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4479         AddrTable[0] = MASTER_CONTROL_ADDR;
4480         ByteTable[0] |= state->config->AgcMasterByte;
4481
4482         mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
4483
4484         mxl5005s_AssignTunerMode(fe); // tunre_config
4485
4486         /* Tuner initialization stage 1 */
4487         MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4488
4489         mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
4490
4491         return 0;
4492 }
4493
4494 int mxl5005s_AssignTunerMode(struct dvb_frontend *fe)
4495 {
4496         struct mxl5005s_state *state = fe->tuner_priv;
4497         struct mxl5005s_config *c = state->config;
4498
4499         InitTunerControls(fe);
4500
4501         /* Set MxL5005S parameters. */
4502         MXL5005_TunerConfig(
4503                 fe,
4504                 c->mod_mode,
4505                 c->if_mode,
4506                 MXL5005S_BANDWIDTH_6MHZ,
4507                 c->if_freq,
4508                 c->xtal_freq,
4509                 c->agc_mode,
4510                 c->top,
4511                 c->output_load,
4512                 c->clock_out,
4513                 c->div_out,
4514                 c->cap_select,
4515                 c->rssi_enable,
4516                 MXL_QAM,
4517                 c->tracking_filter);
4518
4519         return 0;
4520 }
4521
4522 static int mxl5005s_set_params(struct dvb_frontend *fe,
4523                                struct dvb_frontend_parameters *params)
4524 {
4525         u32 freq;
4526         u32 bw;
4527
4528         if (fe->ops.info.type == FE_OFDM)
4529                 bw = params->u.ofdm.bandwidth;
4530         else
4531                 bw = MXL5005S_BANDWIDTH_6MHZ;
4532
4533         freq = params->frequency; /* Hz */
4534         dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw);
4535
4536         mxl5005s_SetRfFreqHz(fe, freq);
4537
4538         msleep(350);
4539
4540         return 0;
4541 }
4542
4543 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4544 {
4545         struct mxl5005s_state *state = fe->tuner_priv;
4546         dprintk(1, "%s()\n", __func__);
4547
4548         *frequency = state->RF_IN;
4549
4550         return 0;
4551 }
4552
4553 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4554 {
4555         struct mxl5005s_state *state = fe->tuner_priv;
4556         dprintk(1, "%s()\n", __func__);
4557
4558         *bandwidth = state->Chan_Bandwidth;
4559
4560         return 0;
4561 }
4562
4563 static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status)
4564 {
4565         dprintk(1, "%s()\n", __func__);
4566
4567         *status = 0;
4568         // *status = TUNER_STATUS_LOCKED;
4569
4570         return 0;
4571 }
4572
4573 static int mxl5005s_release(struct dvb_frontend *fe)
4574 {
4575         dprintk(1, "%s()\n", __func__);
4576         kfree(fe->tuner_priv);
4577         fe->tuner_priv = NULL;
4578         return 0;
4579 }
4580
4581 static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4582         .info = {
4583                 .name           = "MaxLinear MXL5005S",
4584                 .frequency_min  =  48000000,
4585                 .frequency_max  = 860000000,
4586                 .frequency_step =     50000,
4587         },
4588
4589         .release       = mxl5005s_release,
4590         .init          = mxl5005s_init,
4591
4592         .set_params    = mxl5005s_set_params,
4593         .get_frequency = mxl5005s_get_frequency,
4594         .get_bandwidth = mxl5005s_get_bandwidth,
4595         .get_status    = mxl5005s_get_status
4596 };
4597
4598 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4599                                      struct i2c_adapter *i2c,
4600                                      struct mxl5005s_config *config)
4601 {
4602         struct mxl5005s_state *state = NULL;
4603         dprintk(1, "%s()\n", __func__);
4604
4605         state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4606         if (state == NULL)
4607                 return NULL;
4608
4609         state->frontend = fe;
4610         state->config = config;
4611         state->i2c = i2c;
4612
4613         printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address);
4614
4615         memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops));
4616
4617         fe->tuner_priv = state;
4618         return fe;
4619 }
4620 EXPORT_SYMBOL(mxl5005s_attach);
4621
4622 MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4623 MODULE_AUTHOR("Jan Hoogenraad");
4624 MODULE_AUTHOR("Barnaby Shearer");
4625 MODULE_AUTHOR("Andy Hasper");
4626 MODULE_AUTHOR("Steven Toth");
4627 MODULE_LICENSE("GPL");