git.oblomov.eu Git - linux-2.6/blob - drivers/net/irda/smsc-ircc2.h

   1 /*********************************************************************
   2  * $Id: smsc-ircc2.h,v 1.12.2.1 2002/10/27 10:52:37 dip Exp $
   3  *
   4  * Description:   Definitions for the SMC IrCC chipset
   5  * Status:        Experimental.
   6  * Author:        Daniele Peri (peri@csai.unipa.it)
   7  *
   8  *     Copyright (c) 2002      Daniele Peri
   9  *     All Rights Reserved.
  10  *
  11  * Based on smc-ircc.h:
  12  *
  13  *     Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
  14  *     Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
  15  *     All Rights Reserved
  16  *
  17  *
  18  *     This program is free software; you can redistribute it and/or
  19  *     modify it under the terms of the GNU General Public License as
  20  *     published by the Free Software Foundation; either version 2 of
  21  *     the License, or (at your option) any later version.
  22  *
  23  *     This program is distributed in the hope that it will be useful,
  24  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26  *     GNU General Public License for more details.
  27  *
  28  *     You should have received a copy of the GNU General Public License
  29  *     along with this program; if not, write to the Free Software
  30  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  *     MA 02111-1307 USA
  32  *
  33  ********************************************************************/
  34
  35 #ifndef SMSC_IRCC2_H
  36 #define SMSC_IRCC2_H
  37
  38 /* DMA modes needed */
  39 #define DMA_TX_MODE                0x08    /* Mem to I/O, ++, demand. */
  40 #define DMA_RX_MODE                0x04    /* I/O to mem, ++, demand. */
  41
  42 /* Master Control Register */
  43 #define IRCC_MASTER                0x07
  44 #define   IRCC_MASTER_POWERDOWN    0x80
  45 #define   IRCC_MASTER_RESET        0x40
  46 #define   IRCC_MASTER_INT_EN       0x20
  47 #define   IRCC_MASTER_ERROR_RESET  0x10
  48
  49 /* Register block 0 */
  50
  51 /* Interrupt Identification */
  52 #define IRCC_IIR                                        0x01
  53 #define   IRCC_IIR_ACTIVE_FRAME         0x80
  54 #define   IRCC_IIR_EOM                          0x40
  55 #define   IRCC_IIR_RAW_MODE                     0x20
  56 #define   IRCC_IIR_FIFO                         0x10
  57
  58 /* Interrupt Enable */
  59 #define IRCC_IER                                        0x02
  60 #define   IRCC_IER_ACTIVE_FRAME         0x80
  61 #define   IRCC_IER_EOM                          0x40
  62 #define   IRCC_IER_RAW_MODE                     0x20
  63 #define   IRCC_IER_FIFO                         0x10
  64
  65 /* Line Status Register */
  66 #define IRCC_LSR                                        0x03
  67 #define   IRCC_LSR_UNDERRUN                     0x80
  68 #define   IRCC_LSR_OVERRUN                      0x40
  69 #define   IRCC_LSR_FRAME_ERROR          0x20
  70 #define   IRCC_LSR_SIZE_ERROR           0x10
  71 #define   IRCC_LSR_CRC_ERROR            0x80
  72 #define   IRCC_LSR_FRAME_ABORT          0x40
  73
  74 /* Line Status Address Register */
  75 #define IRCC_LSAR                                       0x03
  76 #define IRCC_LSAR_ADDRESS_MASK          0x07
  77
  78 /* Line Control Register A */
  79 #define IRCC_LCR_A                 0x04
  80 #define   IRCC_LCR_A_FIFO_RESET    0x80
  81 #define   IRCC_LCR_A_FAST          0x40
  82 #define   IRCC_LCR_A_GP_DATA       0x20
  83 #define   IRCC_LCR_A_RAW_TX        0x10
  84 #define   IRCC_LCR_A_RAW_RX        0x08
  85 #define   IRCC_LCR_A_ABORT         0x04
  86 #define   IRCC_LCR_A_DATA_DONE     0x02
  87
  88 /* Line Control Register B */
  89 #define IRCC_LCR_B                 0x05
  90 #define   IRCC_LCR_B_SCE_DISABLED  0x00
  91 #define   IRCC_LCR_B_SCE_TRANSMIT  0x40
  92 #define   IRCC_LCR_B_SCE_RECEIVE   0x80
  93 #define   IRCC_LCR_B_SCE_UNDEFINED 0xc0
  94 #define   IRCC_LCR_B_SIP_ENABLE    0x20
  95 #define   IRCC_LCR_B_BRICK_WALL    0x10
  96
  97 /* Bus Status Register */
  98 #define IRCC_BSR                   0x06
  99 #define   IRCC_BSR_NOT_EMPTY       0x80
 100 #define   IRCC_BSR_FIFO_FULL       0x40
 101 #define   IRCC_BSR_TIMEOUT         0x20
 102
 103 /* Register block 1 */
 104
 105 #define IRCC_FIFO_THRESHOLD                     0x02
 106
 107 #define IRCC_SCE_CFGA                           0x00
 108 #define   IRCC_CFGA_AUX_IR                      0x80
 109 #define   IRCC_CFGA_HALF_DUPLEX         0x04
 110 #define   IRCC_CFGA_TX_POLARITY         0x02
 111 #define   IRCC_CFGA_RX_POLARITY         0x01
 112
 113 #define   IRCC_CFGA_COM                         0x00
 114 #define         IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK      0x87
 115 #define         IRCC_CFGA_IRDA_SIR_A    0x08
 116 #define         IRCC_CFGA_ASK_SIR               0x10
 117 #define         IRCC_CFGA_IRDA_SIR_B    0x18
 118 #define         IRCC_CFGA_IRDA_HDLC             0x20
 119 #define         IRCC_CFGA_IRDA_4PPM             0x28
 120 #define         IRCC_CFGA_CONSUMER              0x30
 121 #define         IRCC_CFGA_RAW_IR                0x38
 122 #define     IRCC_CFGA_OTHER                     0x40
 123
 124 #define IRCC_IR_HDLC               0x04
 125 #define IRCC_IR_4PPM               0x01
 126 #define IRCC_IR_CONSUMER           0x02
 127
 128 #define IRCC_SCE_CFGB              0x01
 129 #define IRCC_CFGB_LOOPBACK         0x20
 130 #define IRCC_CFGB_LPBCK_TX_CRC     0x10
 131 #define IRCC_CFGB_NOWAIT           0x08
 132 #define IRCC_CFGB_STRING_MOVE      0x04
 133 #define IRCC_CFGB_DMA_BURST        0x02
 134 #define IRCC_CFGB_DMA_ENABLE       0x01
 135
 136 #define IRCC_CFGB_MUX_COM          0x00
 137 #define IRCC_CFGB_MUX_IR           0x40
 138 #define IRCC_CFGB_MUX_AUX          0x80
 139 #define IRCC_CFGB_MUX_INACTIVE     0xc0
 140
 141 /* Register block 3 - Identification Registers! */
 142 #define IRCC_ID_HIGH               0x00   /* 0x10 */
 143 #define IRCC_ID_LOW                0x01   /* 0xB8 */
 144 #define IRCC_CHIP_ID               0x02   /* 0xF1 */
 145 #define IRCC_VERSION               0x03   /* 0x01 */
 146 #define IRCC_INTERFACE             0x04   /* low 4 = DMA, high 4 = IRQ */
 147 #define         IRCC_INTERFACE_DMA_MASK 0x0F   /* low 4 = DMA, high 4 = IRQ */
 148 #define         IRCC_INTERFACE_IRQ_MASK 0xF0   /* low 4 = DMA, high 4 = IRQ */
 149
 150 /* Register block 4 - IrDA */
 151 #define IRCC_CONTROL               0x00
 152 #define IRCC_BOF_COUNT_LO          0x01 /* Low byte */
 153 #define IRCC_BOF_COUNT_HI          0x00 /* High nibble (bit 0-3) */
 154 #define IRCC_BRICKWALL_CNT_LO      0x02 /* Low byte */
 155 #define IRCC_BRICKWALL_CNT_HI      0x03 /* High nibble (bit 4-7) */
 156 #define IRCC_TX_SIZE_LO            0x04 /* Low byte */
 157 #define IRCC_TX_SIZE_HI            0x03 /* High nibble (bit 0-3) */
 158 #define IRCC_RX_SIZE_HI            0x05 /* High nibble (bit 0-3) */
 159 #define IRCC_RX_SIZE_LO            0x06 /* Low byte */
 160
 161 #define IRCC_1152                  0x80
 162 #define IRCC_CRC                   0x40
 163
 164 /* Register block 5 - IrDA */
 165 #define IRCC_ATC                                        0x00
 166 #define         IRCC_ATC_nPROGREADY             0x80
 167 #define         IRCC_ATC_SPEED                  0x40
 168 #define         IRCC_ATC_ENABLE                 0x20
 169 #define         IRCC_ATC_MASK                   0xE0
 170
 171
 172 #define IRCC_IRHALFDUPLEX_TIMEOUT       0x01
 173
 174 #define IRCC_SCE_TX_DELAY_TIMER         0x02
 175
 176 /*
 177  * Other definitions
 178  */
 179
 180 #define SMSC_IRCC2_MAX_SIR_SPEED                115200
 181 #define SMSC_IRCC2_FIR_CHIP_IO_EXTENT   8
 182 #define SMSC_IRCC2_SIR_CHIP_IO_EXTENT   8
 183 #define SMSC_IRCC2_FIFO_SIZE                    16
 184 #define SMSC_IRCC2_FIFO_THRESHOLD               64
 185 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 186 #define SMSC_IRCC2_RX_BUFF_TRUESIZE             14384
 187 #define SMSC_IRCC2_TX_BUFF_TRUESIZE             14384
 188 #define SMSC_IRCC2_MIN_TURN_TIME                0x07
 189 #define SMSC_IRCC2_WINDOW_SIZE                  0x07
 190 /* Maximum wait for hw transmitter to finish */
 191 #define SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US    1000    /* 1 ms */
 192 /* Maximum wait for ATC transceiver programming to finish */
 193 #define SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES 1
 194 #endif /* SMSC_IRCC2_H */