2 * Defines x86 CPU feature bits
4 #ifndef _ASM_X86_CPUFEATURE_H
5 #define _ASM_X86_CPUFEATURE_H
7 #include <asm/required-features.h>
9 #define NCAPINTS 9 /* N 32-bit words worth of info */
12 * Note: If the comment begins with a quoted string, that string is used
13 * in /proc/cpuinfo instead of the macro name. If the string is "",
14 * this feature bit is not displayed in /proc/cpuinfo at all.
17 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
18 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
19 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
20 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
21 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
22 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
23 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
24 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
25 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
26 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
27 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
28 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
29 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
30 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
31 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
32 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */
33 /* (plus FCMOVcc, FCOMI with FPU) */
34 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
35 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
36 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
37 #define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */
38 #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
39 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
40 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
41 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
42 #define X86_FEATURE_XMM (0*32+25) /* "sse" */
43 #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
44 #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */
45 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
46 #define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */
47 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
48 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
50 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
51 /* Don't duplicate feature flags which are redundant with Intel! */
52 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
53 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */
54 #define X86_FEATURE_NX (1*32+20) /* Execute Disable */
55 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
56 #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
57 #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
58 #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
59 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
60 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
61 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
63 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
64 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
65 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
66 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
68 /* Other features, Linux-defined mapping, word 3 */
69 /* This range is used for feature bits which conflict or are synthesized */
70 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
71 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
72 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
73 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
74 /* cpu types for specific tunings: */
75 #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */
76 #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */
77 #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */
78 #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */
79 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
80 #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
81 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
82 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
83 #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
84 #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
85 #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
86 #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
87 #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
88 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
89 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
90 #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
91 #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
92 #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
93 #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
94 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
95 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
96 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
98 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
99 #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
100 #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
101 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
102 #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
103 #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
104 #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
105 #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */
106 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
107 #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
108 #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
109 #define X86_FEATURE_CID (4*32+10) /* Context ID */
110 #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
111 #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
112 #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
113 #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
114 #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
115 #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
116 #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
117 #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
118 #define X86_FEATURE_AES (4*32+25) /* AES instructions */
119 #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
120 #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
121 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
122 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
124 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
125 #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
126 #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */
127 #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
128 #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
129 #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
130 #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
131 #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
132 #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
133 #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
134 #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
136 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
137 #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
138 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
139 #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
140 #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
141 #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
142 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
143 #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
144 #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
145 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
146 #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
147 #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
148 #define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */
149 #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
150 #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
153 * Auxiliary flags: Linux defined - For features scattered in various
154 * CPUID levels like 0x6, 0xA etc
156 #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
157 #define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */
159 /* Virtualization flags: Linux defined */
160 #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */
161 #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */
162 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
163 #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */
164 #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */
166 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
168 #include <linux/bitops.h>
170 extern const char * const x86_cap_flags[NCAPINTS*32];
171 extern const char * const x86_power_flags[32];
173 #define test_cpu_cap(c, bit) \
174 test_bit(bit, (unsigned long *)((c)->x86_capability))
176 #define cpu_has(c, bit) \
177 (__builtin_constant_p(bit) && \
178 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
179 (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
180 (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
181 (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
182 (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
183 (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
184 (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
185 (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
187 test_cpu_cap(c, bit))
189 #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
191 #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
192 #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
193 #define setup_clear_cpu_cap(bit) do { \
194 clear_cpu_cap(&boot_cpu_data, bit); \
195 set_bit(bit, (unsigned long *)cleared_cpu_caps); \
197 #define setup_force_cpu_cap(bit) do { \
198 set_cpu_cap(&boot_cpu_data, bit); \
199 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
202 #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
203 #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
204 #define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
205 #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
206 #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
207 #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
208 #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
209 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
210 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
211 #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
212 #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
213 #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
214 #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
215 #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
216 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
217 #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
218 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
219 #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
220 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
221 #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
222 #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
223 #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
224 #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
225 #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
226 #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
227 #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
228 #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
229 #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
230 #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
231 #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
232 #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
233 #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
234 #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
235 #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
236 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
237 #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
238 #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
239 #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
240 #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
241 #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
242 #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
243 #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
244 #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
245 #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
247 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
248 # define cpu_has_invlpg 1
250 # define cpu_has_invlpg (boot_cpu_data.x86 > 3)
256 #define cpu_has_vme 0
259 #define cpu_has_pae ___BUG___
264 #undef cpu_has_k6_mtrr
265 #define cpu_has_k6_mtrr 0
267 #undef cpu_has_cyrix_arr
268 #define cpu_has_cyrix_arr 0
270 #undef cpu_has_centaur_mcr
271 #define cpu_has_centaur_mcr 0
273 #endif /* CONFIG_X86_64 */
275 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
277 #endif /* _ASM_X86_CPUFEATURE_H */
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