2 * Low-Level PCI Support for the SH7751
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
23 #include <asm/addrspace.h>
27 * Initialization. Try all known PCI access methods. Note that we support
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
35 int __init sh7751_pci_init(struct pci_channel *chan)
40 pr_debug("PCI: Starting intialization.\n");
42 chan->reg_base = 0xfe200000;
43 chan->io_base = 0xfe240000;
45 /* check for SH7751/SH7751R hardware */
46 id = pci_read_reg(chan, SH7751_PCICONF0);
47 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
48 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
49 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
53 if ((ret = sh4_pci_check_direct(chan)) != 0)
56 return pcibios_init_platform();
59 static int __init __area_sdram_check(struct pci_channel *chan,
64 word = ctrl_inl(SH7751_BCR1);
65 /* check BCR for SDRAM in area */
66 if (((word >> area) & 1) == 0) {
67 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
71 pci_write_reg(chan, word, SH4_PCIBCR1);
73 word = (u16)ctrl_inw(SH7751_BCR2);
74 /* check BCR2 for 32bit SDRAM interface*/
75 if (((word >> (area << 1)) & 0x3) != 0x3) {
76 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
80 pci_write_reg(chan, word, SH4_PCIBCR2);
85 int __init sh7751_pcic_init(struct pci_channel *chan,
86 struct sh4_pci_address_map *map)
91 /* Set the BCR's to enable PCI access */
92 reg = ctrl_inl(SH7751_BCR1);
94 ctrl_outl(reg, SH7751_BCR1);
96 /* Turn the clocks back on (not done in reset)*/
97 pci_write_reg(chan, 0, SH4_PCICLKR);
98 /* Clear Powerdown IRQ's (not done in reset) */
99 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
100 pci_write_reg(chan, word, SH4_PCIPINT);
103 * This code is unused for some boards as it is done in the
104 * bootloader and doing it here means the MAC addresses loaded
105 * by the bootloader get lost.
107 if (!(map->flags & SH4_PCIC_NO_RESET)) {
108 /* toggle PCI reset pin */
109 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
110 pci_write_reg(chan, word, SH4_PCICR);
111 /* Wait for a long time... not 1 sec. but long enough */
113 word = SH4_PCICR_PREFIX;
114 pci_write_reg(chan, word, SH4_PCICR);
117 /* set the command/status bits to:
118 * Wait Cycle Control + Parity Enable + Bus Master +
121 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
122 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
123 pci_write_reg(chan, word, SH7751_PCICONF1);
125 /* define this host as the host bridge */
126 word = PCI_BASE_CLASS_BRIDGE << 24;
127 pci_write_reg(chan, word, SH7751_PCICONF2);
129 /* Set IO and Mem windows to local address
130 * Make PCI and local address the same for easy 1 to 1 mapping
131 * Window0 = map->window0.size @ non-cached area base = SDRAM
132 * Window1 = map->window1.size @ cached area base = SDRAM
134 word = map->window0.size - 1;
135 pci_write_reg(chan, word, SH4_PCILSR0);
136 word = map->window1.size - 1;
137 pci_write_reg(chan, word, SH4_PCILSR1);
138 /* Set the values on window 0 PCI config registers */
139 word = P2SEGADDR(map->window0.base);
140 pci_write_reg(chan, word, SH4_PCILAR0);
141 pci_write_reg(chan, word, SH7751_PCICONF5);
142 /* Set the values on window 1 PCI config registers */
143 word = PHYSADDR(map->window1.base);
144 pci_write_reg(chan, word, SH4_PCILAR1);
145 pci_write_reg(chan, word, SH7751_PCICONF6);
147 /* Set the local 16MB PCI memory space window to
148 * the lowest PCI mapped address
150 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
151 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
152 pci_write_reg(chan, word , SH4_PCIMBR);
154 /* Map IO space into PCI IO window:
155 * IO addresses will be translated to the PCI IO window base address
157 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%lx\n",
158 chan->io_resource->start, chan->io_resource->end,
159 chan->io_base + chan->io_resource->start);
161 /* Make sure the MSB's of IO window are set to access PCI space
163 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
164 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
165 pci_write_reg(chan, word, SH4_PCIIOBR);
167 /* Set PCI WCRx, BCRx's, copy from BSC locations */
169 /* check BCR for SDRAM in specified area */
170 switch (map->window0.base) {
171 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
172 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
173 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
174 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
175 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
176 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
177 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
183 /* configure the wait control registers */
184 word = ctrl_inl(SH7751_WCR1);
185 pci_write_reg(chan, word, SH4_PCIWCR1);
186 word = ctrl_inl(SH7751_WCR2);
187 pci_write_reg(chan, word, SH4_PCIWCR2);
188 word = ctrl_inl(SH7751_WCR3);
189 pci_write_reg(chan, word, SH4_PCIWCR3);
190 word = ctrl_inl(SH7751_MCR);
191 pci_write_reg(chan, word, SH4_PCIMCR);
193 /* NOTE: I'm ignoring the PCI error IRQs for now..
194 * TODO: add support for the internal error interrupts and
198 pci_fixup_pcic(chan);
200 /* SH7751 init done, set central function init complete */
201 /* use round robin mode to stop a device starving/overruning */
202 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
203 pci_write_reg(chan, word, SH4_PCICR);