2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
29 /* reserved_mem_dcache_on and cache friends */
30 #include <asm/cplbinit.h>
31 #include <asm/cacheflush.h>
33 #define DRV_NAME "bfin-spi"
34 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
35 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
36 #define DRV_VERSION "1.0"
38 MODULE_AUTHOR(DRV_AUTHOR);
39 MODULE_DESCRIPTION(DRV_DESC);
40 MODULE_LICENSE("GPL");
42 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
44 #define START_STATE ((void *)0)
45 #define RUNNING_STATE ((void *)1)
46 #define DONE_STATE ((void *)2)
47 #define ERROR_STATE ((void *)-1)
48 #define QUEUE_RUNNING 0
49 #define QUEUE_STOPPED 1
52 /* Driver model hookup */
53 struct platform_device *pdev;
55 /* SPI framework hookup */
56 struct spi_master *master;
58 /* Regs base of SPI controller */
59 void __iomem *regs_base;
61 /* Pin request list */
65 struct bfin5xx_spi_master *master_info;
67 /* Driver message queue */
68 struct workqueue_struct *workqueue;
69 struct work_struct pump_messages;
71 struct list_head queue;
75 /* Message Transfer pump */
76 struct tasklet_struct pump_transfers;
78 /* Current message transfer state info */
79 struct spi_message *cur_msg;
80 struct spi_transfer *cur_transfer;
81 struct chip_data *cur_chip;
100 void (*write) (struct driver_data *);
101 void (*read) (struct driver_data *);
102 void (*duplex) (struct driver_data *);
112 u8 width; /* 0 or 1 */
114 u8 bits_per_word; /* 8 or 16 */
115 u8 cs_change_per_word;
116 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
117 void (*write) (struct driver_data *);
118 void (*read) (struct driver_data *);
119 void (*duplex) (struct driver_data *);
122 #define DEFINE_SPI_REG(reg, off) \
123 static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
128 DEFINE_SPI_REG(CTRL, 0x00)
129 DEFINE_SPI_REG(FLAG, 0x04)
130 DEFINE_SPI_REG(STAT, 0x08)
131 DEFINE_SPI_REG(TDBR, 0x0C)
132 DEFINE_SPI_REG(RDBR, 0x10)
133 DEFINE_SPI_REG(BAUD, 0x14)
134 DEFINE_SPI_REG(SHAW, 0x18)
136 static void bfin_spi_enable(struct driver_data *drv_data)
140 cr = read_CTRL(drv_data);
141 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
144 static void bfin_spi_disable(struct driver_data *drv_data)
148 cr = read_CTRL(drv_data);
149 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
152 /* Caculate the SPI_BAUD register value based on input HZ */
153 static u16 hz_to_spi_baud(u32 speed_hz)
155 u_long sclk = get_sclk();
156 u16 spi_baud = (sclk / (2 * speed_hz));
158 if ((sclk % (2 * speed_hz)) > 0)
164 static int flush(struct driver_data *drv_data)
166 unsigned long limit = loops_per_jiffy << 1;
168 /* wait for stop and clear stat */
169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
172 write_STAT(drv_data, BIT_STAT_CLR);
177 /* Chip select operation functions for cs_change flag */
178 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
180 u16 flag = read_FLAG(drv_data);
183 flag &= ~(chip->flag << 8);
185 write_FLAG(drv_data, flag);
188 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
190 u16 flag = read_FLAG(drv_data);
192 flag |= (chip->flag << 8);
194 write_FLAG(drv_data, flag);
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
201 #define MAX_SPI_SSEL 7
203 /* stop controller and re-config current chip*/
204 static void restore_state(struct driver_data *drv_data)
206 struct chip_data *chip = drv_data->cur_chip;
208 /* Clear status and disable clock */
209 write_STAT(drv_data, BIT_STAT_CLR);
210 bfin_spi_disable(drv_data);
211 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
213 /* Load the registers */
214 write_CTRL(drv_data, chip->ctl_reg);
215 write_BAUD(drv_data, chip->baud);
217 bfin_spi_enable(drv_data);
218 cs_active(drv_data, chip);
221 /* used to kick off transfer in rx mode */
222 static unsigned short dummy_read(struct driver_data *drv_data)
225 tmp = read_RDBR(drv_data);
229 static void null_writer(struct driver_data *drv_data)
231 u8 n_bytes = drv_data->n_bytes;
233 while (drv_data->tx < drv_data->tx_end) {
234 write_TDBR(drv_data, 0);
235 while ((read_STAT(drv_data) & BIT_STAT_TXS))
237 drv_data->tx += n_bytes;
241 static void null_reader(struct driver_data *drv_data)
243 u8 n_bytes = drv_data->n_bytes;
244 dummy_read(drv_data);
246 while (drv_data->rx < drv_data->rx_end) {
247 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
249 dummy_read(drv_data);
250 drv_data->rx += n_bytes;
254 static void u8_writer(struct driver_data *drv_data)
256 dev_dbg(&drv_data->pdev->dev,
257 "cr8-s is 0x%x\n", read_STAT(drv_data));
259 while (drv_data->tx < drv_data->tx_end) {
260 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
261 while (read_STAT(drv_data) & BIT_STAT_TXS)
266 /* poll for SPI completion before return */
267 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
271 static void u8_cs_chg_writer(struct driver_data *drv_data)
273 struct chip_data *chip = drv_data->cur_chip;
275 while (drv_data->tx < drv_data->tx_end) {
276 cs_active(drv_data, chip);
278 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
279 while (read_STAT(drv_data) & BIT_STAT_TXS)
281 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
284 cs_deactive(drv_data, chip);
290 static void u8_reader(struct driver_data *drv_data)
292 dev_dbg(&drv_data->pdev->dev,
293 "cr-8 is 0x%x\n", read_STAT(drv_data));
295 /* poll for SPI completion before start */
296 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
299 /* clear TDBR buffer before read(else it will be shifted out) */
300 write_TDBR(drv_data, 0xFFFF);
302 dummy_read(drv_data);
304 while (drv_data->rx < drv_data->rx_end - 1) {
305 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
307 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
311 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
313 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
317 static void u8_cs_chg_reader(struct driver_data *drv_data)
319 struct chip_data *chip = drv_data->cur_chip;
321 while (drv_data->rx < drv_data->rx_end) {
322 cs_active(drv_data, chip);
323 read_RDBR(drv_data); /* kick off */
325 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
327 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
330 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
331 cs_deactive(drv_data, chip);
337 static void u8_duplex(struct driver_data *drv_data)
339 /* in duplex mode, clk is triggered by writing of TDBR */
340 while (drv_data->rx < drv_data->rx_end) {
341 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
342 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
344 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
346 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
352 static void u8_cs_chg_duplex(struct driver_data *drv_data)
354 struct chip_data *chip = drv_data->cur_chip;
356 while (drv_data->rx < drv_data->rx_end) {
357 cs_active(drv_data, chip);
359 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
361 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
363 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
365 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
367 cs_deactive(drv_data, chip);
374 static void u16_writer(struct driver_data *drv_data)
376 dev_dbg(&drv_data->pdev->dev,
377 "cr16 is 0x%x\n", read_STAT(drv_data));
379 while (drv_data->tx < drv_data->tx_end) {
380 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
381 while ((read_STAT(drv_data) & BIT_STAT_TXS))
386 /* poll for SPI completion before return */
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
391 static void u16_cs_chg_writer(struct driver_data *drv_data)
393 struct chip_data *chip = drv_data->cur_chip;
395 while (drv_data->tx < drv_data->tx_end) {
396 cs_active(drv_data, chip);
398 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
399 while ((read_STAT(drv_data) & BIT_STAT_TXS))
401 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
404 cs_deactive(drv_data, chip);
410 static void u16_reader(struct driver_data *drv_data)
412 dev_dbg(&drv_data->pdev->dev,
413 "cr-16 is 0x%x\n", read_STAT(drv_data));
415 /* poll for SPI completion before start */
416 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
419 /* clear TDBR buffer before read(else it will be shifted out) */
420 write_TDBR(drv_data, 0xFFFF);
422 dummy_read(drv_data);
424 while (drv_data->rx < (drv_data->rx_end - 2)) {
425 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
427 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
431 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
433 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
437 static void u16_cs_chg_reader(struct driver_data *drv_data)
439 struct chip_data *chip = drv_data->cur_chip;
441 /* poll for SPI completion before start */
442 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
445 /* clear TDBR buffer before read(else it will be shifted out) */
446 write_TDBR(drv_data, 0xFFFF);
448 cs_active(drv_data, chip);
449 dummy_read(drv_data);
451 while (drv_data->rx < drv_data->rx_end - 2) {
452 cs_deactive(drv_data, chip);
454 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
456 cs_active(drv_data, chip);
457 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
460 cs_deactive(drv_data, chip);
462 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
464 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
468 static void u16_duplex(struct driver_data *drv_data)
470 /* in duplex mode, clk is triggered by writing of TDBR */
471 while (drv_data->tx < drv_data->tx_end) {
472 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
473 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
475 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
477 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
483 static void u16_cs_chg_duplex(struct driver_data *drv_data)
485 struct chip_data *chip = drv_data->cur_chip;
487 while (drv_data->tx < drv_data->tx_end) {
488 cs_active(drv_data, chip);
490 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
491 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
493 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
495 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
497 cs_deactive(drv_data, chip);
504 /* test if ther is more transfer to be done */
505 static void *next_transfer(struct driver_data *drv_data)
507 struct spi_message *msg = drv_data->cur_msg;
508 struct spi_transfer *trans = drv_data->cur_transfer;
510 /* Move to next transfer */
511 if (trans->transfer_list.next != &msg->transfers) {
512 drv_data->cur_transfer =
513 list_entry(trans->transfer_list.next,
514 struct spi_transfer, transfer_list);
515 return RUNNING_STATE;
521 * caller already set message->status;
522 * dma and pio irqs are blocked give finished message back
524 static void giveback(struct driver_data *drv_data)
526 struct chip_data *chip = drv_data->cur_chip;
527 struct spi_transfer *last_transfer;
529 struct spi_message *msg;
531 spin_lock_irqsave(&drv_data->lock, flags);
532 msg = drv_data->cur_msg;
533 drv_data->cur_msg = NULL;
534 drv_data->cur_transfer = NULL;
535 drv_data->cur_chip = NULL;
536 queue_work(drv_data->workqueue, &drv_data->pump_messages);
537 spin_unlock_irqrestore(&drv_data->lock, flags);
539 last_transfer = list_entry(msg->transfers.prev,
540 struct spi_transfer, transfer_list);
544 /* disable chip select signal. And not stop spi in autobuffer mode */
545 if (drv_data->tx_dma != 0xFFFF) {
546 cs_deactive(drv_data, chip);
547 bfin_spi_disable(drv_data);
550 if (!drv_data->cs_change)
551 cs_deactive(drv_data, chip);
554 msg->complete(msg->context);
557 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
559 struct driver_data *drv_data = dev_id;
560 struct chip_data *chip = drv_data->cur_chip;
561 struct spi_message *msg = drv_data->cur_msg;
563 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
564 clear_dma_irqstat(drv_data->dma_channel);
566 /* Wait for DMA to complete */
567 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
571 * wait for the last transaction shifted out. HRM states:
572 * at this point there may still be data in the SPI DMA FIFO waiting
573 * to be transmitted ... software needs to poll TXS in the SPI_STAT
574 * register until it goes low for 2 successive reads
576 if (drv_data->tx != NULL) {
577 while ((read_STAT(drv_data) & TXS) ||
578 (read_STAT(drv_data) & TXS))
582 while (!(read_STAT(drv_data) & SPIF))
585 msg->actual_length += drv_data->len_in_bytes;
587 if (drv_data->cs_change)
588 cs_deactive(drv_data, chip);
590 /* Move to next transfer */
591 msg->state = next_transfer(drv_data);
593 /* Schedule transfer tasklet */
594 tasklet_schedule(&drv_data->pump_transfers);
596 /* free the irq handler before next transfer */
597 dev_dbg(&drv_data->pdev->dev,
598 "disable dma channel irq%d\n",
599 drv_data->dma_channel);
600 dma_disable_irq(drv_data->dma_channel);
605 static void pump_transfers(unsigned long data)
607 struct driver_data *drv_data = (struct driver_data *)data;
608 struct spi_message *message = NULL;
609 struct spi_transfer *transfer = NULL;
610 struct spi_transfer *previous = NULL;
611 struct chip_data *chip = NULL;
613 u16 cr, dma_width, dma_config;
614 u32 tranf_success = 1;
617 /* Get current state information */
618 message = drv_data->cur_msg;
619 transfer = drv_data->cur_transfer;
620 chip = drv_data->cur_chip;
623 * if msg is error or done, report it back using complete() callback
626 /* Handle for abort */
627 if (message->state == ERROR_STATE) {
628 message->status = -EIO;
633 /* Handle end of message */
634 if (message->state == DONE_STATE) {
640 /* Delay if requested at end of transfer */
641 if (message->state == RUNNING_STATE) {
642 previous = list_entry(transfer->transfer_list.prev,
643 struct spi_transfer, transfer_list);
644 if (previous->delay_usecs)
645 udelay(previous->delay_usecs);
648 /* Setup the transfer state based on the type of transfer */
649 if (flush(drv_data) == 0) {
650 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
651 message->status = -EIO;
656 if (transfer->tx_buf != NULL) {
657 drv_data->tx = (void *)transfer->tx_buf;
658 drv_data->tx_end = drv_data->tx + transfer->len;
659 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
660 transfer->tx_buf, drv_data->tx_end);
665 if (transfer->rx_buf != NULL) {
666 full_duplex = transfer->tx_buf != NULL;
667 drv_data->rx = transfer->rx_buf;
668 drv_data->rx_end = drv_data->rx + transfer->len;
669 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
670 transfer->rx_buf, drv_data->rx_end);
675 drv_data->rx_dma = transfer->rx_dma;
676 drv_data->tx_dma = transfer->tx_dma;
677 drv_data->len_in_bytes = transfer->len;
678 drv_data->cs_change = transfer->cs_change;
680 /* Bits per word setup */
681 switch (transfer->bits_per_word) {
683 drv_data->n_bytes = 1;
684 width = CFG_SPI_WORDSIZE8;
685 drv_data->read = chip->cs_change_per_word ?
686 u8_cs_chg_reader : u8_reader;
687 drv_data->write = chip->cs_change_per_word ?
688 u8_cs_chg_writer : u8_writer;
689 drv_data->duplex = chip->cs_change_per_word ?
690 u8_cs_chg_duplex : u8_duplex;
694 drv_data->n_bytes = 2;
695 width = CFG_SPI_WORDSIZE16;
696 drv_data->read = chip->cs_change_per_word ?
697 u16_cs_chg_reader : u16_reader;
698 drv_data->write = chip->cs_change_per_word ?
699 u16_cs_chg_writer : u16_writer;
700 drv_data->duplex = chip->cs_change_per_word ?
701 u16_cs_chg_duplex : u16_duplex;
705 /* No change, the same as default setting */
706 drv_data->n_bytes = chip->n_bytes;
708 drv_data->write = drv_data->tx ? chip->write : null_writer;
709 drv_data->read = drv_data->rx ? chip->read : null_reader;
710 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
713 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
715 write_CTRL(drv_data, cr);
717 if (width == CFG_SPI_WORDSIZE16) {
718 drv_data->len = (transfer->len) >> 1;
720 drv_data->len = transfer->len;
722 dev_dbg(&drv_data->pdev->dev,
723 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
724 drv_data->write, chip->write, null_writer);
726 /* speed and width has been set on per message */
727 message->state = RUNNING_STATE;
730 /* Speed setup (surely valid because already checked) */
731 if (transfer->speed_hz)
732 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
734 write_BAUD(drv_data, chip->baud);
736 write_STAT(drv_data, BIT_STAT_CLR);
737 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
738 cs_active(drv_data, chip);
740 dev_dbg(&drv_data->pdev->dev,
741 "now pumping a transfer: width is %d, len is %d\n",
742 width, transfer->len);
745 * Try to map dma buffer and do a dma transfer. If successful use,
746 * different way to r/w according to the enable_dma settings and if
747 * we are not doing a full duplex transfer (since the hardware does
748 * not support full duplex DMA transfers).
750 if (!full_duplex && drv_data->cur_chip->enable_dma
751 && drv_data->len > 6) {
753 disable_dma(drv_data->dma_channel);
754 clear_dma_irqstat(drv_data->dma_channel);
755 bfin_spi_disable(drv_data);
757 /* config dma channel */
758 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
759 if (width == CFG_SPI_WORDSIZE16) {
760 set_dma_x_count(drv_data->dma_channel, drv_data->len);
761 set_dma_x_modify(drv_data->dma_channel, 2);
762 dma_width = WDSIZE_16;
764 set_dma_x_count(drv_data->dma_channel, drv_data->len);
765 set_dma_x_modify(drv_data->dma_channel, 1);
766 dma_width = WDSIZE_8;
769 /* poll for SPI completion before start */
770 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
773 /* dirty hack for autobuffer DMA mode */
774 if (drv_data->tx_dma == 0xFFFF) {
775 dev_dbg(&drv_data->pdev->dev,
776 "doing autobuffer DMA out.\n");
778 /* no irq in autobuffer mode */
780 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
781 set_dma_config(drv_data->dma_channel, dma_config);
782 set_dma_start_addr(drv_data->dma_channel,
783 (unsigned long)drv_data->tx);
784 enable_dma(drv_data->dma_channel);
786 /* start SPI transfer */
788 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
790 /* just return here, there can only be one transfer
798 /* In dma mode, rx or tx must be NULL in one transfer */
799 if (drv_data->rx != NULL) {
800 /* set transfer mode, and enable SPI */
801 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
803 /* invalidate caches, if needed */
804 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
805 invalidate_dcache_range((unsigned long) drv_data->rx,
806 (unsigned long) (drv_data->rx +
809 /* clear tx reg soformer data is not shifted out */
810 write_TDBR(drv_data, 0xFFFF);
812 set_dma_x_count(drv_data->dma_channel, drv_data->len);
815 dma_enable_irq(drv_data->dma_channel);
816 dma_config = (WNR | RESTART | dma_width | DI_EN);
817 set_dma_config(drv_data->dma_channel, dma_config);
818 set_dma_start_addr(drv_data->dma_channel,
819 (unsigned long)drv_data->rx);
820 enable_dma(drv_data->dma_channel);
822 /* start SPI transfer */
824 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
826 } else if (drv_data->tx != NULL) {
827 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
829 /* flush caches, if needed */
830 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
831 flush_dcache_range((unsigned long) drv_data->tx,
832 (unsigned long) (drv_data->tx +
836 dma_enable_irq(drv_data->dma_channel);
837 dma_config = (RESTART | dma_width | DI_EN);
838 set_dma_config(drv_data->dma_channel, dma_config);
839 set_dma_start_addr(drv_data->dma_channel,
840 (unsigned long)drv_data->tx);
841 enable_dma(drv_data->dma_channel);
843 /* start SPI transfer */
845 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
848 /* IO mode write then read */
849 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
852 /* full duplex mode */
853 BUG_ON((drv_data->tx_end - drv_data->tx) !=
854 (drv_data->rx_end - drv_data->rx));
855 dev_dbg(&drv_data->pdev->dev,
856 "IO duplex: cr is 0x%x\n", cr);
858 /* set SPI transfer mode */
859 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
861 drv_data->duplex(drv_data);
863 if (drv_data->tx != drv_data->tx_end)
865 } else if (drv_data->tx != NULL) {
866 /* write only half duplex */
867 dev_dbg(&drv_data->pdev->dev,
868 "IO write: cr is 0x%x\n", cr);
870 /* set SPI transfer mode */
871 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
873 drv_data->write(drv_data);
875 if (drv_data->tx != drv_data->tx_end)
877 } else if (drv_data->rx != NULL) {
878 /* read only half duplex */
879 dev_dbg(&drv_data->pdev->dev,
880 "IO read: cr is 0x%x\n", cr);
882 /* set SPI transfer mode */
883 write_CTRL(drv_data, (cr | CFG_SPI_READ));
885 drv_data->read(drv_data);
886 if (drv_data->rx != drv_data->rx_end)
890 if (!tranf_success) {
891 dev_dbg(&drv_data->pdev->dev,
892 "IO write error!\n");
893 message->state = ERROR_STATE;
895 /* Update total byte transfered */
896 message->actual_length += drv_data->len;
898 /* Move to next transfer of this msg */
899 message->state = next_transfer(drv_data);
902 /* Schedule next transfer tasklet */
903 tasklet_schedule(&drv_data->pump_transfers);
908 /* pop a msg from queue and kick off real transfer */
909 static void pump_messages(struct work_struct *work)
911 struct driver_data *drv_data;
914 drv_data = container_of(work, struct driver_data, pump_messages);
916 /* Lock queue and check for queue work */
917 spin_lock_irqsave(&drv_data->lock, flags);
918 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
919 /* pumper kicked off but no work to do */
921 spin_unlock_irqrestore(&drv_data->lock, flags);
925 /* Make sure we are not already running a message */
926 if (drv_data->cur_msg) {
927 spin_unlock_irqrestore(&drv_data->lock, flags);
931 /* Extract head of queue */
932 drv_data->cur_msg = list_entry(drv_data->queue.next,
933 struct spi_message, queue);
935 /* Setup the SSP using the per chip configuration */
936 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
937 restore_state(drv_data);
939 list_del_init(&drv_data->cur_msg->queue);
941 /* Initial message state */
942 drv_data->cur_msg->state = START_STATE;
943 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
944 struct spi_transfer, transfer_list);
946 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
947 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
948 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
949 drv_data->cur_chip->ctl_reg);
951 dev_dbg(&drv_data->pdev->dev,
952 "the first transfer len is %d\n",
953 drv_data->cur_transfer->len);
955 /* Mark as busy and launch transfers */
956 tasklet_schedule(&drv_data->pump_transfers);
959 spin_unlock_irqrestore(&drv_data->lock, flags);
963 * got a msg to transfer, queue it in drv_data->queue.
964 * And kick off message pumper
966 static int transfer(struct spi_device *spi, struct spi_message *msg)
968 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
971 spin_lock_irqsave(&drv_data->lock, flags);
973 if (drv_data->run == QUEUE_STOPPED) {
974 spin_unlock_irqrestore(&drv_data->lock, flags);
978 msg->actual_length = 0;
979 msg->status = -EINPROGRESS;
980 msg->state = START_STATE;
982 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
983 list_add_tail(&msg->queue, &drv_data->queue);
985 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
986 queue_work(drv_data->workqueue, &drv_data->pump_messages);
988 spin_unlock_irqrestore(&drv_data->lock, flags);
993 #define MAX_SPI_SSEL 7
995 static u16 ssel[3][MAX_SPI_SSEL] = {
996 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
997 P_SPI0_SSEL4, P_SPI0_SSEL5,
998 P_SPI0_SSEL6, P_SPI0_SSEL7},
1000 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1001 P_SPI1_SSEL4, P_SPI1_SSEL5,
1002 P_SPI1_SSEL6, P_SPI1_SSEL7},
1004 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1005 P_SPI2_SSEL4, P_SPI2_SSEL5,
1006 P_SPI2_SSEL6, P_SPI2_SSEL7},
1009 /* first setup for new devices */
1010 static int setup(struct spi_device *spi)
1012 struct bfin5xx_spi_chip *chip_info = NULL;
1013 struct chip_data *chip;
1014 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1017 /* Abort device setup if requested features are not supported */
1018 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1019 dev_err(&spi->dev, "requested mode not fully supported\n");
1023 /* Zero (the default) here means 8 bits */
1024 if (!spi->bits_per_word)
1025 spi->bits_per_word = 8;
1027 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1030 /* Only alloc (or use chip_info) on first setup */
1031 chip = spi_get_ctldata(spi);
1033 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1037 chip->enable_dma = 0;
1038 chip_info = spi->controller_data;
1041 /* chip_info isn't always needed */
1043 /* Make sure people stop trying to set fields via ctl_reg
1044 * when they should actually be using common SPI framework.
1045 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1046 * Not sure if a user actually needs/uses any of these,
1047 * but let's assume (for now) they do.
1049 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1050 dev_err(&spi->dev, "do not set bits in ctl_reg "
1051 "that the SPI framework manages\n");
1055 chip->enable_dma = chip_info->enable_dma != 0
1056 && drv_data->master_info->enable_dma;
1057 chip->ctl_reg = chip_info->ctl_reg;
1058 chip->bits_per_word = chip_info->bits_per_word;
1059 chip->cs_change_per_word = chip_info->cs_change_per_word;
1060 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1063 /* translate common spi framework into our register */
1064 if (spi->mode & SPI_CPOL)
1065 chip->ctl_reg |= CPOL;
1066 if (spi->mode & SPI_CPHA)
1067 chip->ctl_reg |= CPHA;
1068 if (spi->mode & SPI_LSB_FIRST)
1069 chip->ctl_reg |= LSBF;
1070 /* we dont support running in slave mode (yet?) */
1071 chip->ctl_reg |= MSTR;
1074 * if any one SPI chip is registered and wants DMA, request the
1075 * DMA channel for it
1077 if (chip->enable_dma && !drv_data->dma_requested) {
1078 /* register dma irq handler */
1079 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1081 "Unable to request BlackFin SPI DMA channel\n");
1084 if (set_dma_callback(drv_data->dma_channel,
1085 (void *)dma_irq_handler, drv_data) < 0) {
1086 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1089 dma_disable_irq(drv_data->dma_channel);
1090 drv_data->dma_requested = 1;
1094 * Notice: for blackfin, the speed_hz is the value of register
1095 * SPI_BAUD, not the real baudrate
1097 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1098 spi_flg = ~(1 << (spi->chip_select));
1099 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1100 chip->chip_select_num = spi->chip_select;
1102 switch (chip->bits_per_word) {
1105 chip->width = CFG_SPI_WORDSIZE8;
1106 chip->read = chip->cs_change_per_word ?
1107 u8_cs_chg_reader : u8_reader;
1108 chip->write = chip->cs_change_per_word ?
1109 u8_cs_chg_writer : u8_writer;
1110 chip->duplex = chip->cs_change_per_word ?
1111 u8_cs_chg_duplex : u8_duplex;
1116 chip->width = CFG_SPI_WORDSIZE16;
1117 chip->read = chip->cs_change_per_word ?
1118 u16_cs_chg_reader : u16_reader;
1119 chip->write = chip->cs_change_per_word ?
1120 u16_cs_chg_writer : u16_writer;
1121 chip->duplex = chip->cs_change_per_word ?
1122 u16_cs_chg_duplex : u16_duplex;
1126 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1127 chip->bits_per_word);
1132 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1133 spi->modalias, chip->width, chip->enable_dma);
1134 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1135 chip->ctl_reg, chip->flag);
1137 spi_set_ctldata(spi, chip);
1139 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1140 if ((chip->chip_select_num > 0)
1141 && (chip->chip_select_num <= spi->master->num_chipselect))
1142 peripheral_request(ssel[spi->master->bus_num]
1143 [chip->chip_select_num-1], spi->modalias);
1145 cs_deactive(drv_data, chip);
1151 * callback for spi framework.
1152 * clean driver specific data
1154 static void cleanup(struct spi_device *spi)
1156 struct chip_data *chip = spi_get_ctldata(spi);
1158 if ((chip->chip_select_num > 0)
1159 && (chip->chip_select_num <= spi->master->num_chipselect))
1160 peripheral_free(ssel[spi->master->bus_num]
1161 [chip->chip_select_num-1]);
1166 static inline int init_queue(struct driver_data *drv_data)
1168 INIT_LIST_HEAD(&drv_data->queue);
1169 spin_lock_init(&drv_data->lock);
1171 drv_data->run = QUEUE_STOPPED;
1174 /* init transfer tasklet */
1175 tasklet_init(&drv_data->pump_transfers,
1176 pump_transfers, (unsigned long)drv_data);
1178 /* init messages workqueue */
1179 INIT_WORK(&drv_data->pump_messages, pump_messages);
1180 drv_data->workqueue = create_singlethread_workqueue(
1181 dev_name(drv_data->master->dev.parent));
1182 if (drv_data->workqueue == NULL)
1188 static inline int start_queue(struct driver_data *drv_data)
1190 unsigned long flags;
1192 spin_lock_irqsave(&drv_data->lock, flags);
1194 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1195 spin_unlock_irqrestore(&drv_data->lock, flags);
1199 drv_data->run = QUEUE_RUNNING;
1200 drv_data->cur_msg = NULL;
1201 drv_data->cur_transfer = NULL;
1202 drv_data->cur_chip = NULL;
1203 spin_unlock_irqrestore(&drv_data->lock, flags);
1205 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1210 static inline int stop_queue(struct driver_data *drv_data)
1212 unsigned long flags;
1213 unsigned limit = 500;
1216 spin_lock_irqsave(&drv_data->lock, flags);
1219 * This is a bit lame, but is optimized for the common execution path.
1220 * A wait_queue on the drv_data->busy could be used, but then the common
1221 * execution path (pump_messages) would be required to call wake_up or
1222 * friends on every SPI message. Do this instead
1224 drv_data->run = QUEUE_STOPPED;
1225 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1226 spin_unlock_irqrestore(&drv_data->lock, flags);
1228 spin_lock_irqsave(&drv_data->lock, flags);
1231 if (!list_empty(&drv_data->queue) || drv_data->busy)
1234 spin_unlock_irqrestore(&drv_data->lock, flags);
1239 static inline int destroy_queue(struct driver_data *drv_data)
1243 status = stop_queue(drv_data);
1247 destroy_workqueue(drv_data->workqueue);
1252 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1254 struct device *dev = &pdev->dev;
1255 struct bfin5xx_spi_master *platform_info;
1256 struct spi_master *master;
1257 struct driver_data *drv_data = 0;
1258 struct resource *res;
1261 platform_info = dev->platform_data;
1263 /* Allocate master with space for drv_data */
1264 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1266 dev_err(&pdev->dev, "can not alloc spi_master\n");
1270 drv_data = spi_master_get_devdata(master);
1271 drv_data->master = master;
1272 drv_data->master_info = platform_info;
1273 drv_data->pdev = pdev;
1274 drv_data->pin_req = platform_info->pin_req;
1276 master->bus_num = pdev->id;
1277 master->num_chipselect = platform_info->num_chipselect;
1278 master->cleanup = cleanup;
1279 master->setup = setup;
1280 master->transfer = transfer;
1282 /* Find and map our resources */
1283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1287 goto out_error_get_res;
1290 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1291 if (drv_data->regs_base == NULL) {
1292 dev_err(dev, "Cannot map IO\n");
1294 goto out_error_ioremap;
1297 drv_data->dma_channel = platform_get_irq(pdev, 0);
1298 if (drv_data->dma_channel < 0) {
1299 dev_err(dev, "No DMA channel specified\n");
1301 goto out_error_no_dma_ch;
1304 /* Initial and start queue */
1305 status = init_queue(drv_data);
1307 dev_err(dev, "problem initializing queue\n");
1308 goto out_error_queue_alloc;
1311 status = start_queue(drv_data);
1313 dev_err(dev, "problem starting queue\n");
1314 goto out_error_queue_alloc;
1317 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1319 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1320 goto out_error_queue_alloc;
1323 /* Register with the SPI framework */
1324 platform_set_drvdata(pdev, drv_data);
1325 status = spi_register_master(master);
1327 dev_err(dev, "problem registering spi master\n");
1328 goto out_error_queue_alloc;
1331 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1332 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1333 drv_data->dma_channel);
1336 out_error_queue_alloc:
1337 destroy_queue(drv_data);
1338 out_error_no_dma_ch:
1339 iounmap((void *) drv_data->regs_base);
1342 spi_master_put(master);
1347 /* stop hardware and remove the driver */
1348 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1350 struct driver_data *drv_data = platform_get_drvdata(pdev);
1356 /* Remove the queue */
1357 status = destroy_queue(drv_data);
1361 /* Disable the SSP at the peripheral and SOC level */
1362 bfin_spi_disable(drv_data);
1365 if (drv_data->master_info->enable_dma) {
1366 if (dma_channel_active(drv_data->dma_channel))
1367 free_dma(drv_data->dma_channel);
1370 /* Disconnect from the SPI framework */
1371 spi_unregister_master(drv_data->master);
1373 peripheral_free_list(drv_data->pin_req);
1375 /* Prevent double remove */
1376 platform_set_drvdata(pdev, NULL);
1382 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1384 struct driver_data *drv_data = platform_get_drvdata(pdev);
1387 status = stop_queue(drv_data);
1392 bfin_spi_disable(drv_data);
1397 static int bfin5xx_spi_resume(struct platform_device *pdev)
1399 struct driver_data *drv_data = platform_get_drvdata(pdev);
1402 /* Enable the SPI interface */
1403 bfin_spi_enable(drv_data);
1405 /* Start the queue running */
1406 status = start_queue(drv_data);
1408 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1415 #define bfin5xx_spi_suspend NULL
1416 #define bfin5xx_spi_resume NULL
1417 #endif /* CONFIG_PM */
1419 MODULE_ALIAS("platform:bfin-spi");
1420 static struct platform_driver bfin5xx_spi_driver = {
1423 .owner = THIS_MODULE,
1425 .suspend = bfin5xx_spi_suspend,
1426 .resume = bfin5xx_spi_resume,
1427 .remove = __devexit_p(bfin5xx_spi_remove),
1430 static int __init bfin5xx_spi_init(void)
1432 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1434 module_init(bfin5xx_spi_init);
1436 static void __exit bfin5xx_spi_exit(void)
1438 platform_driver_unregister(&bfin5xx_spi_driver);
1440 module_exit(bfin5xx_spi_exit);