3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
8 * Copyright 2004 Embedded Edge, LLC
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/config.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/module.h>
43 #include <asm/mach-au1x00/au1000.h>
44 #include <asm/mach-au1x00/au1xxx_dbdma.h>
45 #include <asm/system.h>
48 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
51 * The Descriptor Based DMA supports up to 16 channels.
53 * There are 32 devices defined. We keep an internal structure
54 * of devices using these channels, along with additional
57 * We allocate the descriptors and allow access to them through various
58 * functions. The drivers allocate the data buffers and assign them
61 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
63 /* I couldn't find a macro that did this......
65 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
67 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
68 static int dbdma_initialized=0;
69 static void au1xxx_dbdma_init(void);
71 static dbdev_tab_t dbdev_tab[] = {
72 #ifdef CONFIG_SOC_AU1550
74 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
75 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
76 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
77 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
80 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
81 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
82 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
83 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
86 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
87 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
88 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
89 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
90 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
91 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
94 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
95 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
98 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
99 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
102 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
103 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
106 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
107 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
109 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
110 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
113 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
114 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
117 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
118 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
120 #endif /* CONFIG_SOC_AU1550 */
122 #ifdef CONFIG_SOC_AU1200
123 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
124 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
125 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
126 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
128 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
129 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
131 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
133 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
134 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
136 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
137 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
138 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
139 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
141 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
142 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
144 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
145 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
146 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
149 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
150 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
152 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
153 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
154 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
155 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
157 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
159 #endif // CONFIG_SOC_AU1200
161 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
162 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
164 /* Provide 16 user definable device types */
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
180 { 0, 0, 0, 0, 0, 0, 0 },
183 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
185 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
188 find_dbdev_id (u32 id)
192 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
200 void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
202 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
204 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
207 au1xxx_ddma_add_device(dbdev_tab_t *dev)
211 static u16 new_id=0x1000;
213 p = find_dbdev_id(0);
216 memcpy(p, dev, sizeof(dbdev_tab_t));
217 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
221 printk("add_device: id:%x flags:%x padd:%x\n",
222 p->dev_id, p->dev_flags, p->dev_physaddr );
228 EXPORT_SYMBOL(au1xxx_ddma_add_device);
230 /* Allocate a channel and return a non-zero descriptor if successful.
233 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
234 void (*callback)(int, void *, struct pt_regs *), void *callparam)
240 dbdev_tab_t *stp, *dtp;
244 /* We do the intialization on the first channel allocation.
245 * We have to wait because of the interrupt handler initialization
246 * which can't be done successfully during board set up.
248 if (!dbdma_initialized)
250 dbdma_initialized = 1;
252 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
253 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
258 /* Check to see if we can get both channels.
260 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
261 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
262 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
264 stp->dev_flags |= DEV_FLAGS_INUSE;
265 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
266 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
267 /* Got destination */
268 dtp->dev_flags |= DEV_FLAGS_INUSE;
271 /* Can't get dest. Release src.
273 stp->dev_flags &= ~DEV_FLAGS_INUSE;
280 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
283 /* Let's see if we can allocate a channel for it.
287 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
288 for (i=0; i<NUM_DBDMA_CHANS; i++) {
289 if (chan_tab_ptr[i] == NULL) {
290 /* If kmalloc fails, it is caught below same
291 * as a channel not available.
293 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
294 chan_tab_ptr[i] = ctp;
298 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
301 memset(ctp, 0, sizeof(chan_tab_t));
302 ctp->chan_index = chan = i;
303 dcp = DDMA_CHANNEL_BASE;
304 dcp += (0x0100 * chan);
305 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
306 cp = (au1x_dma_chan_t *)dcp;
308 ctp->chan_dest = dtp;
309 ctp->chan_callback = callback;
310 ctp->chan_callparam = callparam;
312 /* Initialize channel configuration.
315 if (stp->dev_intlevel)
317 if (stp->dev_intpolarity)
319 if (dtp->dev_intlevel)
321 if (dtp->dev_intpolarity)
323 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
324 (dtp->dev_flags & DEV_FLAGS_SYNC))
329 /* Return a non-zero value that can be used to
330 * find the channel information in subsequent
333 rv = (u32)(&chan_tab_ptr[chan]);
336 /* Release devices */
337 stp->dev_flags &= ~DEV_FLAGS_INUSE;
338 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
343 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
345 /* Set the device width if source or destination is a FIFO.
346 * Should be 8, 16, or 32 bits.
349 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
353 dbdev_tab_t *stp, *dtp;
355 ctp = *((chan_tab_t **)chanid);
357 dtp = ctp->chan_dest;
360 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
361 rv = stp->dev_devwidth;
362 stp->dev_devwidth = bits;
364 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
365 rv = dtp->dev_devwidth;
366 dtp->dev_devwidth = bits;
371 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
373 /* Allocate a descriptor ring, initializing as much as possible.
376 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
379 u32 desc_base, srcid, destid;
380 u32 cmd0, cmd1, src1, dest1;
383 dbdev_tab_t *stp, *dtp;
384 au1x_ddma_desc_t *dp;
386 /* I guess we could check this to be within the
387 * range of the table......
389 ctp = *((chan_tab_t **)chanid);
391 dtp = ctp->chan_dest;
393 /* The descriptors must be 32-byte aligned. There is a
394 * possibility the allocation will give us such an address,
395 * and if we try that first we are likely to not waste larger
398 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
403 if (desc_base & 0x1f) {
404 /* Lost....do it again, allocate extra, and round
407 kfree((const void *)desc_base);
408 i = entries * sizeof(au1x_ddma_desc_t);
409 i += (sizeof(au1x_ddma_desc_t) - 1);
410 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
413 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
415 dp = (au1x_ddma_desc_t *)desc_base;
417 /* Keep track of the base descriptor.
419 ctp->chan_desc_base = dp;
421 /* Initialize the rings with as much information as we know.
424 destid = dtp->dev_id;
426 cmd0 = cmd1 = src1 = dest1 = 0;
429 cmd0 |= DSCR_CMD0_SID(srcid);
430 cmd0 |= DSCR_CMD0_DID(destid);
431 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
432 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
434 /* is it mem to mem transfer? */
435 if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
436 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
437 cmd0 |= DSCR_CMD0_MEM;
440 switch (stp->dev_devwidth) {
442 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
445 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
449 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
453 switch (dtp->dev_devwidth) {
455 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
458 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
462 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
466 /* If the device is marked as an in/out FIFO, ensure it is
469 if (stp->dev_flags & DEV_FLAGS_IN)
470 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
471 if (dtp->dev_flags & DEV_FLAGS_OUT)
472 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
474 /* Set up source1. For now, assume no stride and increment.
475 * A channel attribute update can change this later.
477 switch (stp->dev_tsize) {
479 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
482 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
485 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
489 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
493 /* If source input is fifo, set static address.
495 if (stp->dev_flags & DEV_FLAGS_IN) {
496 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
497 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
499 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
502 if (stp->dev_physaddr)
503 src0 = stp->dev_physaddr;
505 /* Set up dest1. For now, assume no stride and increment.
506 * A channel attribute update can change this later.
508 switch (dtp->dev_tsize) {
510 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
513 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
516 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
520 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
524 /* If destination output is fifo, set static address.
526 if (dtp->dev_flags & DEV_FLAGS_OUT) {
527 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
528 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
530 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
532 if (dtp->dev_physaddr)
533 dest0 = dtp->dev_physaddr;
536 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
537 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
539 for (i=0; i<entries; i++) {
540 dp->dscr_cmd0 = cmd0;
541 dp->dscr_cmd1 = cmd1;
542 dp->dscr_source0 = src0;
543 dp->dscr_source1 = src1;
544 dp->dscr_dest0 = dest0;
545 dp->dscr_dest1 = dest1;
549 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
553 /* Make last descrptor point to the first.
556 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
557 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
559 return (u32)(ctp->chan_desc_base);
561 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
563 /* Put a source buffer into the DMA ring.
564 * This updates the source pointer and byte count. Normally used
565 * for memory to fifo transfers.
568 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
571 au1x_ddma_desc_t *dp;
573 /* I guess we could check this to be within the
574 * range of the table......
576 ctp = *((chan_tab_t **)chanid);
578 /* We should have multiple callers for a particular channel,
579 * an interrupt doesn't affect this pointer nor the descriptor,
580 * so no locking should be needed.
584 /* If the descriptor is valid, we are way ahead of the DMA
585 * engine, so just return an error condition.
587 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
591 /* Load up buffer address and byte count.
593 dp->dscr_source0 = virt_to_phys(buf);
594 dp->dscr_cmd1 = nbytes;
596 if (flags & DDMA_FLAGS_IE)
597 dp->dscr_cmd0 |= DSCR_CMD0_IE;
598 if (flags & DDMA_FLAGS_NOIE)
599 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
602 * There is an errata on the Au1200/Au1550 parts that could result
603 * in "stale" data being DMA'd. It has to do with the snoop logic on
604 * the dache eviction buffer. NONCOHERENT_IO is on by default for
605 * these parts. If it is fixedin the future, these dma_cache_inv will
606 * just be nothing more than empty macros. See io.h.
608 dma_cache_wback_inv((unsigned long)buf, nbytes);
609 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
611 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
612 ctp->chan_ptr->ddma_dbell = 0;
614 /* Get next descriptor pointer.
616 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
618 /* return something not zero.
622 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
624 /* Put a destination buffer into the DMA ring.
625 * This updates the destination pointer and byte count. Normally used
626 * to place an empty buffer into the ring for fifo to memory transfers.
629 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
632 au1x_ddma_desc_t *dp;
634 /* I guess we could check this to be within the
635 * range of the table......
637 ctp = *((chan_tab_t **)chanid);
639 /* We should have multiple callers for a particular channel,
640 * an interrupt doesn't affect this pointer nor the descriptor,
641 * so no locking should be needed.
645 /* If the descriptor is valid, we are way ahead of the DMA
646 * engine, so just return an error condition.
648 if (dp->dscr_cmd0 & DSCR_CMD0_V)
651 /* Load up buffer address and byte count */
654 if (flags & DDMA_FLAGS_IE)
655 dp->dscr_cmd0 |= DSCR_CMD0_IE;
656 if (flags & DDMA_FLAGS_NOIE)
657 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
659 dp->dscr_dest0 = virt_to_phys(buf);
660 dp->dscr_cmd1 = nbytes;
662 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
663 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
664 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
667 * There is an errata on the Au1200/Au1550 parts that could result in
668 * "stale" data being DMA'd. It has to do with the snoop logic on the
669 * dache eviction buffer. NONCOHERENT_IO is on by default for these
670 * parts. If it is fixedin the future, these dma_cache_inv will just
671 * be nothing more than empty macros. See io.h.
673 dma_cache_inv((unsigned long)buf,nbytes);
674 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
676 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
677 ctp->chan_ptr->ddma_dbell = 0;
679 /* Get next descriptor pointer.
681 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
683 /* return something not zero.
687 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
689 /* Get a destination buffer into the DMA ring.
690 * Normally used to get a full buffer from the ring during fifo
691 * to memory transfers. This does not set the valid bit, you will
692 * have to put another destination buffer to keep the DMA going.
695 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
698 au1x_ddma_desc_t *dp;
701 /* I guess we could check this to be within the
702 * range of the table......
704 ctp = *((chan_tab_t **)chanid);
706 /* We should have multiple callers for a particular channel,
707 * an interrupt doesn't affect this pointer nor the descriptor,
708 * so no locking should be needed.
712 /* If the descriptor is valid, we are way ahead of the DMA
713 * engine, so just return an error condition.
715 if (dp->dscr_cmd0 & DSCR_CMD0_V)
718 /* Return buffer address and byte count.
720 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
721 *nbytes = dp->dscr_cmd1;
724 /* Get next descriptor pointer.
726 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
728 /* return something not zero.
733 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
736 au1xxx_dbdma_stop(u32 chanid)
740 int halt_timeout = 0;
742 ctp = *((chan_tab_t **)chanid);
745 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
747 while (!(cp->ddma_stat & DDMA_STAT_H)) {
750 if (halt_timeout > 100) {
751 printk("warning: DMA channel won't halt\n");
755 /* clear current desc valid and doorbell */
756 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
759 EXPORT_SYMBOL(au1xxx_dbdma_stop);
761 /* Start using the current descriptor pointer. If the dbdma encounters
762 * a not valid descriptor, it will stop. In this case, we can just
763 * continue by adding a buffer to the list and starting again.
766 au1xxx_dbdma_start(u32 chanid)
771 ctp = *((chan_tab_t **)chanid);
773 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
774 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
779 EXPORT_SYMBOL(au1xxx_dbdma_start);
782 au1xxx_dbdma_reset(u32 chanid)
785 au1x_ddma_desc_t *dp;
787 au1xxx_dbdma_stop(chanid);
789 ctp = *((chan_tab_t **)chanid);
790 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
792 /* Run through the descriptors and reset the valid indicator.
794 dp = ctp->chan_desc_base;
797 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
798 /* reset our SW status -- this is used to determine
799 * if a descriptor is in use by upper level SW. Since
800 * posting can reset 'V' bit.
803 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
804 } while (dp != ctp->chan_desc_base);
806 EXPORT_SYMBOL(au1xxx_dbdma_reset);
809 au1xxx_get_dma_residue(u32 chanid)
815 ctp = *((chan_tab_t **)chanid);
818 /* This is only valid if the channel is stopped.
820 rv = cp->ddma_bytecnt;
826 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
829 au1xxx_dbdma_chan_free(u32 chanid)
832 dbdev_tab_t *stp, *dtp;
834 ctp = *((chan_tab_t **)chanid);
836 dtp = ctp->chan_dest;
838 au1xxx_dbdma_stop(chanid);
840 kfree((void *)ctp->chan_desc_base);
842 stp->dev_flags &= ~DEV_FLAGS_INUSE;
843 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
844 chan_tab_ptr[ctp->chan_index] = NULL;
848 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
851 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
856 au1x_ddma_desc_t *dp;
859 intstat = dbdma_gptr->ddma_intstat;
861 chan_index = au_ffs(intstat) - 1;
863 ctp = chan_tab_ptr[chan_index];
872 if (ctp->chan_callback)
873 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
875 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
876 return IRQ_RETVAL(1);
879 static void au1xxx_dbdma_init(void)
883 dbdma_gptr->ddma_config = 0;
884 dbdma_gptr->ddma_throttle = 0;
885 dbdma_gptr->ddma_inten = 0xffff;
888 #if defined(CONFIG_SOC_AU1550)
889 irq_nr = AU1550_DDMA_INT;
890 #elif defined(CONFIG_SOC_AU1200)
891 irq_nr = AU1200_DDMA_INT;
893 #error Unknown Au1x00 SOC
896 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
897 "Au1xxx dbdma", (void *)dbdma_gptr))
898 printk("Can't get 1550 dbdma irq");
902 au1xxx_dbdma_dump(u32 chanid)
905 au1x_ddma_desc_t *dp;
906 dbdev_tab_t *stp, *dtp;
910 ctp = *((chan_tab_t **)chanid);
912 dtp = ctp->chan_dest;
915 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
916 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
917 printk("desc base %x, get %x, put %x, cur %x\n",
918 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
919 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
921 printk("dbdma chan %x\n", (u32)cp);
922 printk("cfg %08x, desptr %08x, statptr %08x\n",
923 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
924 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
925 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
928 /* Run through the descriptors
930 dp = ctp->chan_desc_base;
933 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
934 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
935 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
936 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
937 printk("stat %08x, nxtptr %08x\n",
938 dp->dscr_stat, dp->dscr_nxtptr);
939 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
940 } while (dp != ctp->chan_desc_base);
943 /* Put a descriptor into the DMA ring.
944 * This updates the source/destination pointers and byte count.
947 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
950 au1x_ddma_desc_t *dp;
953 /* I guess we could check this to be within the
954 * range of the table......
956 ctp = *((chan_tab_t **)chanid);
958 /* We should have multiple callers for a particular channel,
959 * an interrupt doesn't affect this pointer nor the descriptor,
960 * so no locking should be needed.
964 /* If the descriptor is valid, we are way ahead of the DMA
965 * engine, so just return an error condition.
967 if (dp->dscr_cmd0 & DSCR_CMD0_V)
970 /* Load up buffer addresses and byte count.
972 dp->dscr_dest0 = dscr->dscr_dest0;
973 dp->dscr_source0 = dscr->dscr_source0;
974 dp->dscr_dest1 = dscr->dscr_dest1;
975 dp->dscr_source1 = dscr->dscr_source1;
976 dp->dscr_cmd1 = dscr->dscr_cmd1;
977 nbytes = dscr->dscr_cmd1;
978 /* Allow the caller to specifiy if an interrupt is generated */
979 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
980 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
981 ctp->chan_ptr->ddma_dbell = 0;
983 /* Get next descriptor pointer.
985 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
987 /* return something not zero.
992 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */