2 * BRIEF MODULE DESCRIPTION
3 * Au1000 Power Management routines.
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
9 * Some of the routines are right out of init/main.c, whose
10 * copyrights apply here.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/config.h>
33 #include <linux/init.h>
35 #include <linux/pm_legacy.h>
36 #include <linux/slab.h>
37 #include <linux/sysctl.h>
38 #include <linux/jiffies.h>
40 #include <asm/string.h>
41 #include <asm/uaccess.h>
43 #include <asm/system.h>
44 #include <asm/cacheflush.h>
45 #include <asm/mach-au1x00/au1000.h>
51 # define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
53 # define DPRINTK(fmt, args...)
56 static void au1000_calibrate_delay(void);
58 extern void set_au1x00_speed(unsigned int new_freq);
59 extern unsigned int get_au1x00_speed(void);
60 extern unsigned long get_au1x00_uart_baud_base(void);
61 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
62 extern unsigned long save_local_and_disable(int controller);
63 extern void restore_local_and_enable(int controller, unsigned long mask);
64 extern void local_enable_irq(unsigned int irq_nr);
66 /* Quick acpi hack. This will have to change! */
68 #define ACPI_S1_SLP_TYP 19
72 static DEFINE_SPINLOCK(pm_lock);
74 /* We need to save/restore a bunch of core registers that are
75 * either volatile or reset to some state across a processor sleep.
76 * If reading a register doesn't provide a proper result for a
77 * later restore, we have to provide a function for loading that
78 * register and save a copy.
80 * We only have to save/restore registers that aren't otherwise
81 * done as part of a driver pm_* function.
83 static unsigned int sleep_aux_pll_cntrl;
84 static unsigned int sleep_cpu_pll_cntrl;
85 static unsigned int sleep_pin_function;
86 static unsigned int sleep_uart0_inten;
87 static unsigned int sleep_uart0_fifoctl;
88 static unsigned int sleep_uart0_linectl;
89 static unsigned int sleep_uart0_clkdiv;
90 static unsigned int sleep_uart0_enable;
91 static unsigned int sleep_usbhost_enable;
92 static unsigned int sleep_usbdev_enable;
93 static unsigned int sleep_static_memctlr[4][3];
95 /* Define this to cause the value you write to /proc/sys/pm/sleep to
96 * set the TOY timer for the amount of time you want to sleep.
97 * This is done mainly for testing, but may be useful in other cases.
98 * The value is number of 32KHz ticks to sleep.
100 #define SLEEP_TEST_TIMEOUT 1
101 #ifdef SLEEP_TEST_TIMEOUT
102 static int sleep_ticks;
103 void wakeup_counter0_set(int ticks);
109 extern void save_au1xxx_intctl(void);
110 extern void pm_eth0_shutdown(void);
112 /* Do the serial ports.....these really should be a pm_*
113 * registered function by the driver......but of course the
114 * standard serial driver doesn't understand our Au1xxx
117 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
118 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
119 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
120 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
121 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
123 /* Shutdown USB host/device.
125 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
127 /* There appears to be some undocumented reset register....
129 au_writel(0, 0xb0100004); au_sync();
130 au_writel(0, USB_HOST_CONFIG); au_sync();
132 sleep_usbdev_enable = au_readl(USBD_ENABLE);
133 au_writel(0, USBD_ENABLE); au_sync();
135 /* Save interrupt controller state.
137 save_au1xxx_intctl();
141 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
143 /* We don't really need to do this one, but unless we
144 * write it again it won't have a valid value if we
147 sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
149 sleep_pin_function = au_readl(SYS_PINFUNC);
151 /* Save the static memory controller configuration.
153 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
154 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
155 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
156 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
157 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
158 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
159 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
160 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
161 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
162 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
163 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
164 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
168 restore_core_regs(void)
170 extern void restore_au1xxx_intctl(void);
171 extern void wakeup_counter0_adjust(void);
173 au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync();
174 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
175 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
177 /* Restore the static memory controller configuration.
179 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
180 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
181 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
182 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
183 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
184 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
185 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
186 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
187 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
188 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
189 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
190 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
192 /* Enable the UART if it was enabled before sleep.
193 * I guess I should define module control bits........
195 if (sleep_uart0_enable & 0x02) {
196 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
197 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
198 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
199 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
200 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
201 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
202 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
205 restore_au1xxx_intctl();
206 wakeup_counter0_adjust();
209 unsigned long suspend_mode;
211 void wakeup_from_suspend(void)
218 unsigned long wakeup, flags;
219 extern void save_and_sleep(void);
221 spin_lock_irqsave(&pm_lock,flags);
227 /** The code below is all system dependent and we should probably
228 ** have a function call out of here to set this up. You need
229 ** to configure the GPIO or timer interrupts that will bring
231 ** For testing, the TOY counter wakeup is useful.
235 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
237 /* gpio 6 can cause a wake up event */
238 wakeup = au_readl(SYS_WAKEMSK);
239 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
240 wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
242 /* For testing, allow match20 to wake us up.
244 #ifdef SLEEP_TEST_TIMEOUT
245 wakeup_counter0_set(sleep_ticks);
247 wakeup = 1 << 8; /* turn on match20 wakeup */
250 au_writel(1, SYS_WAKESRC); /* clear cause */
252 au_writel(wakeup, SYS_WAKEMSK);
257 /* after a wakeup, the cpu vectors back to 0x1fc00000 so
258 * it's up to the boot code to get us back here.
261 spin_unlock_irqrestore(&pm_lock, flags);
265 static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
266 void __user *buffer, size_t * len, loff_t *ppos)
269 #ifdef SLEEP_TEST_TIMEOUT
270 #define TMPBUFLEN2 16
271 char buf[TMPBUFLEN2], *p;
277 #ifdef SLEEP_TEST_TIMEOUT
278 if (*len > TMPBUFLEN2 - 1) {
281 if (copy_from_user(buf, buffer, *len)) {
286 sleep_ticks = simple_strtoul(p, &p, 0);
288 retval = pm_send_all(PM_SUSPEND, (void *) 2);
294 retval = pm_send_all(PM_RESUME, (void *) 0);
299 static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
300 void __user *buffer, size_t * len, loff_t *ppos)
307 retval = pm_send_all(PM_SUSPEND, (void *) 2);
312 retval = pm_send_all(PM_RESUME, (void *) 0);
318 static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
319 void __user *buffer, size_t * len, loff_t *ppos)
322 unsigned long val, pll;
324 #define MAX_CPU_FREQ 396
325 char buf[TMPBUFLEN], *p;
326 unsigned long flags, intc0_mask, intc1_mask;
327 unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
329 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
331 spin_lock_irqsave(&pm_lock, flags);
335 /* Parse the new frequency */
336 if (*len > TMPBUFLEN - 1) {
337 spin_unlock_irqrestore(&pm_lock, flags);
340 if (copy_from_user(buf, buffer, *len)) {
341 spin_unlock_irqrestore(&pm_lock, flags);
346 val = simple_strtoul(p, &p, 0);
347 if (val > MAX_CPU_FREQ) {
348 spin_unlock_irqrestore(&pm_lock, flags);
353 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
354 /* revisit this for higher speed cpus */
355 spin_unlock_irqrestore(&pm_lock, flags);
359 old_baud_base = get_au1x00_uart_baud_base();
360 old_cpu_freq = get_au1x00_speed();
362 new_cpu_freq = pll * 12 * 1000000;
363 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
364 set_au1x00_speed(new_cpu_freq);
365 set_au1x00_uart_baud_base(new_baud_base);
367 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
369 ((old_refresh * new_cpu_freq) /
370 old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
372 au_writel(pll, SYS_CPUPLL);
374 au_writel(new_refresh, MEM_SDREFCFG);
377 for (i = 0; i < 4; i++) {
379 (UART_BASE + UART_MOD_CNTRL +
380 i * 0x00100000) == 3) {
382 au_readl(UART_BASE + UART_CLK +
384 // baud_rate = baud_base/clk
385 baud_rate = old_baud_base / old_clk;
386 /* we won't get an exact baud rate and the error
387 * could be significant enough that our new
388 * calculation will result in a clock that will
389 * give us a baud rate that's too far off from
390 * what we really want.
392 if (baud_rate > 100000)
394 else if (baud_rate > 50000)
396 else if (baud_rate > 30000)
398 else if (baud_rate > 17000)
402 // new_clk = new_baud_base/baud_rate
403 new_clk = new_baud_base / baud_rate;
405 UART_BASE + UART_CLK +
413 /* We don't want _any_ interrupts other than
414 * match20. Otherwise our au1000_calibrate_delay()
415 * calculation will be off, potentially a lot.
417 intc0_mask = save_local_and_disable(0);
418 intc1_mask = save_local_and_disable(1);
419 local_enable_irq(AU1000_TOY_MATCH2_INT);
420 spin_unlock_irqrestore(&pm_lock, flags);
421 au1000_calibrate_delay();
422 restore_local_and_enable(0, intc0_mask);
423 restore_local_and_enable(1, intc1_mask);
428 static struct ctl_table pm_table[] = {
429 {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
430 {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
431 {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
435 static struct ctl_table pm_dir_table[] = {
436 {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
441 * Initialize power interface
443 static int __init pm_init(void)
445 register_sysctl_table(pm_dir_table, 1);
453 * This is right out of init/main.c
456 /* This is the number of bits of precision for the loops_per_jiffy. Each
457 bit takes on average 1.5/HZ seconds. This (like the original) is a little
461 static void au1000_calibrate_delay(void)
463 unsigned long ticks, loopbit;
464 int lps_precision = LPS_PREC;
466 loops_per_jiffy = (1 << 12);
468 while (loops_per_jiffy <<= 1) {
469 /* wait for "start of" clock tick */
471 while (ticks == jiffies)
475 __delay(loops_per_jiffy);
476 ticks = jiffies - ticks;
481 /* Do a binary approximation to get loops_per_jiffy set to equal one clock
482 (up to lps_precision bits) */
483 loops_per_jiffy >>= 1;
484 loopbit = loops_per_jiffy;
485 while (lps_precision-- && (loopbit >>= 1)) {
486 loops_per_jiffy |= loopbit;
488 while (ticks == jiffies);
490 __delay(loops_per_jiffy);
491 if (jiffies != ticks) /* longer than 1 tick */
492 loops_per_jiffy &= ~loopbit;
495 #endif /* CONFIG_PM */