2 * GE Fanuc SBC610 Device Tree Source
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
25 compatible = "gef,sbc610";
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
88 compatible = "gef,fpga-regs";
93 compatible = "gef,fpga-wdt";
94 reg = <0x4 0x2000 0x8>;
95 interrupts = <0x1a 0x4>;
96 interrupt-parent = <&gef_pic>;
98 /* Second watchdog available, driver currently supports one.
100 compatible = "gef,fpga-wdt";
101 reg = <0x4 0x2010 0x8>;
102 interrupts = <0x1b 0x4>;
103 interrupt-parent = <&gef_pic>;
106 gef_pic: pic@4,4000 {
107 #interrupt-cells = <1>;
108 interrupt-controller;
109 compatible = "gef,fpga-pic";
110 reg = <0x4 0x4000 0x20>;
113 interrupt-parent = <&mpic>;
116 gef_gpio: gpio@7,14000 {
118 compatible = "gef,sbc610-gpio";
119 reg = <0x7 0x14000 0x24>;
125 #address-cells = <1>;
127 #interrupt-cells = <2>;
129 compatible = "simple-bus";
130 ranges = <0x0 0xfef00000 0x00100000>;
131 bus-frequency = <33333333>;
134 compatible = "fsl,mcm-law";
140 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
141 reg = <0x1000 0x1000>;
143 interrupt-parent = <&mpic>;
147 #address-cells = <1>;
149 compatible = "fsl-i2c";
150 reg = <0x3000 0x100>;
151 interrupts = <0x2b 0x2>;
152 interrupt-parent = <&mpic>;
156 compatible = "epson,rx8581";
161 compatible = "dallas,ds1682";
167 #address-cells = <1>;
169 compatible = "fsl-i2c";
170 reg = <0x3100 0x100>;
171 interrupts = <0x2b 0x2>;
172 interrupt-parent = <&mpic>;
177 #address-cells = <1>;
179 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
181 ranges = <0x0 0x21100 0x200>;
184 compatible = "fsl,mpc8641-dma-channel",
185 "fsl,eloplus-dma-channel";
188 interrupt-parent = <&mpic>;
192 compatible = "fsl,mpc8641-dma-channel",
193 "fsl,eloplus-dma-channel";
196 interrupt-parent = <&mpic>;
200 compatible = "fsl,mpc8641-dma-channel",
201 "fsl,eloplus-dma-channel";
204 interrupt-parent = <&mpic>;
208 compatible = "fsl,mpc8641-dma-channel",
209 "fsl,eloplus-dma-channel";
212 interrupt-parent = <&mpic>;
217 enet0: ethernet@24000 {
218 #address-cells = <1>;
220 device_type = "network";
222 compatible = "gianfar";
223 reg = <0x24000 0x1000>;
224 ranges = <0x0 0x24000 0x1000>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
227 interrupt-parent = <&mpic>;
228 phy-handle = <&phy0>;
229 phy-connection-type = "gmii";
232 #address-cells = <1>;
234 compatible = "fsl,gianfar-mdio";
237 phy0: ethernet-phy@0 {
238 interrupt-parent = <&gef_pic>;
239 interrupts = <0x9 0x4>;
242 phy2: ethernet-phy@2 {
243 interrupt-parent = <&gef_pic>;
244 interrupts = <0x8 0x4>;
250 enet1: ethernet@26000 {
251 device_type = "network";
253 compatible = "gianfar";
254 reg = <0x26000 0x1000>;
255 local-mac-address = [ 00 00 00 00 00 00 ];
256 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
257 interrupt-parent = <&mpic>;
258 phy-handle = <&phy2>;
259 phy-connection-type = "gmii";
262 serial0: serial@4500 {
264 device_type = "serial";
265 compatible = "ns16550";
266 reg = <0x4500 0x100>;
267 clock-frequency = <0>;
268 interrupts = <0x2a 0x2>;
269 interrupt-parent = <&mpic>;
272 serial1: serial@4600 {
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0x4600 0x100>;
277 clock-frequency = <0>;
278 interrupts = <0x1c 0x2>;
279 interrupt-parent = <&mpic>;
283 clock-frequency = <0>;
284 interrupt-controller;
285 #address-cells = <0>;
286 #interrupt-cells = <2>;
287 reg = <0x40000 0x40000>;
288 compatible = "chrp,open-pic";
289 device_type = "open-pic";
292 global-utilities@e0000 {
293 compatible = "fsl,mpc8641-guts";
294 reg = <0xe0000 0x1000>;
299 pci0: pcie@fef08000 {
300 compatible = "fsl,mpc8641-pcie";
302 #interrupt-cells = <1>;
304 #address-cells = <3>;
305 reg = <0xfef08000 0x1000>;
306 bus-range = <0x0 0xff>;
307 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
308 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
309 clock-frequency = <33333333>;
310 interrupt-parent = <&mpic>;
311 interrupts = <0x18 0x2>;
312 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
314 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
315 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
316 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
317 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
323 #address-cells = <3>;
325 ranges = <0x02000000 0x0 0x80000000
326 0x02000000 0x0 0x80000000
329 0x01000000 0x0 0x00000000
330 0x01000000 0x0 0x00000000