git.oblomov.eu Git - linux-2.6/blob - drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 #ifdef CONFIG_R8169_NAPI
  60 #define rtl8169_rx_skb                  netif_receive_skb
  61 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  62 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  63 #else
  64 #define rtl8169_rx_skb                  netif_rx
  65 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  66 #define rtl8169_rx_quota(count, quota)  count
  67 #endif
  68
  69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  70 static const int max_interrupt_work = 20;
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  84 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  93 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  94
  95 #define RTL8169_TX_TIMEOUT      (6*HZ)
  96 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 108         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 109         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 110         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 111         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 112         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 113         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 114         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 115         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 116         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 117         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 118 };
 119
 120 enum phy_version {
 121         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 122         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 125         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 126         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 148 };
 149 #undef _R
 150
 151 enum cfg_version {
 152         RTL_CFG_0 = 0x00,
 153         RTL_CFG_1,
 154         RTL_CFG_2
 155 };
 156
 157 static void rtl_hw_start_8169(struct net_device *);
 158 static void rtl_hw_start_8168(struct net_device *);
 159 static void rtl_hw_start_8101(struct net_device *);
 160
 161 static struct pci_device_id rtl8169_pci_tbl[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 170         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 171                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 172         {0,},
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 static int rx_copybreak = 200;
 178 static int use_dac;
 179 static struct {
 180         u32 msg_enable;
 181 } debug = { -1 };
 182
 183 enum rtl_registers {
 184         MAC0            = 0,    /* Ethernet hardware address. */
 185         MAC4            = 4,
 186         MAR0            = 8,    /* Multicast filter. */
 187         CounterAddrLow          = 0x10,
 188         CounterAddrHigh         = 0x14,
 189         TxDescStartAddrLow      = 0x20,
 190         TxDescStartAddrHigh     = 0x24,
 191         TxHDescStartAddrLow     = 0x28,
 192         TxHDescStartAddrHigh    = 0x2c,
 193         FLASH           = 0x30,
 194         ERSR            = 0x36,
 195         ChipCmd         = 0x37,
 196         TxPoll          = 0x38,
 197         IntrMask        = 0x3c,
 198         IntrStatus      = 0x3e,
 199         TxConfig        = 0x40,
 200         RxConfig        = 0x44,
 201         RxMissed        = 0x4c,
 202         Cfg9346         = 0x50,
 203         Config0         = 0x51,
 204         Config1         = 0x52,
 205         Config2         = 0x53,
 206         Config3         = 0x54,
 207         Config4         = 0x55,
 208         Config5         = 0x56,
 209         MultiIntr       = 0x5c,
 210         PHYAR           = 0x60,
 211         TBICSR          = 0x64,
 212         TBI_ANAR        = 0x68,
 213         TBI_LPAR        = 0x6a,
 214         PHYstatus       = 0x6c,
 215         RxMaxSize       = 0xda,
 216         CPlusCmd        = 0xe0,
 217         IntrMitigate    = 0xe2,
 218         RxDescAddrLow   = 0xe4,
 219         RxDescAddrHigh  = 0xe8,
 220         EarlyTxThres    = 0xec,
 221         FuncEvent       = 0xf0,
 222         FuncEventMask   = 0xf4,
 223         FuncPresetState = 0xf8,
 224         FuncForceEvent  = 0xfc,
 225 };
 226
 227 enum rtl_register_content {
 228         /* InterruptStatusBits */
 229         SYSErr          = 0x8000,
 230         PCSTimeout      = 0x4000,
 231         SWInt           = 0x0100,
 232         TxDescUnavail   = 0x0080,
 233         RxFIFOOver      = 0x0040,
 234         LinkChg         = 0x0020,
 235         RxOverflow      = 0x0010,
 236         TxErr           = 0x0008,
 237         TxOK            = 0x0004,
 238         RxErr           = 0x0002,
 239         RxOK            = 0x0001,
 240
 241         /* RxStatusDesc */
 242         RxFOVF  = (1 << 23),
 243         RxRWT   = (1 << 22),
 244         RxRES   = (1 << 21),
 245         RxRUNT  = (1 << 20),
 246         RxCRC   = (1 << 19),
 247
 248         /* ChipCmdBits */
 249         CmdReset        = 0x10,
 250         CmdRxEnb        = 0x08,
 251         CmdTxEnb        = 0x04,
 252         RxBufEmpty      = 0x01,
 253
 254         /* TXPoll register p.5 */
 255         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 256         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 257         FSWInt          = 0x01,         /* Forced software interrupt */
 258
 259         /* Cfg9346Bits */
 260         Cfg9346_Lock    = 0x00,
 261         Cfg9346_Unlock  = 0xc0,
 262
 263         /* rx_mode_bits */
 264         AcceptErr       = 0x20,
 265         AcceptRunt      = 0x10,
 266         AcceptBroadcast = 0x08,
 267         AcceptMulticast = 0x04,
 268         AcceptMyPhys    = 0x02,
 269         AcceptAllPhys   = 0x01,
 270
 271         /* RxConfigBits */
 272         RxCfgFIFOShift  = 13,
 273         RxCfgDMAShift   =  8,
 274
 275         /* TxConfigBits */
 276         TxInterFrameGapShift = 24,
 277         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 278
 279         /* Config1 register p.24 */
 280         PMEnable        = (1 << 0),     /* Power Management Enable */
 281
 282         /* Config2 register p. 25 */
 283         PCI_Clock_66MHz = 0x01,
 284         PCI_Clock_33MHz = 0x00,
 285
 286         /* Config3 register p.25 */
 287         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 288         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 289
 290         /* Config5 register p.27 */
 291         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 292         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 293         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 294         LanWake         = (1 << 1),     /* LanWake enable/disable */
 295         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 296
 297         /* TBICSR p.28 */
 298         TBIReset        = 0x80000000,
 299         TBILoopback     = 0x40000000,
 300         TBINwEnable     = 0x20000000,
 301         TBINwRestart    = 0x10000000,
 302         TBILinkOk       = 0x02000000,
 303         TBINwComplete   = 0x01000000,
 304
 305         /* CPlusCmd p.31 */
 306         PktCntrDisable  = (1 << 7),     // 8168
 307         RxVlan          = (1 << 6),
 308         RxChkSum        = (1 << 5),
 309         PCIDAC          = (1 << 4),
 310         PCIMulRW        = (1 << 3),
 311         INTT_0          = 0x0000,       // 8168
 312         INTT_1          = 0x0001,       // 8168
 313         INTT_2          = 0x0002,       // 8168
 314         INTT_3          = 0x0003,       // 8168
 315
 316         /* rtl8169_PHYstatus */
 317         TBI_Enable      = 0x80,
 318         TxFlowCtrl      = 0x40,
 319         RxFlowCtrl      = 0x20,
 320         _1000bpsF       = 0x10,
 321         _100bps         = 0x08,
 322         _10bps          = 0x04,
 323         LinkStatus      = 0x02,
 324         FullDup         = 0x01,
 325
 326         /* _TBICSRBit */
 327         TBILinkOK       = 0x02000000,
 328
 329         /* DumpCounterCommand */
 330         CounterDump     = 0x8,
 331 };
 332
 333 enum desc_status_bit {
 334         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 335         RingEnd         = (1 << 30), /* End of descriptor ring */
 336         FirstFrag       = (1 << 29), /* First segment of a packet */
 337         LastFrag        = (1 << 28), /* Final segment of a packet */
 338
 339         /* Tx private */
 340         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 341         MSSShift        = 16,        /* MSS value position */
 342         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 343         IPCS            = (1 << 18), /* Calculate IP checksum */
 344         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 345         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 346         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 347
 348         /* Rx private */
 349         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 350         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 351
 352 #define RxProtoUDP      (PID1)
 353 #define RxProtoTCP      (PID0)
 354 #define RxProtoIP       (PID1 | PID0)
 355 #define RxProtoMask     RxProtoIP
 356
 357         IPFail          = (1 << 16), /* IP checksum failed */
 358         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 359         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 360         RxVlanTag       = (1 << 16), /* VLAN tag available */
 361 };
 362
 363 #define RsvdMask        0x3fffc000
 364
 365 struct TxDesc {
 366         __le32 opts1;
 367         __le32 opts2;
 368         __le64 addr;
 369 };
 370
 371 struct RxDesc {
 372         __le32 opts1;
 373         __le32 opts2;
 374         __le64 addr;
 375 };
 376
 377 struct ring_info {
 378         struct sk_buff  *skb;
 379         u32             len;
 380         u8              __pad[sizeof(void *) - sizeof(u32)];
 381 };
 382
 383 struct rtl8169_private {
 384         void __iomem *mmio_addr;        /* memory map physical address */
 385         struct pci_dev *pci_dev;        /* Index of PCI device */
 386         struct net_device *dev;
 387         struct net_device_stats stats;  /* statistics of net device */
 388         spinlock_t lock;                /* spin lock flag */
 389         u32 msg_enable;
 390         int chipset;
 391         int mac_version;
 392         int phy_version;
 393         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 394         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 395         u32 dirty_rx;
 396         u32 dirty_tx;
 397         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 398         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 399         dma_addr_t TxPhyAddr;
 400         dma_addr_t RxPhyAddr;
 401         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 402         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 403         unsigned align;
 404         unsigned rx_buf_sz;
 405         struct timer_list timer;
 406         u16 cp_cmd;
 407         u16 intr_event;
 408         u16 napi_event;
 409         u16 intr_mask;
 410         int phy_auto_nego_reg;
 411         int phy_1000_ctrl_reg;
 412 #ifdef CONFIG_R8169_VLAN
 413         struct vlan_group *vlgrp;
 414 #endif
 415         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 416         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 417         void (*phy_reset_enable)(void __iomem *);
 418         void (*hw_start)(struct net_device *);
 419         unsigned int (*phy_reset_pending)(void __iomem *);
 420         unsigned int (*link_ok)(void __iomem *);
 421         struct delayed_work task;
 422         unsigned wol_enabled : 1;
 423 };
 424
 425 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 426 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 427 module_param(rx_copybreak, int, 0);
 428 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 429 module_param(use_dac, int, 0);
 430 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 431 module_param_named(debug, debug.msg_enable, int, 0);
 432 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 433 MODULE_LICENSE("GPL");
 434 MODULE_VERSION(RTL8169_VERSION);
 435
 436 static int rtl8169_open(struct net_device *dev);
 437 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 438 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 439 static int rtl8169_init_ring(struct net_device *dev);
 440 static void rtl_hw_start(struct net_device *dev);
 441 static int rtl8169_close(struct net_device *dev);
 442 static void rtl_set_rx_mode(struct net_device *dev);
 443 static void rtl8169_tx_timeout(struct net_device *dev);
 444 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 445 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 446                                 void __iomem *);
 447 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 448 static void rtl8169_down(struct net_device *dev);
 449 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 450
 451 #ifdef CONFIG_R8169_NAPI
 452 static int rtl8169_poll(struct net_device *dev, int *budget);
 453 #endif
 454
 455 static const unsigned int rtl8169_rx_config =
 456         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 457
 458 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 459 {
 460         int i;
 461
 462         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 463
 464         for (i = 20; i > 0; i--) {
 465                 /*
 466                  * Check if the RTL8169 has completed writing to the specified
 467                  * MII register.
 468                  */
 469                 if (!(RTL_R32(PHYAR) & 0x80000000))
 470                         break;
 471                 udelay(25);
 472         }
 473 }
 474
 475 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 476 {
 477         int i, value = -1;
 478
 479         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 480
 481         for (i = 20; i > 0; i--) {
 482                 /*
 483                  * Check if the RTL8169 has completed retrieving data from
 484                  * the specified MII register.
 485                  */
 486                 if (RTL_R32(PHYAR) & 0x80000000) {
 487                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 488                         break;
 489                 }
 490                 udelay(25);
 491         }
 492         return value;
 493 }
 494
 495 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 496 {
 497         RTL_W16(IntrMask, 0x0000);
 498
 499         RTL_W16(IntrStatus, 0xffff);
 500 }
 501
 502 static void rtl8169_asic_down(void __iomem *ioaddr)
 503 {
 504         RTL_W8(ChipCmd, 0x00);
 505         rtl8169_irq_mask_and_ack(ioaddr);
 506         RTL_R16(CPlusCmd);
 507 }
 508
 509 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 510 {
 511         return RTL_R32(TBICSR) & TBIReset;
 512 }
 513
 514 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 515 {
 516         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 517 }
 518
 519 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 520 {
 521         return RTL_R32(TBICSR) & TBILinkOk;
 522 }
 523
 524 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 525 {
 526         return RTL_R8(PHYstatus) & LinkStatus;
 527 }
 528
 529 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 530 {
 531         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 532 }
 533
 534 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 535 {
 536         unsigned int val;
 537
 538         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 539         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 540 }
 541
 542 static void rtl8169_check_link_status(struct net_device *dev,
 543                                       struct rtl8169_private *tp,
 544                                       void __iomem *ioaddr)
 545 {
 546         unsigned long flags;
 547
 548         spin_lock_irqsave(&tp->lock, flags);
 549         if (tp->link_ok(ioaddr)) {
 550                 netif_carrier_on(dev);
 551                 if (netif_msg_ifup(tp))
 552                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 553         } else {
 554                 if (netif_msg_ifdown(tp))
 555                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 556                 netif_carrier_off(dev);
 557         }
 558         spin_unlock_irqrestore(&tp->lock, flags);
 559 }
 560
 561 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 562 {
 563         struct rtl8169_private *tp = netdev_priv(dev);
 564         void __iomem *ioaddr = tp->mmio_addr;
 565         u8 options;
 566
 567         wol->wolopts = 0;
 568
 569 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 570         wol->supported = WAKE_ANY;
 571
 572         spin_lock_irq(&tp->lock);
 573
 574         options = RTL_R8(Config1);
 575         if (!(options & PMEnable))
 576                 goto out_unlock;
 577
 578         options = RTL_R8(Config3);
 579         if (options & LinkUp)
 580                 wol->wolopts |= WAKE_PHY;
 581         if (options & MagicPacket)
 582                 wol->wolopts |= WAKE_MAGIC;
 583
 584         options = RTL_R8(Config5);
 585         if (options & UWF)
 586                 wol->wolopts |= WAKE_UCAST;
 587         if (options & BWF)
 588                 wol->wolopts |= WAKE_BCAST;
 589         if (options & MWF)
 590                 wol->wolopts |= WAKE_MCAST;
 591
 592 out_unlock:
 593         spin_unlock_irq(&tp->lock);
 594 }
 595
 596 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 597 {
 598         struct rtl8169_private *tp = netdev_priv(dev);
 599         void __iomem *ioaddr = tp->mmio_addr;
 600         unsigned int i;
 601         static struct {
 602                 u32 opt;
 603                 u16 reg;
 604                 u8  mask;
 605         } cfg[] = {
 606                 { WAKE_ANY,   Config1, PMEnable },
 607                 { WAKE_PHY,   Config3, LinkUp },
 608                 { WAKE_MAGIC, Config3, MagicPacket },
 609                 { WAKE_UCAST, Config5, UWF },
 610                 { WAKE_BCAST, Config5, BWF },
 611                 { WAKE_MCAST, Config5, MWF },
 612                 { WAKE_ANY,   Config5, LanWake }
 613         };
 614
 615         spin_lock_irq(&tp->lock);
 616
 617         RTL_W8(Cfg9346, Cfg9346_Unlock);
 618
 619         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 620                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 621                 if (wol->wolopts & cfg[i].opt)
 622                         options |= cfg[i].mask;
 623                 RTL_W8(cfg[i].reg, options);
 624         }
 625
 626         RTL_W8(Cfg9346, Cfg9346_Lock);
 627
 628         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 629
 630         spin_unlock_irq(&tp->lock);
 631
 632         return 0;
 633 }
 634
 635 static void rtl8169_get_drvinfo(struct net_device *dev,
 636                                 struct ethtool_drvinfo *info)
 637 {
 638         struct rtl8169_private *tp = netdev_priv(dev);
 639
 640         strcpy(info->driver, MODULENAME);
 641         strcpy(info->version, RTL8169_VERSION);
 642         strcpy(info->bus_info, pci_name(tp->pci_dev));
 643 }
 644
 645 static int rtl8169_get_regs_len(struct net_device *dev)
 646 {
 647         return R8169_REGS_SIZE;
 648 }
 649
 650 static int rtl8169_set_speed_tbi(struct net_device *dev,
 651                                  u8 autoneg, u16 speed, u8 duplex)
 652 {
 653         struct rtl8169_private *tp = netdev_priv(dev);
 654         void __iomem *ioaddr = tp->mmio_addr;
 655         int ret = 0;
 656         u32 reg;
 657
 658         reg = RTL_R32(TBICSR);
 659         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 660             (duplex == DUPLEX_FULL)) {
 661                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 662         } else if (autoneg == AUTONEG_ENABLE)
 663                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 664         else {
 665                 if (netif_msg_link(tp)) {
 666                         printk(KERN_WARNING "%s: "
 667                                "incorrect speed setting refused in TBI mode\n",
 668                                dev->name);
 669                 }
 670                 ret = -EOPNOTSUPP;
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int rtl8169_set_speed_xmii(struct net_device *dev,
 677                                   u8 autoneg, u16 speed, u8 duplex)
 678 {
 679         struct rtl8169_private *tp = netdev_priv(dev);
 680         void __iomem *ioaddr = tp->mmio_addr;
 681         int auto_nego, giga_ctrl;
 682
 683         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 684         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 685                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 686         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 687         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 688
 689         if (autoneg == AUTONEG_ENABLE) {
 690                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 691                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 692                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 693         } else {
 694                 if (speed == SPEED_10)
 695                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 696                 else if (speed == SPEED_100)
 697                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 698                 else if (speed == SPEED_1000)
 699                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 700
 701                 if (duplex == DUPLEX_HALF)
 702                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 703
 704                 if (duplex == DUPLEX_FULL)
 705                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 706
 707                 /* This tweak comes straight from Realtek's driver. */
 708                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 709                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 710                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 711                 }
 712         }
 713
 714         /* The 8100e/8101e do Fast Ethernet only. */
 715         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 716             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 717             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 718                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 719                     netif_msg_link(tp)) {
 720                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 721                                dev->name);
 722                 }
 723                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 724         }
 725
 726         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 727
 728         tp->phy_auto_nego_reg = auto_nego;
 729         tp->phy_1000_ctrl_reg = giga_ctrl;
 730
 731         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 732         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 733         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 734         return 0;
 735 }
 736
 737 static int rtl8169_set_speed(struct net_device *dev,
 738                              u8 autoneg, u16 speed, u8 duplex)
 739 {
 740         struct rtl8169_private *tp = netdev_priv(dev);
 741         int ret;
 742
 743         ret = tp->set_speed(dev, autoneg, speed, duplex);
 744
 745         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 746                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 747
 748         return ret;
 749 }
 750
 751 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 752 {
 753         struct rtl8169_private *tp = netdev_priv(dev);
 754         unsigned long flags;
 755         int ret;
 756
 757         spin_lock_irqsave(&tp->lock, flags);
 758         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 759         spin_unlock_irqrestore(&tp->lock, flags);
 760
 761         return ret;
 762 }
 763
 764 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 765 {
 766         struct rtl8169_private *tp = netdev_priv(dev);
 767
 768         return tp->cp_cmd & RxChkSum;
 769 }
 770
 771 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 772 {
 773         struct rtl8169_private *tp = netdev_priv(dev);
 774         void __iomem *ioaddr = tp->mmio_addr;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&tp->lock, flags);
 778
 779         if (data)
 780                 tp->cp_cmd |= RxChkSum;
 781         else
 782                 tp->cp_cmd &= ~RxChkSum;
 783
 784         RTL_W16(CPlusCmd, tp->cp_cmd);
 785         RTL_R16(CPlusCmd);
 786
 787         spin_unlock_irqrestore(&tp->lock, flags);
 788
 789         return 0;
 790 }
 791
 792 #ifdef CONFIG_R8169_VLAN
 793
 794 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 795                                       struct sk_buff *skb)
 796 {
 797         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 798                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 799 }
 800
 801 static void rtl8169_vlan_rx_register(struct net_device *dev,
 802                                      struct vlan_group *grp)
 803 {
 804         struct rtl8169_private *tp = netdev_priv(dev);
 805         void __iomem *ioaddr = tp->mmio_addr;
 806         unsigned long flags;
 807
 808         spin_lock_irqsave(&tp->lock, flags);
 809         tp->vlgrp = grp;
 810         if (tp->vlgrp)
 811                 tp->cp_cmd |= RxVlan;
 812         else
 813                 tp->cp_cmd &= ~RxVlan;
 814         RTL_W16(CPlusCmd, tp->cp_cmd);
 815         RTL_R16(CPlusCmd);
 816         spin_unlock_irqrestore(&tp->lock, flags);
 817 }
 818
 819 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 820                                struct sk_buff *skb)
 821 {
 822         u32 opts2 = le32_to_cpu(desc->opts2);
 823         int ret;
 824
 825         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 826                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 827                 ret = 0;
 828         } else
 829                 ret = -1;
 830         desc->opts2 = 0;
 831         return ret;
 832 }
 833
 834 #else /* !CONFIG_R8169_VLAN */
 835
 836 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 837                                       struct sk_buff *skb)
 838 {
 839         return 0;
 840 }
 841
 842 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 843                                struct sk_buff *skb)
 844 {
 845         return -1;
 846 }
 847
 848 #endif
 849
 850 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 851 {
 852         struct rtl8169_private *tp = netdev_priv(dev);
 853         void __iomem *ioaddr = tp->mmio_addr;
 854         u32 status;
 855
 856         cmd->supported =
 857                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 858         cmd->port = PORT_FIBRE;
 859         cmd->transceiver = XCVR_INTERNAL;
 860
 861         status = RTL_R32(TBICSR);
 862         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 863         cmd->autoneg = !!(status & TBINwEnable);
 864
 865         cmd->speed = SPEED_1000;
 866         cmd->duplex = DUPLEX_FULL; /* Always set */
 867 }
 868
 869 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 870 {
 871         struct rtl8169_private *tp = netdev_priv(dev);
 872         void __iomem *ioaddr = tp->mmio_addr;
 873         u8 status;
 874
 875         cmd->supported = SUPPORTED_10baseT_Half |
 876                          SUPPORTED_10baseT_Full |
 877                          SUPPORTED_100baseT_Half |
 878                          SUPPORTED_100baseT_Full |
 879                          SUPPORTED_1000baseT_Full |
 880                          SUPPORTED_Autoneg |
 881                          SUPPORTED_TP;
 882
 883         cmd->autoneg = 1;
 884         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 885
 886         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 887                 cmd->advertising |= ADVERTISED_10baseT_Half;
 888         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 889                 cmd->advertising |= ADVERTISED_10baseT_Full;
 890         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 891                 cmd->advertising |= ADVERTISED_100baseT_Half;
 892         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 893                 cmd->advertising |= ADVERTISED_100baseT_Full;
 894         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 895                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 896
 897         status = RTL_R8(PHYstatus);
 898
 899         if (status & _1000bpsF)
 900                 cmd->speed = SPEED_1000;
 901         else if (status & _100bps)
 902                 cmd->speed = SPEED_100;
 903         else if (status & _10bps)
 904                 cmd->speed = SPEED_10;
 905
 906         if (status & TxFlowCtrl)
 907                 cmd->advertising |= ADVERTISED_Asym_Pause;
 908         if (status & RxFlowCtrl)
 909                 cmd->advertising |= ADVERTISED_Pause;
 910
 911         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 912                       DUPLEX_FULL : DUPLEX_HALF;
 913 }
 914
 915 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 916 {
 917         struct rtl8169_private *tp = netdev_priv(dev);
 918         unsigned long flags;
 919
 920         spin_lock_irqsave(&tp->lock, flags);
 921
 922         tp->get_settings(dev, cmd);
 923
 924         spin_unlock_irqrestore(&tp->lock, flags);
 925         return 0;
 926 }
 927
 928 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 929                              void *p)
 930 {
 931         struct rtl8169_private *tp = netdev_priv(dev);
 932         unsigned long flags;
 933
 934         if (regs->len > R8169_REGS_SIZE)
 935                 regs->len = R8169_REGS_SIZE;
 936
 937         spin_lock_irqsave(&tp->lock, flags);
 938         memcpy_fromio(p, tp->mmio_addr, regs->len);
 939         spin_unlock_irqrestore(&tp->lock, flags);
 940 }
 941
 942 static u32 rtl8169_get_msglevel(struct net_device *dev)
 943 {
 944         struct rtl8169_private *tp = netdev_priv(dev);
 945
 946         return tp->msg_enable;
 947 }
 948
 949 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 950 {
 951         struct rtl8169_private *tp = netdev_priv(dev);
 952
 953         tp->msg_enable = value;
 954 }
 955
 956 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 957         "tx_packets",
 958         "rx_packets",
 959         "tx_errors",
 960         "rx_errors",
 961         "rx_missed",
 962         "align_errors",
 963         "tx_single_collisions",
 964         "tx_multi_collisions",
 965         "unicast",
 966         "broadcast",
 967         "multicast",
 968         "tx_aborted",
 969         "tx_underrun",
 970 };
 971
 972 struct rtl8169_counters {
 973         u64     tx_packets;
 974         u64     rx_packets;
 975         u64     tx_errors;
 976         u32     rx_errors;
 977         u16     rx_missed;
 978         u16     align_errors;
 979         u32     tx_one_collision;
 980         u32     tx_multi_collision;
 981         u64     rx_unicast;
 982         u64     rx_broadcast;
 983         u32     rx_multicast;
 984         u16     tx_aborted;
 985         u16     tx_underun;
 986 };
 987
 988 static int rtl8169_get_stats_count(struct net_device *dev)
 989 {
 990         return ARRAY_SIZE(rtl8169_gstrings);
 991 }
 992
 993 static void rtl8169_get_ethtool_stats(struct net_device *dev,
 994                                       struct ethtool_stats *stats, u64 *data)
 995 {
 996         struct rtl8169_private *tp = netdev_priv(dev);
 997         void __iomem *ioaddr = tp->mmio_addr;
 998         struct rtl8169_counters *counters;
 999         dma_addr_t paddr;
1000         u32 cmd;
1001
1002         ASSERT_RTNL();
1003
1004         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1005         if (!counters)
1006                 return;
1007
1008         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1009         cmd = (u64)paddr & DMA_32BIT_MASK;
1010         RTL_W32(CounterAddrLow, cmd);
1011         RTL_W32(CounterAddrLow, cmd | CounterDump);
1012
1013         while (RTL_R32(CounterAddrLow) & CounterDump) {
1014                 if (msleep_interruptible(1))
1015                         break;
1016         }
1017
1018         RTL_W32(CounterAddrLow, 0);
1019         RTL_W32(CounterAddrHigh, 0);
1020
1021         data[0] = le64_to_cpu(counters->tx_packets);
1022         data[1] = le64_to_cpu(counters->rx_packets);
1023         data[2] = le64_to_cpu(counters->tx_errors);
1024         data[3] = le32_to_cpu(counters->rx_errors);
1025         data[4] = le16_to_cpu(counters->rx_missed);
1026         data[5] = le16_to_cpu(counters->align_errors);
1027         data[6] = le32_to_cpu(counters->tx_one_collision);
1028         data[7] = le32_to_cpu(counters->tx_multi_collision);
1029         data[8] = le64_to_cpu(counters->rx_unicast);
1030         data[9] = le64_to_cpu(counters->rx_broadcast);
1031         data[10] = le32_to_cpu(counters->rx_multicast);
1032         data[11] = le16_to_cpu(counters->tx_aborted);
1033         data[12] = le16_to_cpu(counters->tx_underun);
1034
1035         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1036 }
1037
1038 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1039 {
1040         switch(stringset) {
1041         case ETH_SS_STATS:
1042                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1043                 break;
1044         }
1045 }
1046
1047 static const struct ethtool_ops rtl8169_ethtool_ops = {
1048         .get_drvinfo            = rtl8169_get_drvinfo,
1049         .get_regs_len           = rtl8169_get_regs_len,
1050         .get_link               = ethtool_op_get_link,
1051         .get_settings           = rtl8169_get_settings,
1052         .set_settings           = rtl8169_set_settings,
1053         .get_msglevel           = rtl8169_get_msglevel,
1054         .set_msglevel           = rtl8169_set_msglevel,
1055         .get_rx_csum            = rtl8169_get_rx_csum,
1056         .set_rx_csum            = rtl8169_set_rx_csum,
1057         .get_tx_csum            = ethtool_op_get_tx_csum,
1058         .set_tx_csum            = ethtool_op_set_tx_csum,
1059         .get_sg                 = ethtool_op_get_sg,
1060         .set_sg                 = ethtool_op_set_sg,
1061         .get_tso                = ethtool_op_get_tso,
1062         .set_tso                = ethtool_op_set_tso,
1063         .get_regs               = rtl8169_get_regs,
1064         .get_wol                = rtl8169_get_wol,
1065         .set_wol                = rtl8169_set_wol,
1066         .get_strings            = rtl8169_get_strings,
1067         .get_stats_count        = rtl8169_get_stats_count,
1068         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1069 };
1070
1071 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1072                                        int bitnum, int bitval)
1073 {
1074         int val;
1075
1076         val = mdio_read(ioaddr, reg);
1077         val = (bitval == 1) ?
1078                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1079         mdio_write(ioaddr, reg, val & 0xffff);
1080 }
1081
1082 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1083                                     void __iomem *ioaddr)
1084 {
1085         /*
1086          * The driver currently handles the 8168Bf and the 8168Be identically
1087          * but they can be identified more specifically through the test below
1088          * if needed:
1089          *
1090          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1091          *
1092          * Same thing for the 8101Eb and the 8101Ec:
1093          *
1094          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1095          */
1096         const struct {
1097                 u32 mask;
1098                 int mac_version;
1099         } mac_info[] = {
1100                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1101                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1102                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1103                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1104                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1105                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1106                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1107                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1108                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1109                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1110                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1111         }, *p = mac_info;
1112         u32 reg;
1113
1114         reg = RTL_R32(TxConfig) & 0xfc800000;
1115         while ((reg & p->mask) != p->mask)
1116                 p++;
1117         tp->mac_version = p->mac_version;
1118 }
1119
1120 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1121 {
1122         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1123 }
1124
1125 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1126                                     void __iomem *ioaddr)
1127 {
1128         const struct {
1129                 u16 mask;
1130                 u16 set;
1131                 int phy_version;
1132         } phy_info[] = {
1133                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1134                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1135                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1136                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1137         }, *p = phy_info;
1138         u16 reg;
1139
1140         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1141         while ((reg & p->mask) != p->set)
1142                 p++;
1143         tp->phy_version = p->phy_version;
1144 }
1145
1146 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1147 {
1148         struct {
1149                 int version;
1150                 char *msg;
1151                 u32 reg;
1152         } phy_print[] = {
1153                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1154                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1155                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1156                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1157                 { 0, NULL, 0x0000 }
1158         }, *p;
1159
1160         for (p = phy_print; p->msg; p++) {
1161                 if (tp->phy_version == p->version) {
1162                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1163                         return;
1164                 }
1165         }
1166         dprintk("phy_version == Unknown\n");
1167 }
1168
1169 static void rtl8169_hw_phy_config(struct net_device *dev)
1170 {
1171         struct rtl8169_private *tp = netdev_priv(dev);
1172         void __iomem *ioaddr = tp->mmio_addr;
1173         struct {
1174                 u16 regs[5]; /* Beware of bit-sign propagation */
1175         } phy_magic[5] = { {
1176                 { 0x0000,       //w 4 15 12 0
1177                   0x00a1,       //w 3 15 0 00a1
1178                   0x0008,       //w 2 15 0 0008
1179                   0x1020,       //w 1 15 0 1020
1180                   0x1000 } },{  //w 0 15 0 1000
1181                 { 0x7000,       //w 4 15 12 7
1182                   0xff41,       //w 3 15 0 ff41
1183                   0xde60,       //w 2 15 0 de60
1184                   0x0140,       //w 1 15 0 0140
1185                   0x0077 } },{  //w 0 15 0 0077
1186                 { 0xa000,       //w 4 15 12 a
1187                   0xdf01,       //w 3 15 0 df01
1188                   0xdf20,       //w 2 15 0 df20
1189                   0xff95,       //w 1 15 0 ff95
1190                   0xfa00 } },{  //w 0 15 0 fa00
1191                 { 0xb000,       //w 4 15 12 b
1192                   0xff41,       //w 3 15 0 ff41
1193                   0xde20,       //w 2 15 0 de20
1194                   0x0140,       //w 1 15 0 0140
1195                   0x00bb } },{  //w 0 15 0 00bb
1196                 { 0xf000,       //w 4 15 12 f
1197                   0xdf01,       //w 3 15 0 df01
1198                   0xdf20,       //w 2 15 0 df20
1199                   0xff95,       //w 1 15 0 ff95
1200                   0xbf00 }      //w 0 15 0 bf00
1201                 }
1202         }, *p = phy_magic;
1203         unsigned int i;
1204
1205         rtl8169_print_mac_version(tp);
1206         rtl8169_print_phy_version(tp);
1207
1208         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1209                 return;
1210         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1211                 return;
1212
1213         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1214         dprintk("Do final_reg2.cfg\n");
1215
1216         /* Shazam ! */
1217
1218         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1219                 mdio_write(ioaddr, 31, 0x0002);
1220                 mdio_write(ioaddr,  1, 0x90d0);
1221                 mdio_write(ioaddr, 31, 0x0000);
1222                 return;
1223         }
1224
1225         /* phy config for RTL8169s mac_version C chip */
1226         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1227         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1228         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1229         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1230
1231         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1232                 int val, pos = 4;
1233
1234                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1235                 mdio_write(ioaddr, pos, val);
1236                 while (--pos >= 0)
1237                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1238                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1239                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1240         }
1241         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1242 }
1243
1244 static void rtl8169_phy_timer(unsigned long __opaque)
1245 {
1246         struct net_device *dev = (struct net_device *)__opaque;
1247         struct rtl8169_private *tp = netdev_priv(dev);
1248         struct timer_list *timer = &tp->timer;
1249         void __iomem *ioaddr = tp->mmio_addr;
1250         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1251
1252         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1253         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1254
1255         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1256                 return;
1257
1258         spin_lock_irq(&tp->lock);
1259
1260         if (tp->phy_reset_pending(ioaddr)) {
1261                 /*
1262                  * A busy loop could burn quite a few cycles on nowadays CPU.
1263                  * Let's delay the execution of the timer for a few ticks.
1264                  */
1265                 timeout = HZ/10;
1266                 goto out_mod_timer;
1267         }
1268
1269         if (tp->link_ok(ioaddr))
1270                 goto out_unlock;
1271
1272         if (netif_msg_link(tp))
1273                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1274
1275         tp->phy_reset_enable(ioaddr);
1276
1277 out_mod_timer:
1278         mod_timer(timer, jiffies + timeout);
1279 out_unlock:
1280         spin_unlock_irq(&tp->lock);
1281 }
1282
1283 static inline void rtl8169_delete_timer(struct net_device *dev)
1284 {
1285         struct rtl8169_private *tp = netdev_priv(dev);
1286         struct timer_list *timer = &tp->timer;
1287
1288         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1289             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1290                 return;
1291
1292         del_timer_sync(timer);
1293 }
1294
1295 static inline void rtl8169_request_timer(struct net_device *dev)
1296 {
1297         struct rtl8169_private *tp = netdev_priv(dev);
1298         struct timer_list *timer = &tp->timer;
1299
1300         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1301             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1302                 return;
1303
1304         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1305 }
1306
1307 #ifdef CONFIG_NET_POLL_CONTROLLER
1308 /*
1309  * Polling 'interrupt' - used by things like netconsole to send skbs
1310  * without having to re-enable interrupts. It's not called while
1311  * the interrupt routine is executing.
1312  */
1313 static void rtl8169_netpoll(struct net_device *dev)
1314 {
1315         struct rtl8169_private *tp = netdev_priv(dev);
1316         struct pci_dev *pdev = tp->pci_dev;
1317
1318         disable_irq(pdev->irq);
1319         rtl8169_interrupt(pdev->irq, dev);
1320         enable_irq(pdev->irq);
1321 }
1322 #endif
1323
1324 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1325                                   void __iomem *ioaddr)
1326 {
1327         iounmap(ioaddr);
1328         pci_release_regions(pdev);
1329         pci_disable_device(pdev);
1330         free_netdev(dev);
1331 }
1332
1333 static void rtl8169_phy_reset(struct net_device *dev,
1334                               struct rtl8169_private *tp)
1335 {
1336         void __iomem *ioaddr = tp->mmio_addr;
1337         unsigned int i;
1338
1339         tp->phy_reset_enable(ioaddr);
1340         for (i = 0; i < 100; i++) {
1341                 if (!tp->phy_reset_pending(ioaddr))
1342                         return;
1343                 msleep(1);
1344         }
1345         if (netif_msg_link(tp))
1346                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1347 }
1348
1349 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1350 {
1351         void __iomem *ioaddr = tp->mmio_addr;
1352
1353         rtl8169_hw_phy_config(dev);
1354
1355         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1356         RTL_W8(0x82, 0x01);
1357
1358         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1359
1360         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1361                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1362
1363         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1364                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365                 RTL_W8(0x82, 0x01);
1366                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1367                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1368         }
1369
1370         rtl8169_phy_reset(dev, tp);
1371
1372         /*
1373          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1374          * only 8101. Don't panic.
1375          */
1376         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1377
1378         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1379                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1380 }
1381
1382 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1383 {
1384         void __iomem *ioaddr = tp->mmio_addr;
1385         u32 high;
1386         u32 low;
1387
1388         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1389         high = addr[4] | (addr[5] << 8);
1390
1391         spin_lock_irq(&tp->lock);
1392
1393         RTL_W8(Cfg9346, Cfg9346_Unlock);
1394         RTL_W32(MAC0, low);
1395         RTL_W32(MAC4, high);
1396         RTL_W8(Cfg9346, Cfg9346_Lock);
1397
1398         spin_unlock_irq(&tp->lock);
1399 }
1400
1401 static int rtl_set_mac_address(struct net_device *dev, void *p)
1402 {
1403         struct rtl8169_private *tp = netdev_priv(dev);
1404         struct sockaddr *addr = p;
1405
1406         if (!is_valid_ether_addr(addr->sa_data))
1407                 return -EADDRNOTAVAIL;
1408
1409         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1410
1411         rtl_rar_set(tp, dev->dev_addr);
1412
1413         return 0;
1414 }
1415
1416 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1417 {
1418         struct rtl8169_private *tp = netdev_priv(dev);
1419         struct mii_ioctl_data *data = if_mii(ifr);
1420
1421         if (!netif_running(dev))
1422                 return -ENODEV;
1423
1424         switch (cmd) {
1425         case SIOCGMIIPHY:
1426                 data->phy_id = 32; /* Internal PHY */
1427                 return 0;
1428
1429         case SIOCGMIIREG:
1430                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1431                 return 0;
1432
1433         case SIOCSMIIREG:
1434                 if (!capable(CAP_NET_ADMIN))
1435                         return -EPERM;
1436                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1437                 return 0;
1438         }
1439         return -EOPNOTSUPP;
1440 }
1441
1442 static const struct rtl_cfg_info {
1443         void (*hw_start)(struct net_device *);
1444         unsigned int region;
1445         unsigned int align;
1446         u16 intr_event;
1447         u16 napi_event;
1448 } rtl_cfg_infos [] = {
1449         [RTL_CFG_0] = {
1450                 .hw_start       = rtl_hw_start_8169,
1451                 .region         = 1,
1452                 .align          = 0,
1453                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1454                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1455                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1456         },
1457         [RTL_CFG_1] = {
1458                 .hw_start       = rtl_hw_start_8168,
1459                 .region         = 2,
1460                 .align          = 8,
1461                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1462                                   TxErr | TxOK | RxOK | RxErr,
1463                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1464         },
1465         [RTL_CFG_2] = {
1466                 .hw_start       = rtl_hw_start_8101,
1467                 .region         = 2,
1468                 .align          = 8,
1469                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1470                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1471                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1472         }
1473 };
1474
1475 static int __devinit
1476 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1477 {
1478         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1479         const unsigned int region = cfg->region;
1480         struct rtl8169_private *tp;
1481         struct net_device *dev;
1482         void __iomem *ioaddr;
1483         unsigned int i;
1484         int rc;
1485
1486         if (netif_msg_drv(&debug)) {
1487                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1488                        MODULENAME, RTL8169_VERSION);
1489         }
1490
1491         dev = alloc_etherdev(sizeof (*tp));
1492         if (!dev) {
1493                 if (netif_msg_drv(&debug))
1494                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1495                 rc = -ENOMEM;
1496                 goto out;
1497         }
1498
1499         SET_MODULE_OWNER(dev);
1500         SET_NETDEV_DEV(dev, &pdev->dev);
1501         tp = netdev_priv(dev);
1502         tp->dev = dev;
1503         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1504
1505         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1506         rc = pci_enable_device(pdev);
1507         if (rc < 0) {
1508                 if (netif_msg_probe(tp))
1509                         dev_err(&pdev->dev, "enable failure\n");
1510                 goto err_out_free_dev_1;
1511         }
1512
1513         rc = pci_set_mwi(pdev);
1514         if (rc < 0)
1515                 goto err_out_disable_2;
1516
1517         /* make sure PCI base addr 1 is MMIO */
1518         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1519                 if (netif_msg_probe(tp)) {
1520                         dev_err(&pdev->dev,
1521                                 "region #%d not an MMIO resource, aborting\n",
1522                                 region);
1523                 }
1524                 rc = -ENODEV;
1525                 goto err_out_mwi_3;
1526         }
1527
1528         /* check for weird/broken PCI region reporting */
1529         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1530                 if (netif_msg_probe(tp)) {
1531                         dev_err(&pdev->dev,
1532                                 "Invalid PCI region size(s), aborting\n");
1533                 }
1534                 rc = -ENODEV;
1535                 goto err_out_mwi_3;
1536         }
1537
1538         rc = pci_request_regions(pdev, MODULENAME);
1539         if (rc < 0) {
1540                 if (netif_msg_probe(tp))
1541                         dev_err(&pdev->dev, "could not request regions.\n");
1542                 goto err_out_mwi_3;
1543         }
1544
1545         tp->cp_cmd = PCIMulRW | RxChkSum;
1546
1547         if ((sizeof(dma_addr_t) > 4) &&
1548             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1549                 tp->cp_cmd |= PCIDAC;
1550                 dev->features |= NETIF_F_HIGHDMA;
1551         } else {
1552                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1553                 if (rc < 0) {
1554                         if (netif_msg_probe(tp)) {
1555                                 dev_err(&pdev->dev,
1556                                         "DMA configuration failed.\n");
1557                         }
1558                         goto err_out_free_res_4;
1559                 }
1560         }
1561
1562         pci_set_master(pdev);
1563
1564         /* ioremap MMIO region */
1565         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1566         if (!ioaddr) {
1567                 if (netif_msg_probe(tp))
1568                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1569                 rc = -EIO;
1570                 goto err_out_free_res_4;
1571         }
1572
1573         /* Unneeded ? Don't mess with Mrs. Murphy. */
1574         rtl8169_irq_mask_and_ack(ioaddr);
1575
1576         /* Soft reset the chip. */
1577         RTL_W8(ChipCmd, CmdReset);
1578
1579         /* Check that the chip has finished the reset. */
1580         for (i = 0; i < 100; i++) {
1581                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1582                         break;
1583                 msleep_interruptible(1);
1584         }
1585
1586         /* Identify chip attached to board */
1587         rtl8169_get_mac_version(tp, ioaddr);
1588         rtl8169_get_phy_version(tp, ioaddr);
1589
1590         rtl8169_print_mac_version(tp);
1591         rtl8169_print_phy_version(tp);
1592
1593         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1594                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1595                         break;
1596         }
1597         if (i < 0) {
1598                 /* Unknown chip: assume array element #0, original RTL-8169 */
1599                 if (netif_msg_probe(tp)) {
1600                         dev_printk(KERN_DEBUG, &pdev->dev,
1601                                 "unknown chip version, assuming %s\n",
1602                                 rtl_chip_info[0].name);
1603                 }
1604                 i++;
1605         }
1606         tp->chipset = i;
1607
1608         RTL_W8(Cfg9346, Cfg9346_Unlock);
1609         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1610         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1611         RTL_W8(Cfg9346, Cfg9346_Lock);
1612
1613         if (RTL_R8(PHYstatus) & TBI_Enable) {
1614                 tp->set_speed = rtl8169_set_speed_tbi;
1615                 tp->get_settings = rtl8169_gset_tbi;
1616                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1617                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1618                 tp->link_ok = rtl8169_tbi_link_ok;
1619
1620                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1621         } else {
1622                 tp->set_speed = rtl8169_set_speed_xmii;
1623                 tp->get_settings = rtl8169_gset_xmii;
1624                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1625                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1626                 tp->link_ok = rtl8169_xmii_link_ok;
1627
1628                 dev->do_ioctl = rtl8169_ioctl;
1629         }
1630
1631         /* Get MAC address.  FIXME: read EEPROM */
1632         for (i = 0; i < MAC_ADDR_LEN; i++)
1633                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1634         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1635
1636         dev->open = rtl8169_open;
1637         dev->hard_start_xmit = rtl8169_start_xmit;
1638         dev->get_stats = rtl8169_get_stats;
1639         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1640         dev->stop = rtl8169_close;
1641         dev->tx_timeout = rtl8169_tx_timeout;
1642         dev->set_multicast_list = rtl_set_rx_mode;
1643         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1644         dev->irq = pdev->irq;
1645         dev->base_addr = (unsigned long) ioaddr;
1646         dev->change_mtu = rtl8169_change_mtu;
1647         dev->set_mac_address = rtl_set_mac_address;
1648
1649 #ifdef CONFIG_R8169_NAPI
1650         dev->poll = rtl8169_poll;
1651         dev->weight = R8169_NAPI_WEIGHT;
1652 #endif
1653
1654 #ifdef CONFIG_R8169_VLAN
1655         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1656         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1657 #endif
1658
1659 #ifdef CONFIG_NET_POLL_CONTROLLER
1660         dev->poll_controller = rtl8169_netpoll;
1661 #endif
1662
1663         tp->intr_mask = 0xffff;
1664         tp->pci_dev = pdev;
1665         tp->mmio_addr = ioaddr;
1666         tp->align = cfg->align;
1667         tp->hw_start = cfg->hw_start;
1668         tp->intr_event = cfg->intr_event;
1669         tp->napi_event = cfg->napi_event;
1670
1671         init_timer(&tp->timer);
1672         tp->timer.data = (unsigned long) dev;
1673         tp->timer.function = rtl8169_phy_timer;
1674
1675         spin_lock_init(&tp->lock);
1676
1677         rc = register_netdev(dev);
1678         if (rc < 0)
1679                 goto err_out_unmap_5;
1680
1681         pci_set_drvdata(pdev, dev);
1682
1683         if (netif_msg_probe(tp)) {
1684                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1685
1686                 printk(KERN_INFO "%s: %s at 0x%lx, "
1687                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1688                        "XID %08x IRQ %d\n",
1689                        dev->name,
1690                        rtl_chip_info[tp->chipset].name,
1691                        dev->base_addr,
1692                        dev->dev_addr[0], dev->dev_addr[1],
1693                        dev->dev_addr[2], dev->dev_addr[3],
1694                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1695         }
1696
1697         rtl8169_init_phy(dev, tp);
1698
1699 out:
1700         return rc;
1701
1702 err_out_unmap_5:
1703         iounmap(ioaddr);
1704 err_out_free_res_4:
1705         pci_release_regions(pdev);
1706 err_out_mwi_3:
1707         pci_clear_mwi(pdev);
1708 err_out_disable_2:
1709         pci_disable_device(pdev);
1710 err_out_free_dev_1:
1711         free_netdev(dev);
1712         goto out;
1713 }
1714
1715 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1716 {
1717         struct net_device *dev = pci_get_drvdata(pdev);
1718         struct rtl8169_private *tp = netdev_priv(dev);
1719
1720         flush_scheduled_work();
1721
1722         unregister_netdev(dev);
1723         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1724         pci_set_drvdata(pdev, NULL);
1725 }
1726
1727 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1728                                   struct net_device *dev)
1729 {
1730         unsigned int mtu = dev->mtu;
1731
1732         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1733 }
1734
1735 static int rtl8169_open(struct net_device *dev)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738         struct pci_dev *pdev = tp->pci_dev;
1739         int retval = -ENOMEM;
1740
1741
1742         rtl8169_set_rxbufsize(tp, dev);
1743
1744         /*
1745          * Rx and Tx desscriptors needs 256 bytes alignment.
1746          * pci_alloc_consistent provides more.
1747          */
1748         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1749                                                &tp->TxPhyAddr);
1750         if (!tp->TxDescArray)
1751                 goto out;
1752
1753         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1754                                                &tp->RxPhyAddr);
1755         if (!tp->RxDescArray)
1756                 goto err_free_tx_0;
1757
1758         retval = rtl8169_init_ring(dev);
1759         if (retval < 0)
1760                 goto err_free_rx_1;
1761
1762         INIT_DELAYED_WORK(&tp->task, NULL);
1763
1764         smp_mb();
1765
1766         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1767                              dev->name, dev);
1768         if (retval < 0)
1769                 goto err_release_ring_2;
1770
1771         rtl_hw_start(dev);
1772
1773         rtl8169_request_timer(dev);
1774
1775         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1776 out:
1777         return retval;
1778
1779 err_release_ring_2:
1780         rtl8169_rx_clear(tp);
1781 err_free_rx_1:
1782         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1783                             tp->RxPhyAddr);
1784 err_free_tx_0:
1785         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1786                             tp->TxPhyAddr);
1787         goto out;
1788 }
1789
1790 static void rtl8169_hw_reset(void __iomem *ioaddr)
1791 {
1792         /* Disable interrupts */
1793         rtl8169_irq_mask_and_ack(ioaddr);
1794
1795         /* Reset the chipset */
1796         RTL_W8(ChipCmd, CmdReset);
1797
1798         /* PCI commit */
1799         RTL_R8(ChipCmd);
1800 }
1801
1802 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1803 {
1804         void __iomem *ioaddr = tp->mmio_addr;
1805         u32 cfg = rtl8169_rx_config;
1806
1807         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1808         RTL_W32(RxConfig, cfg);
1809
1810         /* Set DMA burst size and Interframe Gap Time */
1811         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1812                 (InterFrameGap << TxInterFrameGapShift));
1813 }
1814
1815 static void rtl_hw_start(struct net_device *dev)
1816 {
1817         struct rtl8169_private *tp = netdev_priv(dev);
1818         void __iomem *ioaddr = tp->mmio_addr;
1819         unsigned int i;
1820
1821         /* Soft reset the chip. */
1822         RTL_W8(ChipCmd, CmdReset);
1823
1824         /* Check that the chip has finished the reset. */
1825         for (i = 0; i < 100; i++) {
1826                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1827                         break;
1828                 msleep_interruptible(1);
1829         }
1830
1831         tp->hw_start(dev);
1832
1833         netif_start_queue(dev);
1834 }
1835
1836
1837 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1838                                          void __iomem *ioaddr)
1839 {
1840         /*
1841          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1842          * register to be written before TxDescAddrLow to work.
1843          * Switching from MMIO to I/O access fixes the issue as well.
1844          */
1845         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1846         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1847         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1848         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1849 }
1850
1851 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1852 {
1853         u16 cmd;
1854
1855         cmd = RTL_R16(CPlusCmd);
1856         RTL_W16(CPlusCmd, cmd);
1857         return cmd;
1858 }
1859
1860 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1861 {
1862         /* Low hurts. Let's disable the filtering. */
1863         RTL_W16(RxMaxSize, 16383);
1864 }
1865
1866 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1867 {
1868         struct {
1869                 u32 mac_version;
1870                 u32 clk;
1871                 u32 val;
1872         } cfg2_info [] = {
1873                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1874                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1875                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1876                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1877         }, *p = cfg2_info;
1878         unsigned int i;
1879         u32 clk;
1880
1881         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1882         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1883                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1884                         RTL_W32(0x7c, p->val);
1885                         break;
1886                 }
1887         }
1888 }
1889
1890 static void rtl_hw_start_8169(struct net_device *dev)
1891 {
1892         struct rtl8169_private *tp = netdev_priv(dev);
1893         void __iomem *ioaddr = tp->mmio_addr;
1894         struct pci_dev *pdev = tp->pci_dev;
1895
1896         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1897                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1898                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1899         }
1900
1901         RTL_W8(Cfg9346, Cfg9346_Unlock);
1902         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1903             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1904             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1905             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1906                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1907
1908         RTL_W8(EarlyTxThres, EarlyTxThld);
1909
1910         rtl_set_rx_max_size(ioaddr);
1911
1912         rtl_set_rx_tx_config_registers(tp);
1913
1914         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1915
1916         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1917             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1918                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1919                         "Bit-3 and bit-14 MUST be 1\n");
1920                 tp->cp_cmd |= (1 << 14);
1921         }
1922
1923         RTL_W16(CPlusCmd, tp->cp_cmd);
1924
1925         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1926
1927         /*
1928          * Undocumented corner. Supposedly:
1929          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1930          */
1931         RTL_W16(IntrMitigate, 0x0000);
1932
1933         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1934
1935         RTL_W8(Cfg9346, Cfg9346_Lock);
1936
1937         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1938         RTL_R8(IntrMask);
1939
1940         RTL_W32(RxMissed, 0);
1941
1942         rtl_set_rx_mode(dev);
1943
1944         /* no early-rx interrupts */
1945         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1946
1947         /* Enable all known interrupts by setting the interrupt mask. */
1948         RTL_W16(IntrMask, tp->intr_event);
1949
1950         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1951 }
1952
1953 static void rtl_hw_start_8168(struct net_device *dev)
1954 {
1955         struct rtl8169_private *tp = netdev_priv(dev);
1956         void __iomem *ioaddr = tp->mmio_addr;
1957         struct pci_dev *pdev = tp->pci_dev;
1958         u8 ctl;
1959
1960         RTL_W8(Cfg9346, Cfg9346_Unlock);
1961
1962         RTL_W8(EarlyTxThres, EarlyTxThld);
1963
1964         rtl_set_rx_max_size(ioaddr);
1965
1966         rtl_set_rx_tx_config_registers(tp);
1967
1968         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1969
1970         RTL_W16(CPlusCmd, tp->cp_cmd);
1971
1972         /* Tx performance tweak. */
1973         pci_read_config_byte(pdev, 0x69, &ctl);
1974         ctl = (ctl & ~0x70) | 0x50;
1975         pci_write_config_byte(pdev, 0x69, ctl);
1976
1977         RTL_W16(IntrMitigate, 0x5151);
1978
1979         /* Work around for RxFIFO overflow. */
1980         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1981                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1982                 tp->intr_event &= ~RxOverflow;
1983         }
1984
1985         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1986
1987         RTL_W8(Cfg9346, Cfg9346_Lock);
1988
1989         RTL_R8(IntrMask);
1990
1991         RTL_W32(RxMissed, 0);
1992
1993         rtl_set_rx_mode(dev);
1994
1995         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1996
1997         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1998
1999         RTL_W16(IntrMask, tp->intr_event);
2000 }
2001
2002 static void rtl_hw_start_8101(struct net_device *dev)
2003 {
2004         struct rtl8169_private *tp = netdev_priv(dev);
2005         void __iomem *ioaddr = tp->mmio_addr;
2006         struct pci_dev *pdev = tp->pci_dev;
2007
2008         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2009                 pci_write_config_word(pdev, 0x68, 0x00);
2010                 pci_write_config_word(pdev, 0x69, 0x08);
2011         }
2012
2013         RTL_W8(Cfg9346, Cfg9346_Unlock);
2014
2015         RTL_W8(EarlyTxThres, EarlyTxThld);
2016
2017         rtl_set_rx_max_size(ioaddr);
2018
2019         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2020
2021         RTL_W16(CPlusCmd, tp->cp_cmd);
2022
2023         RTL_W16(IntrMitigate, 0x0000);
2024
2025         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2026
2027         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2028         rtl_set_rx_tx_config_registers(tp);
2029
2030         RTL_W8(Cfg9346, Cfg9346_Lock);
2031
2032         RTL_R8(IntrMask);
2033
2034         RTL_W32(RxMissed, 0);
2035
2036         rtl_set_rx_mode(dev);
2037
2038         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2039
2040         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2041
2042         RTL_W16(IntrMask, tp->intr_event);
2043 }
2044
2045 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2046 {
2047         struct rtl8169_private *tp = netdev_priv(dev);
2048         int ret = 0;
2049
2050         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2051                 return -EINVAL;
2052
2053         dev->mtu = new_mtu;
2054
2055         if (!netif_running(dev))
2056                 goto out;
2057
2058         rtl8169_down(dev);
2059
2060         rtl8169_set_rxbufsize(tp, dev);
2061
2062         ret = rtl8169_init_ring(dev);
2063         if (ret < 0)
2064                 goto out;
2065
2066         netif_poll_enable(dev);
2067
2068         rtl_hw_start(dev);
2069
2070         rtl8169_request_timer(dev);
2071
2072 out:
2073         return ret;
2074 }
2075
2076 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2077 {
2078         desc->addr = 0x0badbadbadbadbadull;
2079         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2080 }
2081
2082 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2083                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2084 {
2085         struct pci_dev *pdev = tp->pci_dev;
2086
2087         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2088                          PCI_DMA_FROMDEVICE);
2089         dev_kfree_skb(*sk_buff);
2090         *sk_buff = NULL;
2091         rtl8169_make_unusable_by_asic(desc);
2092 }
2093
2094 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2095 {
2096         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2097
2098         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2099 }
2100
2101 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2102                                        u32 rx_buf_sz)
2103 {
2104         desc->addr = cpu_to_le64(mapping);
2105         wmb();
2106         rtl8169_mark_to_asic(desc, rx_buf_sz);
2107 }
2108
2109 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2110                                             struct net_device *dev,
2111                                             struct RxDesc *desc, int rx_buf_sz,
2112                                             unsigned int align)
2113 {
2114         struct sk_buff *skb;
2115         dma_addr_t mapping;
2116         unsigned int pad;
2117
2118         pad = align ? align : NET_IP_ALIGN;
2119
2120         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2121         if (!skb)
2122                 goto err_out;
2123
2124         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2125
2126         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2127                                  PCI_DMA_FROMDEVICE);
2128
2129         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2130 out:
2131         return skb;
2132
2133 err_out:
2134         rtl8169_make_unusable_by_asic(desc);
2135         goto out;
2136 }
2137
2138 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2139 {
2140         unsigned int i;
2141
2142         for (i = 0; i < NUM_RX_DESC; i++) {
2143                 if (tp->Rx_skbuff[i]) {
2144                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2145                                             tp->RxDescArray + i);
2146                 }
2147         }
2148 }
2149
2150 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2151                            u32 start, u32 end)
2152 {
2153         u32 cur;
2154
2155         for (cur = start; end - cur != 0; cur++) {
2156                 struct sk_buff *skb;
2157                 unsigned int i = cur % NUM_RX_DESC;
2158
2159                 WARN_ON((s32)(end - cur) < 0);
2160
2161                 if (tp->Rx_skbuff[i])
2162                         continue;
2163
2164                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2165                                            tp->RxDescArray + i,
2166                                            tp->rx_buf_sz, tp->align);
2167                 if (!skb)
2168                         break;
2169
2170                 tp->Rx_skbuff[i] = skb;
2171         }
2172         return cur - start;
2173 }
2174
2175 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2176 {
2177         desc->opts1 |= cpu_to_le32(RingEnd);
2178 }
2179
2180 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2181 {
2182         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2183 }
2184
2185 static int rtl8169_init_ring(struct net_device *dev)
2186 {
2187         struct rtl8169_private *tp = netdev_priv(dev);
2188
2189         rtl8169_init_ring_indexes(tp);
2190
2191         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2192         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2193
2194         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2195                 goto err_out;
2196
2197         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2198
2199         return 0;
2200
2201 err_out:
2202         rtl8169_rx_clear(tp);
2203         return -ENOMEM;
2204 }
2205
2206 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2207                                  struct TxDesc *desc)
2208 {
2209         unsigned int len = tx_skb->len;
2210
2211         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2212         desc->opts1 = 0x00;
2213         desc->opts2 = 0x00;
2214         desc->addr = 0x00;
2215         tx_skb->len = 0;
2216 }
2217
2218 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2219 {
2220         unsigned int i;
2221
2222         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2223                 unsigned int entry = i % NUM_TX_DESC;
2224                 struct ring_info *tx_skb = tp->tx_skb + entry;
2225                 unsigned int len = tx_skb->len;
2226
2227                 if (len) {
2228                         struct sk_buff *skb = tx_skb->skb;
2229
2230                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2231                                              tp->TxDescArray + entry);
2232                         if (skb) {
2233                                 dev_kfree_skb(skb);
2234                                 tx_skb->skb = NULL;
2235                         }
2236                         tp->stats.tx_dropped++;
2237                 }
2238         }
2239         tp->cur_tx = tp->dirty_tx = 0;
2240 }
2241
2242 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2243 {
2244         struct rtl8169_private *tp = netdev_priv(dev);
2245
2246         PREPARE_DELAYED_WORK(&tp->task, task);
2247         schedule_delayed_work(&tp->task, 4);
2248 }
2249
2250 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2251 {
2252         struct rtl8169_private *tp = netdev_priv(dev);
2253         void __iomem *ioaddr = tp->mmio_addr;
2254
2255         synchronize_irq(dev->irq);
2256
2257         /* Wait for any pending NAPI task to complete */
2258         netif_poll_disable(dev);
2259
2260         rtl8169_irq_mask_and_ack(ioaddr);
2261
2262         netif_poll_enable(dev);
2263 }
2264
2265 static void rtl8169_reinit_task(struct work_struct *work)
2266 {
2267         struct rtl8169_private *tp =
2268                 container_of(work, struct rtl8169_private, task.work);
2269         struct net_device *dev = tp->dev;
2270         int ret;
2271
2272         rtnl_lock();
2273
2274         if (!netif_running(dev))
2275                 goto out_unlock;
2276
2277         rtl8169_wait_for_quiescence(dev);
2278         rtl8169_close(dev);
2279
2280         ret = rtl8169_open(dev);
2281         if (unlikely(ret < 0)) {
2282                 if (net_ratelimit() && netif_msg_drv(tp)) {
2283                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2284                                " Rescheduling.\n", dev->name, ret);
2285                 }
2286                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2287         }
2288
2289 out_unlock:
2290         rtnl_unlock();
2291 }
2292
2293 static void rtl8169_reset_task(struct work_struct *work)
2294 {
2295         struct rtl8169_private *tp =
2296                 container_of(work, struct rtl8169_private, task.work);
2297         struct net_device *dev = tp->dev;
2298
2299         rtnl_lock();
2300
2301         if (!netif_running(dev))
2302                 goto out_unlock;
2303
2304         rtl8169_wait_for_quiescence(dev);
2305
2306         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2307         rtl8169_tx_clear(tp);
2308
2309         if (tp->dirty_rx == tp->cur_rx) {
2310                 rtl8169_init_ring_indexes(tp);
2311                 rtl_hw_start(dev);
2312                 netif_wake_queue(dev);
2313         } else {
2314                 if (net_ratelimit() && netif_msg_intr(tp)) {
2315                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2316                                dev->name);
2317                 }
2318                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2319         }
2320
2321 out_unlock:
2322         rtnl_unlock();
2323 }
2324
2325 static void rtl8169_tx_timeout(struct net_device *dev)
2326 {
2327         struct rtl8169_private *tp = netdev_priv(dev);
2328
2329         rtl8169_hw_reset(tp->mmio_addr);
2330
2331         /* Let's wait a bit while any (async) irq lands on */
2332         rtl8169_schedule_work(dev, rtl8169_reset_task);
2333 }
2334
2335 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2336                               u32 opts1)
2337 {
2338         struct skb_shared_info *info = skb_shinfo(skb);
2339         unsigned int cur_frag, entry;
2340         struct TxDesc * uninitialized_var(txd);
2341
2342         entry = tp->cur_tx;
2343         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2344                 skb_frag_t *frag = info->frags + cur_frag;
2345                 dma_addr_t mapping;
2346                 u32 status, len;
2347                 void *addr;
2348
2349                 entry = (entry + 1) % NUM_TX_DESC;
2350
2351                 txd = tp->TxDescArray + entry;
2352                 len = frag->size;
2353                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2354                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2355
2356                 /* anti gcc 2.95.3 bugware (sic) */
2357                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2358
2359                 txd->opts1 = cpu_to_le32(status);
2360                 txd->addr = cpu_to_le64(mapping);
2361
2362                 tp->tx_skb[entry].len = len;
2363         }
2364
2365         if (cur_frag) {
2366                 tp->tx_skb[entry].skb = skb;
2367                 txd->opts1 |= cpu_to_le32(LastFrag);
2368         }
2369
2370         return cur_frag;
2371 }
2372
2373 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2374 {
2375         if (dev->features & NETIF_F_TSO) {
2376                 u32 mss = skb_shinfo(skb)->gso_size;
2377
2378                 if (mss)
2379                         return LargeSend | ((mss & MSSMask) << MSSShift);
2380         }
2381         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2382                 const struct iphdr *ip = ip_hdr(skb);
2383
2384                 if (ip->protocol == IPPROTO_TCP)
2385                         return IPCS | TCPCS;
2386                 else if (ip->protocol == IPPROTO_UDP)
2387                         return IPCS | UDPCS;
2388                 WARN_ON(1);     /* we need a WARN() */
2389         }
2390         return 0;
2391 }
2392
2393 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2394 {
2395         struct rtl8169_private *tp = netdev_priv(dev);
2396         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2397         struct TxDesc *txd = tp->TxDescArray + entry;
2398         void __iomem *ioaddr = tp->mmio_addr;
2399         dma_addr_t mapping;
2400         u32 status, len;
2401         u32 opts1;
2402         int ret = NETDEV_TX_OK;
2403
2404         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2405                 if (netif_msg_drv(tp)) {
2406                         printk(KERN_ERR
2407                                "%s: BUG! Tx Ring full when queue awake!\n",
2408                                dev->name);
2409                 }
2410                 goto err_stop;
2411         }
2412
2413         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2414                 goto err_stop;
2415
2416         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2417
2418         frags = rtl8169_xmit_frags(tp, skb, opts1);
2419         if (frags) {
2420                 len = skb_headlen(skb);
2421                 opts1 |= FirstFrag;
2422         } else {
2423                 len = skb->len;
2424
2425                 if (unlikely(len < ETH_ZLEN)) {
2426                         if (skb_padto(skb, ETH_ZLEN))
2427                                 goto err_update_stats;
2428                         len = ETH_ZLEN;
2429                 }
2430
2431                 opts1 |= FirstFrag | LastFrag;
2432                 tp->tx_skb[entry].skb = skb;
2433         }
2434
2435         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2436
2437         tp->tx_skb[entry].len = len;
2438         txd->addr = cpu_to_le64(mapping);
2439         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2440
2441         wmb();
2442
2443         /* anti gcc 2.95.3 bugware (sic) */
2444         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2445         txd->opts1 = cpu_to_le32(status);
2446
2447         dev->trans_start = jiffies;
2448
2449         tp->cur_tx += frags + 1;
2450
2451         smp_wmb();
2452
2453         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2454
2455         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2456                 netif_stop_queue(dev);
2457                 smp_rmb();
2458                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2459                         netif_wake_queue(dev);
2460         }
2461
2462 out:
2463         return ret;
2464
2465 err_stop:
2466         netif_stop_queue(dev);
2467         ret = NETDEV_TX_BUSY;
2468 err_update_stats:
2469         tp->stats.tx_dropped++;
2470         goto out;
2471 }
2472
2473 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2474 {
2475         struct rtl8169_private *tp = netdev_priv(dev);
2476         struct pci_dev *pdev = tp->pci_dev;
2477         void __iomem *ioaddr = tp->mmio_addr;
2478         u16 pci_status, pci_cmd;
2479
2480         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2481         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2482
2483         if (netif_msg_intr(tp)) {
2484                 printk(KERN_ERR
2485                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2486                        dev->name, pci_cmd, pci_status);
2487         }
2488
2489         /*
2490          * The recovery sequence below admits a very elaborated explanation:
2491          * - it seems to work;
2492          * - I did not see what else could be done;
2493          * - it makes iop3xx happy.
2494          *
2495          * Feel free to adjust to your needs.
2496          */
2497         if (pdev->broken_parity_status)
2498                 pci_cmd &= ~PCI_COMMAND_PARITY;
2499         else
2500                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2501
2502         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2503
2504         pci_write_config_word(pdev, PCI_STATUS,
2505                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2506                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2507                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2508
2509         /* The infamous DAC f*ckup only happens at boot time */
2510         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2511                 if (netif_msg_intr(tp))
2512                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2513                 tp->cp_cmd &= ~PCIDAC;
2514                 RTL_W16(CPlusCmd, tp->cp_cmd);
2515                 dev->features &= ~NETIF_F_HIGHDMA;
2516         }
2517
2518         rtl8169_hw_reset(ioaddr);
2519
2520         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2521 }
2522
2523 static void rtl8169_tx_interrupt(struct net_device *dev,
2524                                  struct rtl8169_private *tp,
2525                                  void __iomem *ioaddr)
2526 {
2527         unsigned int dirty_tx, tx_left;
2528
2529         dirty_tx = tp->dirty_tx;
2530         smp_rmb();
2531         tx_left = tp->cur_tx - dirty_tx;
2532
2533         while (tx_left > 0) {
2534                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2535                 struct ring_info *tx_skb = tp->tx_skb + entry;
2536                 u32 len = tx_skb->len;
2537                 u32 status;
2538
2539                 rmb();
2540                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2541                 if (status & DescOwn)
2542                         break;
2543
2544                 tp->stats.tx_bytes += len;
2545                 tp->stats.tx_packets++;
2546
2547                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2548
2549                 if (status & LastFrag) {
2550                         dev_kfree_skb_irq(tx_skb->skb);
2551                         tx_skb->skb = NULL;
2552                 }
2553                 dirty_tx++;
2554                 tx_left--;
2555         }
2556
2557         if (tp->dirty_tx != dirty_tx) {
2558                 tp->dirty_tx = dirty_tx;
2559                 smp_wmb();
2560                 if (netif_queue_stopped(dev) &&
2561                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2562                         netif_wake_queue(dev);
2563                 }
2564         }
2565 }
2566
2567 static inline int rtl8169_fragmented_frame(u32 status)
2568 {
2569         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2570 }
2571
2572 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2573 {
2574         u32 opts1 = le32_to_cpu(desc->opts1);
2575         u32 status = opts1 & RxProtoMask;
2576
2577         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2578             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2579             ((status == RxProtoIP) && !(opts1 & IPFail)))
2580                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2581         else
2582                 skb->ip_summed = CHECKSUM_NONE;
2583 }
2584
2585 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2586                                        struct rtl8169_private *tp, int pkt_size,
2587                                        dma_addr_t addr)
2588 {
2589         struct sk_buff *skb;
2590         bool done = false;
2591
2592         if (pkt_size >= rx_copybreak)
2593                 goto out;
2594
2595         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2596         if (!skb)
2597                 goto out;
2598
2599         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2600                                     PCI_DMA_FROMDEVICE);
2601         skb_reserve(skb, NET_IP_ALIGN);
2602         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2603         *sk_buff = skb;
2604         done = true;
2605 out:
2606         return done;
2607 }
2608
2609 static int rtl8169_rx_interrupt(struct net_device *dev,
2610                                 struct rtl8169_private *tp,
2611                                 void __iomem *ioaddr)
2612 {
2613         unsigned int cur_rx, rx_left;
2614         unsigned int delta, count;
2615
2616         cur_rx = tp->cur_rx;
2617         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2618         rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2619
2620         for (; rx_left > 0; rx_left--, cur_rx++) {
2621                 unsigned int entry = cur_rx % NUM_RX_DESC;
2622                 struct RxDesc *desc = tp->RxDescArray + entry;
2623                 u32 status;
2624
2625                 rmb();
2626                 status = le32_to_cpu(desc->opts1);
2627
2628                 if (status & DescOwn)
2629                         break;
2630                 if (unlikely(status & RxRES)) {
2631                         if (netif_msg_rx_err(tp)) {
2632                                 printk(KERN_INFO
2633                                        "%s: Rx ERROR. status = %08x\n",
2634                                        dev->name, status);
2635                         }
2636                         tp->stats.rx_errors++;
2637                         if (status & (RxRWT | RxRUNT))
2638                                 tp->stats.rx_length_errors++;
2639                         if (status & RxCRC)
2640                                 tp->stats.rx_crc_errors++;
2641                         if (status & RxFOVF) {
2642                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2643                                 tp->stats.rx_fifo_errors++;
2644                         }
2645                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2646                 } else {
2647                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2648                         dma_addr_t addr = le64_to_cpu(desc->addr);
2649                         int pkt_size = (status & 0x00001FFF) - 4;
2650                         struct pci_dev *pdev = tp->pci_dev;
2651
2652                         /*
2653                          * The driver does not support incoming fragmented
2654                          * frames. They are seen as a symptom of over-mtu
2655                          * sized frames.
2656                          */
2657                         if (unlikely(rtl8169_fragmented_frame(status))) {
2658                                 tp->stats.rx_dropped++;
2659                                 tp->stats.rx_length_errors++;
2660                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2661                                 continue;
2662                         }
2663
2664                         rtl8169_rx_csum(skb, desc);
2665
2666                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2667                                 pci_dma_sync_single_for_device(pdev, addr,
2668                                         pkt_size, PCI_DMA_FROMDEVICE);
2669                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2670                         } else {
2671                                 pci_unmap_single(pdev, addr, pkt_size,
2672                                                  PCI_DMA_FROMDEVICE);
2673                                 tp->Rx_skbuff[entry] = NULL;
2674                         }
2675
2676                         skb_put(skb, pkt_size);
2677                         skb->protocol = eth_type_trans(skb, dev);
2678
2679                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2680                                 rtl8169_rx_skb(skb);
2681
2682                         dev->last_rx = jiffies;
2683                         tp->stats.rx_bytes += pkt_size;
2684                         tp->stats.rx_packets++;
2685                 }
2686
2687                 /* Work around for AMD plateform. */
2688                 if ((desc->opts2 & 0xfffe000) &&
2689                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2690                         desc->opts2 = 0;
2691                         cur_rx++;
2692                 }
2693         }
2694
2695         count = cur_rx - tp->cur_rx;
2696         tp->cur_rx = cur_rx;
2697
2698         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2699         if (!delta && count && netif_msg_intr(tp))
2700                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2701         tp->dirty_rx += delta;
2702
2703         /*
2704          * FIXME: until there is periodic timer to try and refill the ring,
2705          * a temporary shortage may definitely kill the Rx process.
2706          * - disable the asic to try and avoid an overflow and kick it again
2707          *   after refill ?
2708          * - how do others driver handle this condition (Uh oh...).
2709          */
2710         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2711                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2712
2713         return count;
2714 }
2715
2716 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2717 {
2718         struct net_device *dev = dev_instance;
2719         struct rtl8169_private *tp = netdev_priv(dev);
2720         int boguscnt = max_interrupt_work;
2721         void __iomem *ioaddr = tp->mmio_addr;
2722         int status;
2723         int handled = 0;
2724
2725         do {
2726                 status = RTL_R16(IntrStatus);
2727
2728                 /* hotplug/major error/no more work/shared irq */
2729                 if ((status == 0xFFFF) || !status)
2730                         break;
2731
2732                 handled = 1;
2733
2734                 if (unlikely(!netif_running(dev))) {
2735                         rtl8169_asic_down(ioaddr);
2736                         goto out;
2737                 }
2738
2739                 status &= tp->intr_mask;
2740                 RTL_W16(IntrStatus,
2741                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2742
2743                 if (!(status & tp->intr_event))
2744                         break;
2745
2746                 /* Work around for rx fifo overflow */
2747                 if (unlikely(status & RxFIFOOver) &&
2748                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2749                         netif_stop_queue(dev);
2750                         rtl8169_tx_timeout(dev);
2751                         break;
2752                 }
2753
2754                 if (unlikely(status & SYSErr)) {
2755                         rtl8169_pcierr_interrupt(dev);
2756                         break;
2757                 }
2758
2759                 if (status & LinkChg)
2760                         rtl8169_check_link_status(dev, tp, ioaddr);
2761
2762 #ifdef CONFIG_R8169_NAPI
2763                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2764                 tp->intr_mask = ~tp->napi_event;
2765
2766                 if (likely(netif_rx_schedule_prep(dev)))
2767                         __netif_rx_schedule(dev);
2768                 else if (netif_msg_intr(tp)) {
2769                         printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2770                                dev->name, status);
2771                 }
2772                 break;
2773 #else
2774                 /* Rx interrupt */
2775                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2776                         rtl8169_rx_interrupt(dev, tp, ioaddr);
2777
2778                 /* Tx interrupt */
2779                 if (status & (TxOK | TxErr))
2780                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2781 #endif
2782
2783                 boguscnt--;
2784         } while (boguscnt > 0);
2785
2786         if (boguscnt <= 0) {
2787                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2788                         printk(KERN_WARNING
2789                                "%s: Too much work at interrupt!\n", dev->name);
2790                 }
2791                 /* Clear all interrupt sources. */
2792                 RTL_W16(IntrStatus, 0xffff);
2793         }
2794 out:
2795         return IRQ_RETVAL(handled);
2796 }
2797
2798 #ifdef CONFIG_R8169_NAPI
2799 static int rtl8169_poll(struct net_device *dev, int *budget)
2800 {
2801         unsigned int work_done, work_to_do = min(*budget, dev->quota);
2802         struct rtl8169_private *tp = netdev_priv(dev);
2803         void __iomem *ioaddr = tp->mmio_addr;
2804
2805         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2806         rtl8169_tx_interrupt(dev, tp, ioaddr);
2807
2808         *budget -= work_done;
2809         dev->quota -= work_done;
2810
2811         if (work_done < work_to_do) {
2812                 netif_rx_complete(dev);
2813                 tp->intr_mask = 0xffff;
2814                 /*
2815                  * 20040426: the barrier is not strictly required but the
2816                  * behavior of the irq handler could be less predictable
2817                  * without it. Btw, the lack of flush for the posted pci
2818                  * write is safe - FR
2819                  */
2820                 smp_wmb();
2821                 RTL_W16(IntrMask, tp->intr_event);
2822         }
2823
2824         return (work_done >= work_to_do);
2825 }
2826 #endif
2827
2828 static void rtl8169_down(struct net_device *dev)
2829 {
2830         struct rtl8169_private *tp = netdev_priv(dev);
2831         void __iomem *ioaddr = tp->mmio_addr;
2832         unsigned int poll_locked = 0;
2833         unsigned int intrmask;
2834
2835         rtl8169_delete_timer(dev);
2836
2837         netif_stop_queue(dev);
2838
2839 core_down:
2840         spin_lock_irq(&tp->lock);
2841
2842         rtl8169_asic_down(ioaddr);
2843
2844         /* Update the error counts. */
2845         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2846         RTL_W32(RxMissed, 0);
2847
2848         spin_unlock_irq(&tp->lock);
2849
2850         synchronize_irq(dev->irq);
2851
2852         if (!poll_locked) {
2853                 netif_poll_disable(dev);
2854                 poll_locked++;
2855         }
2856
2857         /* Give a racing hard_start_xmit a few cycles to complete. */
2858         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2859
2860         /*
2861          * And now for the 50k$ question: are IRQ disabled or not ?
2862          *
2863          * Two paths lead here:
2864          * 1) dev->close
2865          *    -> netif_running() is available to sync the current code and the
2866          *       IRQ handler. See rtl8169_interrupt for details.
2867          * 2) dev->change_mtu
2868          *    -> rtl8169_poll can not be issued again and re-enable the
2869          *       interruptions. Let's simply issue the IRQ down sequence again.
2870          *
2871          * No loop if hotpluged or major error (0xffff).
2872          */
2873         intrmask = RTL_R16(IntrMask);
2874         if (intrmask && (intrmask != 0xffff))
2875                 goto core_down;
2876
2877         rtl8169_tx_clear(tp);
2878
2879         rtl8169_rx_clear(tp);
2880 }
2881
2882 static int rtl8169_close(struct net_device *dev)
2883 {
2884         struct rtl8169_private *tp = netdev_priv(dev);
2885         struct pci_dev *pdev = tp->pci_dev;
2886
2887         rtl8169_down(dev);
2888
2889         free_irq(dev->irq, dev);
2890
2891         netif_poll_enable(dev);
2892
2893         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2894                             tp->RxPhyAddr);
2895         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2896                             tp->TxPhyAddr);
2897         tp->TxDescArray = NULL;
2898         tp->RxDescArray = NULL;
2899
2900         return 0;
2901 }
2902
2903 static void rtl_set_rx_mode(struct net_device *dev)
2904 {
2905         struct rtl8169_private *tp = netdev_priv(dev);
2906         void __iomem *ioaddr = tp->mmio_addr;
2907         unsigned long flags;
2908         u32 mc_filter[2];       /* Multicast hash filter */
2909         int rx_mode;
2910         u32 tmp = 0;
2911
2912         if (dev->flags & IFF_PROMISC) {
2913                 /* Unconditionally log net taps. */
2914                 if (netif_msg_link(tp)) {
2915                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2916                                dev->name);
2917                 }
2918                 rx_mode =
2919                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2920                     AcceptAllPhys;
2921                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2922         } else if ((dev->mc_count > multicast_filter_limit)
2923                    || (dev->flags & IFF_ALLMULTI)) {
2924                 /* Too many to filter perfectly -- accept all multicasts. */
2925                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2926                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2927         } else {
2928                 struct dev_mc_list *mclist;
2929                 unsigned int i;
2930
2931                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2932                 mc_filter[1] = mc_filter[0] = 0;
2933                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2934                      i++, mclist = mclist->next) {
2935                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2936                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2937                         rx_mode |= AcceptMulticast;
2938                 }
2939         }
2940
2941         spin_lock_irqsave(&tp->lock, flags);
2942
2943         tmp = rtl8169_rx_config | rx_mode |
2944               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2945
2946         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2947             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2948             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2949             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2950             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2951                 mc_filter[0] = 0xffffffff;
2952                 mc_filter[1] = 0xffffffff;
2953         }
2954
2955         RTL_W32(MAR0 + 0, mc_filter[0]);
2956         RTL_W32(MAR0 + 4, mc_filter[1]);
2957
2958         RTL_W32(RxConfig, tmp);
2959
2960         spin_unlock_irqrestore(&tp->lock, flags);
2961 }
2962
2963 /**
2964  *  rtl8169_get_stats - Get rtl8169 read/write statistics
2965  *  @dev: The Ethernet Device to get statistics for
2966  *
2967  *  Get TX/RX statistics for rtl8169
2968  */
2969 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2970 {
2971         struct rtl8169_private *tp = netdev_priv(dev);
2972         void __iomem *ioaddr = tp->mmio_addr;
2973         unsigned long flags;
2974
2975         if (netif_running(dev)) {
2976                 spin_lock_irqsave(&tp->lock, flags);
2977                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2978                 RTL_W32(RxMissed, 0);
2979                 spin_unlock_irqrestore(&tp->lock, flags);
2980         }
2981
2982         return &tp->stats;
2983 }
2984
2985 #ifdef CONFIG_PM
2986
2987 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2988 {
2989         struct net_device *dev = pci_get_drvdata(pdev);
2990         struct rtl8169_private *tp = netdev_priv(dev);
2991         void __iomem *ioaddr = tp->mmio_addr;
2992
2993         if (!netif_running(dev))
2994                 goto out_pci_suspend;
2995
2996         netif_device_detach(dev);
2997         netif_stop_queue(dev);
2998
2999         spin_lock_irq(&tp->lock);
3000
3001         rtl8169_asic_down(ioaddr);
3002
3003         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3004         RTL_W32(RxMissed, 0);
3005
3006         spin_unlock_irq(&tp->lock);
3007
3008 out_pci_suspend:
3009         pci_save_state(pdev);
3010         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3011         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3012
3013         return 0;
3014 }
3015
3016 static int rtl8169_resume(struct pci_dev *pdev)
3017 {
3018         struct net_device *dev = pci_get_drvdata(pdev);
3019
3020         pci_set_power_state(pdev, PCI_D0);
3021         pci_restore_state(pdev);
3022         pci_enable_wake(pdev, PCI_D0, 0);
3023
3024         if (!netif_running(dev))
3025                 goto out;
3026
3027         netif_device_attach(dev);
3028
3029         rtl8169_schedule_work(dev, rtl8169_reset_task);
3030 out:
3031         return 0;
3032 }
3033
3034 #endif /* CONFIG_PM */
3035
3036 static struct pci_driver rtl8169_pci_driver = {
3037         .name           = MODULENAME,
3038         .id_table       = rtl8169_pci_tbl,
3039         .probe          = rtl8169_init_one,
3040         .remove         = __devexit_p(rtl8169_remove_one),
3041 #ifdef CONFIG_PM
3042         .suspend        = rtl8169_suspend,
3043         .resume         = rtl8169_resume,
3044 #endif
3045 };
3046
3047 static int __init rtl8169_init_module(void)
3048 {
3049         return pci_register_driver(&rtl8169_pci_driver);
3050 }
3051
3052 static void __exit rtl8169_cleanup_module(void)
3053 {
3054         pci_unregister_driver(&rtl8169_pci_driver);
3055 }
3056
3057 module_init(rtl8169_init_module);
3058 module_exit(rtl8169_cleanup_module);