Merge branch 'linux-next' of git://git.infradead.org/ubifs-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8544ds.dts
1 /*
2  * MPC8544 DS Device Tree Source
3  *
4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13 / {
14         model = "MPC8544DS";
15         compatible = "MPC8544DS", "MPC85xxDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 serial0 = &serial0;
23                 serial1 = &serial1;
24                 pci0 = &pci0;
25                 pci1 = &pci1;
26                 pci2 = &pci2;
27                 pci3 = &pci3;
28         };
29
30         cpus {
31                 #address-cells = <1>;
32                 #size-cells = <0>;
33
34                 PowerPC,8544@0 {
35                         device_type = "cpu";
36                         reg = <0x0>;
37                         d-cache-line-size = <32>;       // 32 bytes
38                         i-cache-line-size = <32>;       // 32 bytes
39                         d-cache-size = <0x8000>;                // L1, 32K
40                         i-cache-size = <0x8000>;                // L1, 32K
41                         timebase-frequency = <0>;
42                         bus-frequency = <0>;
43                         clock-frequency = <0>;
44                         next-level-cache = <&L2>;
45                 };
46         };
47
48         memory {
49                 device_type = "memory";
50                 reg = <0x0 0x0>;        // Filled by U-Boot
51         };
52
53         soc8544@e0000000 {
54                 #address-cells = <1>;
55                 #size-cells = <1>;
56                 device_type = "soc";
57                 compatible = "simple-bus";
58
59                 ranges = <0x0 0xe0000000 0x100000>;
60                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
61                 bus-frequency = <0>;            // Filled out by uboot.
62
63                 memory-controller@2000 {
64                         compatible = "fsl,8544-memory-controller";
65                         reg = <0x2000 0x1000>;
66                         interrupt-parent = <&mpic>;
67                         interrupts = <18 2>;
68                 };
69
70                 L2: l2-cache-controller@20000 {
71                         compatible = "fsl,8544-l2-cache-controller";
72                         reg = <0x20000 0x1000>;
73                         cache-line-size = <32>; // 32 bytes
74                         cache-size = <0x40000>; // L2, 256K
75                         interrupt-parent = <&mpic>;
76                         interrupts = <16 2>;
77                 };
78
79                 i2c@3000 {
80                         #address-cells = <1>;
81                         #size-cells = <0>;
82                         cell-index = <0>;
83                         compatible = "fsl-i2c";
84                         reg = <0x3000 0x100>;
85                         interrupts = <43 2>;
86                         interrupt-parent = <&mpic>;
87                         dfsrr;
88                 };
89
90                 i2c@3100 {
91                         #address-cells = <1>;
92                         #size-cells = <0>;
93                         cell-index = <1>;
94                         compatible = "fsl-i2c";
95                         reg = <0x3100 0x100>;
96                         interrupts = <43 2>;
97                         interrupt-parent = <&mpic>;
98                         dfsrr;
99                 };
100
101                 mdio@24520 {
102                         #address-cells = <1>;
103                         #size-cells = <0>;
104                         compatible = "fsl,gianfar-mdio";
105                         reg = <0x24520 0x20>;
106
107                         phy0: ethernet-phy@0 {
108                                 interrupt-parent = <&mpic>;
109                                 interrupts = <10 1>;
110                                 reg = <0x0>;
111                                 device_type = "ethernet-phy";
112                         };
113                         phy1: ethernet-phy@1 {
114                                 interrupt-parent = <&mpic>;
115                                 interrupts = <10 1>;
116                                 reg = <0x1>;
117                                 device_type = "ethernet-phy";
118                         };
119
120                         tbi0: tbi-phy@11 {
121                                 reg = <0x11>;
122                                 device_type = "tbi-phy";
123                         };
124                 };
125
126                 mdio@26520 {
127                         #address-cells = <1>;
128                         #size-cells = <0>;
129                         compatible = "fsl,gianfar-tbi";
130                         reg = <0x26520 0x20>;
131
132                         tbi1: tbi-phy@11 {
133                                 reg = <0x11>;
134                                 device_type = "tbi-phy";
135                         };
136                 };
137
138
139                 dma@21300 {
140                         #address-cells = <1>;
141                         #size-cells = <1>;
142                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
143                         reg = <0x21300 0x4>;
144                         ranges = <0x0 0x21100 0x200>;
145                         cell-index = <0>;
146                         dma-channel@0 {
147                                 compatible = "fsl,mpc8544-dma-channel",
148                                                 "fsl,eloplus-dma-channel";
149                                 reg = <0x0 0x80>;
150                                 cell-index = <0>;
151                                 interrupt-parent = <&mpic>;
152                                 interrupts = <20 2>;
153                         };
154                         dma-channel@80 {
155                                 compatible = "fsl,mpc8544-dma-channel",
156                                                 "fsl,eloplus-dma-channel";
157                                 reg = <0x80 0x80>;
158                                 cell-index = <1>;
159                                 interrupt-parent = <&mpic>;
160                                 interrupts = <21 2>;
161                         };
162                         dma-channel@100 {
163                                 compatible = "fsl,mpc8544-dma-channel",
164                                                 "fsl,eloplus-dma-channel";
165                                 reg = <0x100 0x80>;
166                                 cell-index = <2>;
167                                 interrupt-parent = <&mpic>;
168                                 interrupts = <22 2>;
169                         };
170                         dma-channel@180 {
171                                 compatible = "fsl,mpc8544-dma-channel",
172                                                 "fsl,eloplus-dma-channel";
173                                 reg = <0x180 0x80>;
174                                 cell-index = <3>;
175                                 interrupt-parent = <&mpic>;
176                                 interrupts = <23 2>;
177                         };
178                 };
179
180                 enet0: ethernet@24000 {
181                         cell-index = <0>;
182                         device_type = "network";
183                         model = "TSEC";
184                         compatible = "gianfar";
185                         reg = <0x24000 0x1000>;
186                         local-mac-address = [ 00 00 00 00 00 00 ];
187                         interrupts = <29 2 30 2 34 2>;
188                         interrupt-parent = <&mpic>;
189                         phy-handle = <&phy0>;
190                         tbi-handle = <&tbi0>;
191                         phy-connection-type = "rgmii-id";
192                 };
193
194                 enet1: ethernet@26000 {
195                         cell-index = <1>;
196                         device_type = "network";
197                         model = "TSEC";
198                         compatible = "gianfar";
199                         reg = <0x26000 0x1000>;
200                         local-mac-address = [ 00 00 00 00 00 00 ];
201                         interrupts = <31 2 32 2 33 2>;
202                         interrupt-parent = <&mpic>;
203                         phy-handle = <&phy1>;
204                         tbi-handle = <&tbi1>;
205                         phy-connection-type = "rgmii-id";
206                 };
207
208                 serial0: serial@4500 {
209                         cell-index = <0>;
210                         device_type = "serial";
211                         compatible = "ns16550";
212                         reg = <0x4500 0x100>;
213                         clock-frequency = <0>;
214                         interrupts = <42 2>;
215                         interrupt-parent = <&mpic>;
216                 };
217
218                 serial1: serial@4600 {
219                         cell-index = <1>;
220                         device_type = "serial";
221                         compatible = "ns16550";
222                         reg = <0x4600 0x100>;
223                         clock-frequency = <0>;
224                         interrupts = <42 2>;
225                         interrupt-parent = <&mpic>;
226                 };
227
228                 global-utilities@e0000 {        //global utilities block
229                         compatible = "fsl,mpc8548-guts";
230                         reg = <0xe0000 0x1000>;
231                         fsl,has-rstcr;
232                 };
233
234                 crypto@30000 {
235                         compatible = "fsl,sec2.1", "fsl,sec2.0";
236                         reg = <0x30000 0x10000>;
237                         interrupts = <45 2>;
238                         interrupt-parent = <&mpic>;
239                         fsl,num-channels = <4>;
240                         fsl,channel-fifo-len = <24>;
241                         fsl,exec-units-mask = <0xfe>;
242                         fsl,descriptor-types-mask = <0x12b0ebf>;
243                 };
244
245                 mpic: pic@40000 {
246                         interrupt-controller;
247                         #address-cells = <0>;
248                         #interrupt-cells = <2>;
249                         reg = <0x40000 0x40000>;
250                         compatible = "chrp,open-pic";
251                         device_type = "open-pic";
252                 };
253
254                 msi@41600 {
255                         compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
256                         reg = <0x41600 0x80>;
257                         msi-available-ranges = <0 0x100>;
258                         interrupts = <
259                                 0xe0 0
260                                 0xe1 0
261                                 0xe2 0
262                                 0xe3 0
263                                 0xe4 0
264                                 0xe5 0
265                                 0xe6 0
266                                 0xe7 0>;
267                         interrupt-parent = <&mpic>;
268                 };
269         };
270
271         pci0: pci@e0008000 {
272                 cell-index = <0>;
273                 compatible = "fsl,mpc8540-pci";
274                 device_type = "pci";
275                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
276                 interrupt-map = <
277
278                         /* IDSEL 0x11 J17 Slot 1 */
279                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
280                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
281                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
282                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
283
284                         /* IDSEL 0x12 J16 Slot 2 */
285
286                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
287                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
288                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
289                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
290
291                 interrupt-parent = <&mpic>;
292                 interrupts = <24 2>;
293                 bus-range = <0 255>;
294                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
295                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
296                 clock-frequency = <66666666>;
297                 #interrupt-cells = <1>;
298                 #size-cells = <2>;
299                 #address-cells = <3>;
300                 reg = <0xe0008000 0x1000>;
301         };
302
303         pci1: pcie@e0009000 {
304                 cell-index = <1>;
305                 compatible = "fsl,mpc8548-pcie";
306                 device_type = "pci";
307                 #interrupt-cells = <1>;
308                 #size-cells = <2>;
309                 #address-cells = <3>;
310                 reg = <0xe0009000 0x1000>;
311                 bus-range = <0 255>;
312                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
313                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
314                 clock-frequency = <33333333>;
315                 interrupt-parent = <&mpic>;
316                 interrupts = <26 2>;
317                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
318                 interrupt-map = <
319                         /* IDSEL 0x0 */
320                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
321                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
322                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
323                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
324                         >;
325                 pcie@0 {
326                         reg = <0x0 0x0 0x0 0x0 0x0>;
327                         #size-cells = <2>;
328                         #address-cells = <3>;
329                         device_type = "pci";
330                         ranges = <0x2000000 0x0 0x80000000
331                                   0x2000000 0x0 0x80000000
332                                   0x0 0x20000000
333
334                                   0x1000000 0x0 0x0
335                                   0x1000000 0x0 0x0
336                                   0x0 0x10000>;
337                 };
338         };
339
340         pci2: pcie@e000a000 {
341                 cell-index = <2>;
342                 compatible = "fsl,mpc8548-pcie";
343                 device_type = "pci";
344                 #interrupt-cells = <1>;
345                 #size-cells = <2>;
346                 #address-cells = <3>;
347                 reg = <0xe000a000 0x1000>;
348                 bus-range = <0 255>;
349                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
350                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
351                 clock-frequency = <33333333>;
352                 interrupt-parent = <&mpic>;
353                 interrupts = <25 2>;
354                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
355                 interrupt-map = <
356                         /* IDSEL 0x0 */
357                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
358                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
359                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
360                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
361                         >;
362                 pcie@0 {
363                         reg = <0x0 0x0 0x0 0x0 0x0>;
364                         #size-cells = <2>;
365                         #address-cells = <3>;
366                         device_type = "pci";
367                         ranges = <0x2000000 0x0 0xa0000000
368                                   0x2000000 0x0 0xa0000000
369                                   0x0 0x10000000
370
371                                   0x1000000 0x0 0x0
372                                   0x1000000 0x0 0x0
373                                   0x0 0x10000>;
374                 };
375         };
376
377         pci3: pcie@e000b000 {
378                 cell-index = <3>;
379                 compatible = "fsl,mpc8548-pcie";
380                 device_type = "pci";
381                 #interrupt-cells = <1>;
382                 #size-cells = <2>;
383                 #address-cells = <3>;
384                 reg = <0xe000b000 0x1000>;
385                 bus-range = <0 255>;
386                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
387                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
388                 clock-frequency = <33333333>;
389                 interrupt-parent = <&mpic>;
390                 interrupts = <27 2>;
391                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
392                 interrupt-map = <
393                         // IDSEL 0x1c  USB
394                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
395                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
396                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
397                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
398
399                         // IDSEL 0x1d  Audio
400                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
401
402                         // IDSEL 0x1e Legacy
403                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
404                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
405
406                         // IDSEL 0x1f IDE/SATA
407                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
408                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
409                 >;
410
411                 pcie@0 {
412                         reg = <0x0 0x0 0x0 0x0 0x0>;
413                         #size-cells = <2>;
414                         #address-cells = <3>;
415                         device_type = "pci";
416                         ranges = <0x2000000 0x0 0xb0000000
417                                   0x2000000 0x0 0xb0000000
418                                   0x0 0x100000
419
420                                   0x1000000 0x0 0x0
421                                   0x1000000 0x0 0x0
422                                   0x0 0x100000>;
423
424                         uli1575@0 {
425                                 reg = <0x0 0x0 0x0 0x0 0x0>;
426                                 #size-cells = <2>;
427                                 #address-cells = <3>;
428                                 ranges = <0x2000000 0x0 0xb0000000
429                                           0x2000000 0x0 0xb0000000
430                                           0x0 0x100000
431
432                                           0x1000000 0x0 0x0
433                                           0x1000000 0x0 0x0
434                                           0x0 0x100000>;
435                                 isa@1e {
436                                         device_type = "isa";
437                                         #interrupt-cells = <2>;
438                                         #size-cells = <1>;
439                                         #address-cells = <2>;
440                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
441                                         ranges = <0x1 0x0
442                                                   0x1000000 0x0 0x0
443                                                   0x1000>;
444                                         interrupt-parent = <&i8259>;
445
446                                         i8259: interrupt-controller@20 {
447                                                 reg = <0x1 0x20 0x2
448                                                        0x1 0xa0 0x2
449                                                        0x1 0x4d0 0x2>;
450                                                 interrupt-controller;
451                                                 device_type = "interrupt-controller";
452                                                 #address-cells = <0>;
453                                                 #interrupt-cells = <2>;
454                                                 compatible = "chrp,iic";
455                                                 interrupts = <9 2>;
456                                                 interrupt-parent = <&mpic>;
457                                         };
458
459                                         i8042@60 {
460                                                 #size-cells = <0>;
461                                                 #address-cells = <1>;
462                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
463                                                 interrupts = <1 3 12 3>;
464                                                 interrupt-parent = <&i8259>;
465
466                                                 keyboard@0 {
467                                                         reg = <0x0>;
468                                                         compatible = "pnpPNP,303";
469                                                 };
470
471                                                 mouse@1 {
472                                                         reg = <0x1>;
473                                                         compatible = "pnpPNP,f03";
474                                                 };
475                                         };
476
477                                         rtc@70 {
478                                                 compatible = "pnpPNP,b00";
479                                                 reg = <0x1 0x70 0x2>;
480                                         };
481
482                                         gpio@400 {
483                                                 reg = <0x1 0x400 0x80>;
484                                         };
485                                 };
486                         };
487                 };
488         };
489 };