Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc836x_mds.dts
1 /*
2  * MPC8360E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 /*
14 /memreserve/    00000000 1000000;
15 */
16
17 /dts-v1/;
18
19 / {
20         model = "MPC8360MDS";
21         compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
22         #address-cells = <1>;
23         #size-cells = <1>;
24
25         aliases {
26                 ethernet0 = &enet0;
27                 ethernet1 = &enet1;
28                 serial0 = &serial0;
29                 serial1 = &serial1;
30                 pci0 = &pci0;
31         };
32
33         cpus {
34                 #address-cells = <1>;
35                 #size-cells = <0>;
36
37                 PowerPC,8360@0 {
38                         device_type = "cpu";
39                         reg = <0x0>;
40                         d-cache-line-size = <32>;       // 32 bytes
41                         i-cache-line-size = <32>;       // 32 bytes
42                         d-cache-size = <32768>;         // L1, 32K
43                         i-cache-size = <32768>;         // L1, 32K
44                         timebase-frequency = <66000000>;
45                         bus-frequency = <264000000>;
46                         clock-frequency = <528000000>;
47                 };
48         };
49
50         memory {
51                 device_type = "memory";
52                 reg = <0x00000000 0x10000000>;
53         };
54
55         localbus@e0005000 {
56                 #address-cells = <2>;
57                 #size-cells = <1>;
58                 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
59                              "simple-bus";
60                 reg = <0xe0005000 0xd8>;
61                 ranges = <0 0 0xfe000000 0x02000000
62                           1 0 0xf8000000 0x00008000>;
63
64                 flash@0,0 {
65                         compatible = "cfi-flash";
66                         reg = <0 0 0x2000000>;
67                         bank-width = <2>;
68                         device-width = <1>;
69                 };
70
71                 bcsr@1,0 {
72                         device_type = "board-control";
73                         reg = <1 0 0x8000>;
74                 };
75         };
76
77         soc8360@e0000000 {
78                 #address-cells = <1>;
79                 #size-cells = <1>;
80                 device_type = "soc";
81                 compatible = "simple-bus";
82                 ranges = <0x0 0xe0000000 0x00100000>;
83                 reg = <0xe0000000 0x00000200>;
84                 bus-frequency = <264000000>;
85
86                 wdt@200 {
87                         device_type = "watchdog";
88                         compatible = "mpc83xx_wdt";
89                         reg = <0x200 0x100>;
90                 };
91
92                 i2c@3000 {
93                         #address-cells = <1>;
94                         #size-cells = <0>;
95                         cell-index = <0>;
96                         compatible = "fsl-i2c";
97                         reg = <0x3000 0x100>;
98                         interrupts = <14 0x8>;
99                         interrupt-parent = <&ipic>;
100                         dfsrr;
101
102                         rtc@68 {
103                                 compatible = "dallas,ds1374";
104                                 reg = <0x68>;
105                         };
106                 };
107
108                 i2c@3100 {
109                         #address-cells = <1>;
110                         #size-cells = <0>;
111                         cell-index = <1>;
112                         compatible = "fsl-i2c";
113                         reg = <0x3100 0x100>;
114                         interrupts = <15 0x8>;
115                         interrupt-parent = <&ipic>;
116                         dfsrr;
117                 };
118
119                 serial0: serial@4500 {
120                         cell-index = <0>;
121                         device_type = "serial";
122                         compatible = "ns16550";
123                         reg = <0x4500 0x100>;
124                         clock-frequency = <264000000>;
125                         interrupts = <9 0x8>;
126                         interrupt-parent = <&ipic>;
127                 };
128
129                 serial1: serial@4600 {
130                         cell-index = <1>;
131                         device_type = "serial";
132                         compatible = "ns16550";
133                         reg = <0x4600 0x100>;
134                         clock-frequency = <264000000>;
135                         interrupts = <10 0x8>;
136                         interrupt-parent = <&ipic>;
137                 };
138
139                 dma@82a8 {
140                         #address-cells = <1>;
141                         #size-cells = <1>;
142                         compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
143                         reg = <0x82a8 4>;
144                         ranges = <0 0x8100 0x1a8>;
145                         interrupt-parent = <&ipic>;
146                         interrupts = <71 8>;
147                         cell-index = <0>;
148                         dma-channel@0 {
149                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
150                                 reg = <0 0x80>;
151                                 cell-index = <0>;
152                                 interrupt-parent = <&ipic>;
153                                 interrupts = <71 8>;
154                         };
155                         dma-channel@80 {
156                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
157                                 reg = <0x80 0x80>;
158                                 cell-index = <1>;
159                                 interrupt-parent = <&ipic>;
160                                 interrupts = <71 8>;
161                         };
162                         dma-channel@100 {
163                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
164                                 reg = <0x100 0x80>;
165                                 cell-index = <2>;
166                                 interrupt-parent = <&ipic>;
167                                 interrupts = <71 8>;
168                         };
169                         dma-channel@180 {
170                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
171                                 reg = <0x180 0x28>;
172                                 cell-index = <3>;
173                                 interrupt-parent = <&ipic>;
174                                 interrupts = <71 8>;
175                         };
176                 };
177
178                 crypto@30000 {
179                         compatible = "fsl,sec2.0";
180                         reg = <0x30000 0x10000>;
181                         interrupts = <11 0x8>;
182                         interrupt-parent = <&ipic>;
183                         fsl,num-channels = <4>;
184                         fsl,channel-fifo-len = <24>;
185                         fsl,exec-units-mask = <0x7e>;
186                         fsl,descriptor-types-mask = <0x01010ebf>;
187                 };
188
189                 ipic: pic@700 {
190                         interrupt-controller;
191                         #address-cells = <0>;
192                         #interrupt-cells = <2>;
193                         reg = <0x700 0x100>;
194                         device_type = "ipic";
195                 };
196
197                 par_io@1400 {
198                         reg = <0x1400 0x100>;
199                         device_type = "par_io";
200                         num-ports = <7>;
201
202                         pio1: ucc_pin@01 {
203                                 pio-map = <
204                         /* port  pin  dir  open_drain  assignment  has_irq */
205                                         0  3  1  0  1  0        /* TxD0 */
206                                         0  4  1  0  1  0        /* TxD1 */
207                                         0  5  1  0  1  0        /* TxD2 */
208                                         0  6  1  0  1  0        /* TxD3 */
209                                         1  6  1  0  3  0        /* TxD4 */
210                                         1  7  1  0  1  0        /* TxD5 */
211                                         1  9  1  0  2  0        /* TxD6 */
212                                         1  10 1  0  2  0        /* TxD7 */
213                                         0  9  2  0  1  0        /* RxD0 */
214                                         0  10 2  0  1  0        /* RxD1 */
215                                         0  11 2  0  1  0        /* RxD2 */
216                                         0  12 2  0  1  0        /* RxD3 */
217                                         0  13 2  0  1  0        /* RxD4 */
218                                         1  1  2  0  2  0        /* RxD5 */
219                                         1  0  2  0  2  0        /* RxD6 */
220                                         1  4  2  0  2  0        /* RxD7 */
221                                         0  7  1  0  1  0        /* TX_EN */
222                                         0  8  1  0  1  0        /* TX_ER */
223                                         0  15 2  0  1  0        /* RX_DV */
224                                         0  16 2  0  1  0        /* RX_ER */
225                                         0  0  2  0  1  0        /* RX_CLK */
226                                         2  9  1  0  3  0        /* GTX_CLK - CLK10 */
227                                         2  8  2  0  1  0>;      /* GTX125 - CLK9 */
228                         };
229                         pio2: ucc_pin@02 {
230                                 pio-map = <
231                         /* port  pin  dir  open_drain  assignment  has_irq */
232                                         0  17 1  0  1  0   /* TxD0 */
233                                         0  18 1  0  1  0   /* TxD1 */
234                                         0  19 1  0  1  0   /* TxD2 */
235                                         0  20 1  0  1  0   /* TxD3 */
236                                         1  2  1  0  1  0   /* TxD4 */
237                                         1  3  1  0  2  0   /* TxD5 */
238                                         1  5  1  0  3  0   /* TxD6 */
239                                         1  8  1  0  3  0   /* TxD7 */
240                                         0  23 2  0  1  0   /* RxD0 */
241                                         0  24 2  0  1  0   /* RxD1 */
242                                         0  25 2  0  1  0   /* RxD2 */
243                                         0  26 2  0  1  0   /* RxD3 */
244                                         0  27 2  0  1  0   /* RxD4 */
245                                         1  12 2  0  2  0   /* RxD5 */
246                                         1  13 2  0  3  0   /* RxD6 */
247                                         1  11 2  0  2  0   /* RxD7 */
248                                         0  21 1  0  1  0   /* TX_EN */
249                                         0  22 1  0  1  0   /* TX_ER */
250                                         0  29 2  0  1  0   /* RX_DV */
251                                         0  30 2  0  1  0   /* RX_ER */
252                                         0  31 2  0  1  0   /* RX_CLK */
253                                         2  2  1  0  2  0   /* GTX_CLK - CLK10 */
254                                         2  3  2  0  1  0   /* GTX125 - CLK4 */
255                                         0  1  3  0  2  0   /* MDIO */
256                                         0  2  1  0  1  0>; /* MDC */
257                         };
258
259                 };
260         };
261
262         qe@e0100000 {
263                 #address-cells = <1>;
264                 #size-cells = <1>;
265                 device_type = "qe";
266                 compatible = "fsl,qe";
267                 ranges = <0x0 0xe0100000 0x00100000>;
268                 reg = <0xe0100000 0x480>;
269                 brg-frequency = <0>;
270                 bus-frequency = <396000000>;
271
272                 muram@10000 {
273                         #address-cells = <1>;
274                         #size-cells = <1>;
275                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
276                         ranges = <0x0 0x00010000 0x0000c000>;
277
278                         data-only@0 {
279                                 compatible = "fsl,qe-muram-data",
280                                              "fsl,cpm-muram-data";
281                                 reg = <0x0 0xc000>;
282                         };
283                 };
284
285                 spi@4c0 {
286                         cell-index = <0>;
287                         compatible = "fsl,spi";
288                         reg = <0x4c0 0x40>;
289                         interrupts = <2>;
290                         interrupt-parent = <&qeic>;
291                         mode = "cpu";
292                 };
293
294                 spi@500 {
295                         cell-index = <1>;
296                         compatible = "fsl,spi";
297                         reg = <0x500 0x40>;
298                         interrupts = <1>;
299                         interrupt-parent = <&qeic>;
300                         mode = "cpu";
301                 };
302
303                 usb@6c0 {
304                         compatible = "qe_udc";
305                         reg = <0x6c0 0x40 0x8b00 0x100>;
306                         interrupts = <11>;
307                         interrupt-parent = <&qeic>;
308                         mode = "slave";
309                 };
310
311                 enet0: ucc@2000 {
312                         device_type = "network";
313                         compatible = "ucc_geth";
314                         cell-index = <1>;
315                         reg = <0x2000 0x200>;
316                         interrupts = <32>;
317                         interrupt-parent = <&qeic>;
318                         local-mac-address = [ 00 00 00 00 00 00 ];
319                         rx-clock-name = "none";
320                         tx-clock-name = "clk9";
321                         phy-handle = <&phy0>;
322                         phy-connection-type = "rgmii-id";
323                         pio-handle = <&pio1>;
324                 };
325
326                 enet1: ucc@3000 {
327                         device_type = "network";
328                         compatible = "ucc_geth";
329                         cell-index = <2>;
330                         reg = <0x3000 0x200>;
331                         interrupts = <33>;
332                         interrupt-parent = <&qeic>;
333                         local-mac-address = [ 00 00 00 00 00 00 ];
334                         rx-clock-name = "none";
335                         tx-clock-name = "clk4";
336                         phy-handle = <&phy1>;
337                         phy-connection-type = "rgmii-id";
338                         pio-handle = <&pio2>;
339                 };
340
341                 mdio@2120 {
342                         #address-cells = <1>;
343                         #size-cells = <0>;
344                         reg = <0x2120 0x18>;
345                         compatible = "fsl,ucc-mdio";
346
347                         phy0: ethernet-phy@00 {
348                                 interrupt-parent = <&ipic>;
349                                 interrupts = <17 0x8>;
350                                 reg = <0x0>;
351                                 device_type = "ethernet-phy";
352                         };
353                         phy1: ethernet-phy@01 {
354                                 interrupt-parent = <&ipic>;
355                                 interrupts = <18 0x8>;
356                                 reg = <0x1>;
357                                 device_type = "ethernet-phy";
358                         };
359                 };
360
361                 qeic: interrupt-controller@80 {
362                         interrupt-controller;
363                         compatible = "fsl,qe-ic";
364                         #address-cells = <0>;
365                         #interrupt-cells = <1>;
366                         reg = <0x80 0x80>;
367                         big-endian;
368                         interrupts = <32 0x8 33 0x8>; // high:32 low:33
369                         interrupt-parent = <&ipic>;
370                 };
371         };
372
373         pci0: pci@e0008500 {
374                 cell-index = <1>;
375                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
376                 interrupt-map = <
377
378                                 /* IDSEL 0x11 AD17 */
379                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
380                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
381                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
382                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
383
384                                 /* IDSEL 0x12 AD18 */
385                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
386                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
387                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
388                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
389
390                                 /* IDSEL 0x13 AD19 */
391                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
392                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
393                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
394                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
395
396                                 /* IDSEL 0x15 AD21*/
397                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
398                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
399                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
400                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
401
402                                 /* IDSEL 0x16 AD22*/
403                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
404                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
405                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
406                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
407
408                                 /* IDSEL 0x17 AD23*/
409                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
410                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
411                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
412                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
413
414                                 /* IDSEL 0x18 AD24*/
415                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
416                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
417                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
418                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
419                 interrupt-parent = <&ipic>;
420                 interrupts = <66 0x8>;
421                 bus-range = <0 0>;
422                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
423                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
424                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
425                 clock-frequency = <66666666>;
426                 #interrupt-cells = <1>;
427                 #size-cells = <2>;
428                 #address-cells = <3>;
429                 reg = <0xe0008500 0x100         /* internal registers */
430                        0xe0008300 0x8>;         /* config space access registers */
431                 compatible = "fsl,mpc8349-pci";
432                 device_type = "pci";
433         };
434 };