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   1 #ifndef _ASM_SPARC64_TOPOLOGY_H
   2 #define _ASM_SPARC64_TOPOLOGY_H
   3
   4 #ifdef CONFIG_NUMA
   5
   6 #include <asm/mmzone.h>
   7
   8 static inline int cpu_to_node(int cpu)
   9 {
  10         return numa_cpu_lookup_table[cpu];
  11 }
  12
  13 #define parent_node(node)       (node)
  14
  15 static inline cpumask_t node_to_cpumask(int node)
  16 {
  17         return numa_cpumask_lookup_table[node];
  18 }
  19
  20 /* Returns a pointer to the cpumask of CPUs on Node 'node'. */
  21 #define node_to_cpumask_ptr(v, node)            \
  22                 cpumask_t *v = &(numa_cpumask_lookup_table[node])
  23
  24 #define node_to_cpumask_ptr_next(v, node)       \
  25                            v = &(numa_cpumask_lookup_table[node])
  26
  27 static inline int node_to_first_cpu(int node)
  28 {
  29         cpumask_t tmp;
  30         tmp = node_to_cpumask(node);
  31         return first_cpu(tmp);
  32 }
  33
  34 struct pci_bus;
  35 #ifdef CONFIG_PCI
  36 extern int pcibus_to_node(struct pci_bus *pbus);
  37 #else
  38 static inline int pcibus_to_node(struct pci_bus *pbus)
  39 {
  40         return -1;
  41 }
  42 #endif
  43
  44 #define pcibus_to_cpumask(bus)  \
  45         (pcibus_to_node(bus) == -1 ? \
  46          CPU_MASK_ALL : \
  47          node_to_cpumask(pcibus_to_node(bus)))
  48
  49 #define SD_NODE_INIT (struct sched_domain) {            \
  50         .min_interval           = 8,                    \
  51         .max_interval           = 32,                   \
  52         .busy_factor            = 32,                   \
  53         .imbalance_pct          = 125,                  \
  54         .cache_nice_tries       = 2,                    \
  55         .busy_idx               = 3,                    \
  56         .idle_idx               = 2,                    \
  57         .newidle_idx            = 0,                    \
  58         .wake_idx               = 1,                    \
  59         .forkexec_idx           = 1,                    \
  60         .flags                  = SD_LOAD_BALANCE       \
  61                                 | SD_BALANCE_FORK       \
  62                                 | SD_BALANCE_EXEC       \
  63                                 | SD_SERIALIZE          \
  64                                 | SD_WAKE_BALANCE,      \
  65         .last_balance           = jiffies,              \
  66         .balance_interval       = 1,                    \
  67 }
  68
  69 #else /* CONFIG_NUMA */
  70
  71 #include <asm-generic/topology.h>
  72
  73 #endif /* !(CONFIG_NUMA) */
  74
  75 #ifdef CONFIG_SMP
  76 #define topology_physical_package_id(cpu)       (cpu_data(cpu).proc_id)
  77 #define topology_core_id(cpu)                   (cpu_data(cpu).core_id)
  78 #define topology_core_siblings(cpu)             (cpu_core_map[cpu])
  79 #define topology_thread_siblings(cpu)           (per_cpu(cpu_sibling_map, cpu))
  80 #define mc_capable()                            (sparc64_multi_core)
  81 #define smt_capable()                           (sparc64_multi_core)
  82 #endif /* CONFIG_SMP */
  83
  84 #define cpu_coregroup_map(cpu)                  (cpu_core_map[cpu])
  85
  86 #endif /* _ASM_SPARC64_TOPOLOGY_H */