2 * Copyright 2004 James Cleverdon, IBM.
3 * Subject to the GNU Public License, v.2
5 * Flat APIC subarch code.
7 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
11 #include <linux/errno.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/hardirq.h>
21 #include <asm/genapic.h>
22 #include <mach_apicdef.h>
25 #include <acpi/acpi_bus.h>
28 static int __init flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
33 static cpumask_t flat_target_cpus(void)
35 return cpu_online_map;
38 static cpumask_t flat_vector_allocation_domain(int cpu)
40 /* Careful. Some cpus do not strictly honor the set of cpus
41 * specified in the interrupt destination when using lowest
42 * priority interrupt delivery mode.
44 * In particular there was a hyperthreading cpu observed to
45 * deliver interrupts to the wrong hyperthread when only one
46 * hyperthread was specified in the interrupt desitination.
48 cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
53 * Set up the logical destination ID.
55 * Intel recommends to set DFR, LDR and TPR before enabling
56 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
57 * document number 292116). So here it goes...
59 static void flat_init_apic_ldr(void)
62 unsigned long num, id;
64 num = smp_processor_id();
66 apic_write(APIC_DFR, APIC_DFR_FLAT);
67 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
68 val |= SET_APIC_LOGICAL_ID(id);
69 apic_write(APIC_LDR, val);
72 static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
74 unsigned long mask = cpus_addr(cpumask)[0];
77 local_irq_save(flags);
78 __send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL);
79 local_irq_restore(flags);
82 static void flat_send_IPI_allbutself(int vector)
84 #ifdef CONFIG_HOTPLUG_CPU
89 if (hotplug || vector == NMI_VECTOR) {
90 cpumask_t allbutme = cpu_online_map;
92 cpu_clear(smp_processor_id(), allbutme);
94 if (!cpus_empty(allbutme))
95 flat_send_IPI_mask(allbutme, vector);
96 } else if (num_online_cpus() > 1) {
97 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
101 static void flat_send_IPI_all(int vector)
103 if (vector == NMI_VECTOR)
104 flat_send_IPI_mask(cpu_online_map, vector);
106 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
109 static unsigned int get_apic_id(unsigned long x)
113 id = (((x)>>24) & 0xFFu);
117 static unsigned long set_apic_id(unsigned int id)
121 x = ((id & 0xFFu)<<24);
125 static unsigned int read_xapic_id(void)
129 id = get_apic_id(apic_read(APIC_ID));
133 static int flat_apic_id_registered(void)
135 return physid_isset(read_xapic_id(), phys_cpu_present_map);
138 static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
140 return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
143 static unsigned int phys_pkg_id(int index_msb)
145 return hard_smp_processor_id() >> index_msb;
148 struct genapic apic_flat = {
150 .acpi_madt_oem_check = flat_acpi_madt_oem_check,
151 .int_delivery_mode = dest_LowestPrio,
152 .int_dest_mode = (APIC_DEST_LOGICAL != 0),
153 .target_cpus = flat_target_cpus,
154 .vector_allocation_domain = flat_vector_allocation_domain,
155 .apic_id_registered = flat_apic_id_registered,
156 .init_apic_ldr = flat_init_apic_ldr,
157 .send_IPI_all = flat_send_IPI_all,
158 .send_IPI_allbutself = flat_send_IPI_allbutself,
159 .send_IPI_mask = flat_send_IPI_mask,
160 .send_IPI_self = apic_send_IPI_self,
161 .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
162 .phys_pkg_id = phys_pkg_id,
163 .get_apic_id = get_apic_id,
164 .set_apic_id = set_apic_id,
165 .apic_id_mask = (0xFFu<<24),
169 * Physflat mode is used when there are more than 8 CPUs on a AMD system.
170 * We cannot use logical delivery in this case because the mask
171 * overflows, so use physical mode.
173 static int __init physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
177 * Quirk: some x86_64 machines can only use physical APIC mode
178 * regardless of how many processors are present (x86_64 ES7000
181 if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
182 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL))
189 static cpumask_t physflat_target_cpus(void)
191 return cpu_online_map;
194 static cpumask_t physflat_vector_allocation_domain(int cpu)
196 return cpumask_of_cpu(cpu);
199 static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
201 send_IPI_mask_sequence(cpumask, vector);
204 static void physflat_send_IPI_allbutself(int vector)
206 cpumask_t allbutme = cpu_online_map;
208 cpu_clear(smp_processor_id(), allbutme);
209 physflat_send_IPI_mask(allbutme, vector);
212 static void physflat_send_IPI_all(int vector)
214 physflat_send_IPI_mask(cpu_online_map, vector);
217 static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
222 * We're using fixed IRQ delivery, can only return one phys APIC ID.
223 * May as well be the first.
225 cpu = first_cpu(cpumask);
226 if ((unsigned)cpu < nr_cpu_ids)
227 return per_cpu(x86_cpu_to_apicid, cpu);
232 struct genapic apic_physflat = {
233 .name = "physical flat",
234 .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
235 .int_delivery_mode = dest_Fixed,
236 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
237 .target_cpus = physflat_target_cpus,
238 .vector_allocation_domain = physflat_vector_allocation_domain,
239 .apic_id_registered = flat_apic_id_registered,
240 .init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
241 .send_IPI_all = physflat_send_IPI_all,
242 .send_IPI_allbutself = physflat_send_IPI_allbutself,
243 .send_IPI_mask = physflat_send_IPI_mask,
244 .send_IPI_self = apic_send_IPI_self,
245 .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
246 .phys_pkg_id = phys_pkg_id,
247 .get_apic_id = get_apic_id,
248 .set_apic_id = set_apic_id,
249 .apic_id_mask = (0xFFu<<24),